diff --git a/LICENSE.md b/LICENSE.md index a67c417dd..377b8c909 100644 --- a/LICENSE.md +++ b/LICENSE.md @@ -12,7 +12,7 @@ | rm_motor_speed
(pre-compiled libraries) | Renesas Electronics Corporation | [Renesas Software License Agreement](https://www.renesas.com/us/en/document/oth/disclaimer002)| | rm_zmod4xxx
(pre-compiled libraries) | Renesas Electronics Corporation | [Renesas Software License Agreement](https://www.renesas.com/us/en/document/oth/disclaimer002)| | Third-Party components included in the packs | -| [CMSIS](https://github.com/ARM-software/CMSIS_5) | ARM Limited | Apache-2.0 License | +| [CMSIS](https://github.com/ARM-software/CMSIS_6) | ARM Limited | Apache-2.0 License | | [CMSIS Pack](https://github.com/Open-CMSIS-Pack) | ARM Limited | Apache-2.0 License | | [CMSIS DSP](https://github.com/ARM-software/CMSIS-DSP)| ARM Limited | Apache-2.0 License | | [CMSISNN](https://github.com/ARM-software/CMSIS-NN) | ARM Limited | Apache-2.0 License | diff --git a/README.md b/README.md index 9e7fc5d4e..c56c089ae 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe ### Current Release -[FSP v5.3.0](https://github.com/renesas/fsp/releases/tag/v5.3.0) +[FSP v5.4.0](https://github.com/renesas/fsp/releases/tag/v5.4.0) ### Supported RA MCU Kits @@ -25,8 +25,10 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe - FPB-RA2E3 - FPB-RA4E1 - FPB-RA4E2 +- FPB-RA4T1 - FPB-RA6E1 - FPB-RA6E2 +- FPB-RA6T3 - EK-RA2A1 - EK-RA2A2 - EK-RA2E1 @@ -101,7 +103,7 @@ When using the zipped version of the packs the zip file should be extracted into #### For new users that are using FSP with e² studio -1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v5.3.0). +1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v5.4.0). 2. Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required. #### If using RA Smart Configurator (RASC) with IAR Embedded Workbench or Keil MDK #### diff --git a/SUPPORTED_SOFTWARE.md b/SUPPORTED_SOFTWARE.md index fd0236109..ecf75356c 100644 --- a/SUPPORTED_SOFTWARE.md +++ b/SUPPORTED_SOFTWARE.md @@ -2,7 +2,7 @@ ### FSP Top Level Modules * AI - * [Arm CMSIS5 NN Library Source](https://arm-software.github.io/CMSIS-NN/latest/index.html) + * [Arm CMSIS NN Library Source](https://arm-software.github.io/CMSIS-NN/latest/index.html) * [Data Collector (rm_rai_data_collector)](https://renesas.github.io/fsp/group___r_m___r_a_i___d_a_t_a___c_o_l_l_e_c_t_o_r.html) * [Data Shipper (rm_rai_data_shipper)](https://renesas.github.io/fsp/group___r_m___r_a_i___d_a_t_a___s_h_i_p_p_e_r.html) * Analog @@ -27,18 +27,18 @@ * [CTSU (r_ctsu)](https://renesas.github.io/fsp/group___c_t_s_u.html) * [Touch (rm_touch)](https://renesas.github.io/fsp/group___t_o_u_c_h.html) * Connectivity - * [Azure RTOS USBX DFU](https://docs.microsoft.com/en-us/azure/rtos/usbx/) - * [Azure RTOS USBX HCDC](https://docs.microsoft.com/en-us/azure/rtos/usbx/) - * [Azure RTOS USBX HHID](https://docs.microsoft.com/en-us/azure/rtos/usbx/) - * [Azure RTOS USBX HPRN](https://docs.microsoft.com/en-us/azure/rtos/usbx/) - * [Azure RTOS USBX HUVC](https://docs.microsoft.com/en-us/azure/rtos/usbx/) - * [Azure RTOS USBX OTG CDC](https://docs.microsoft.com/en-us/azure/rtos/usbx/) - * [Azure RTOS USBX OTG HID](https://docs.microsoft.com/en-us/azure/rtos/usbx/) - * [Azure RTOS USBX PAUD](https://docs.microsoft.com/en-us/azure/rtos/usbx/) - * [Azure RTOS USBX PCDC](https://docs.microsoft.com/en-us/azure/rtos/usbx/) - * [Azure RTOS USBX PHID](https://docs.microsoft.com/en-us/azure/rtos/usbx/) - * [Azure RTOS USBX PMSC](https://docs.microsoft.com/en-us/azure/rtos/usbx/) - * [Azure RTOS USBX PPRN](https://docs.microsoft.com/en-us/azure/rtos/usbx/) + * [Azure RTOS USBX DFU](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/usbx/index.md) + * [Azure RTOS USBX HCDC](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/usbx/index.md) + * [Azure RTOS USBX HHID](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/usbx/index.md) + * [Azure RTOS USBX HPRN](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/usbx/index.md) + * [Azure RTOS USBX HUVC](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/usbx/index.md) + * [Azure RTOS USBX OTG CDC](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/usbx/index.md) + * [Azure RTOS USBX OTG HID](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/usbx/index.md) + * [Azure RTOS USBX PAUD](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/usbx/index.md) + * [Azure RTOS USBX PCDC](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/usbx/index.md) + * [Azure RTOS USBX PHID](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/usbx/index.md) + * [Azure RTOS USBX PMSC](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/usbx/index.md) + * [Azure RTOS USBX PPRN](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/usbx/index.md) * [CAN (r_can)](https://renesas.github.io/fsp/group___c_a_n.html) * [CAN FD (r_canfd)](https://renesas.github.io/fsp/group___c_a_n_f_d.html) * [CAN FD Lite (r_canfdlite)](https://renesas.github.io/fsp/group___c_a_n_f_d.html) @@ -57,6 +57,7 @@ * [IICA Master (r_iica_master)](https://renesas.github.io/fsp/group___i_i_c_a___m_a_s_t_e_r.html) * [IICA Slave (r_iica_slave)](https://renesas.github.io/fsp/group___i_i_c_a___s_l_a_v_e.html) * [LIN (r_sci_b_lin)](https://renesas.github.io/fsp/group___s_c_i___b___l_i_n.html) + * [SMBus Communication Device (rm_comms_smbus)](https://renesas.github.io/fsp/group___r_m___c_o_m_m_s___s_m_b_u_s.html) * [SMCI (r_sci_smci)](https://renesas.github.io/fsp/group___s_c_i___s_m_c_i.html) * [SPI (r_sau_spi)](https://renesas.github.io/fsp/group___s_a_u___s_p_i.html) * [SPI (r_sci_b_spi)](https://renesas.github.io/fsp/group___s_c_i___b___s_p_i.html) @@ -68,7 +69,7 @@ * [UART (r_sci_uart)](https://renesas.github.io/fsp/group___s_c_i___u_a_r_t.html) * [UART (r_uarta)](https://renesas.github.io/fsp/group___u_a_r_t_a.html) * [UART Communication Device (rm_comms_uart)](https://renesas.github.io/fsp/group___r_m___c_o_m_m_s___u_a_r_t.html) - * [USB Composite (r_usb_composite)](https://renesas.github.io/fsp/group___u_s_b.html) + * [USB Composite (r_usb_composite)](https://renesas.github.io/fsp/group___u_s_b___c_o_m_p_o_s_i_t_e.html) * [USB HCDC (r_usb_hcdc)](https://renesas.github.io/fsp/group___u_s_b___h_c_d_c.html) * [USB HHID (r_usb_hhid)](https://renesas.github.io/fsp/group___u_s_b___h_h_i_d.html) * [USB HMSC (r_usb_hmsc)](https://renesas.github.io/fsp/group___u_s_b___h_m_s_c.html) @@ -80,10 +81,10 @@ * [USB PPRN (r_usb_pprn)](https://renesas.github.io/fsp/group___u_s_b___p_p_r_n.html) * [USB PVND (r_usb_pvnd)](https://renesas.github.io/fsp/group___u_s_b___p_v_n_d.html) * DSP - * [Arm CMSIS5 DSP Library Source](http://www.keil.com/pack/doc/CMSIS/DSP/html/index.html) + * [Arm CMSIS DSP Library Source](https://arm-software.github.io/CMSIS-DSP/latest/) * [IIR Filter Accelerator (r_iirfa)](https://renesas.github.io/fsp/group___i_i_r_f_a.html) * Graphics - * [Azure RTOS GUIX](https://docs.microsoft.com/en-us/azure/rtos/guix/) + * [Azure RTOS GUIX](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/guix/index.md) * [Capture Engine Unit (r_ceu)](https://renesas.github.io/fsp/group___c_e_u.html) * [D/AVE 2D (r_drw)](https://www.tes-dst.com/technology-products/gpus/d/ave-2d/) * [D/AVE 2D Port Interface (r_drw)](https://renesas.github.io/fsp/group___d_r_w.html) @@ -100,7 +101,7 @@ * [Clock Accuracy Circuit (r_cac)](https://renesas.github.io/fsp/group___c_a_c.html) * [Data Operation Circuit (r_doc)](https://renesas.github.io/fsp/group___d_o_c.html) * [Independent Watchdog (r_iwdt)](https://renesas.github.io/fsp/group___i_w_d_t.html) - * [Low/Programmable Voltage Detection (r_lvd)](https://renesas.github.io/fsp/group___l_v_d.html) + * [Low/Programmable Voltage Detection (r_lvd)](https://renesas.github.io/fsp/group___l_v_d-_p_v_d.html) * [Watchdog (r_wdt)](https://renesas.github.io/fsp/group___w_d_t.html) * Motor * [120-degree conduction control sensorless (rm_motor_120_control_sensorless)](https://renesas.github.io/fsp/group___m_o_t_o_r__120___c_o_n_t_r_o_l___s_e_n_s_o_r_l_e_s_s.html) @@ -174,40 +175,40 @@ * [BLE Mesh Network (rm_ble_mesh_network)](https://renesas.github.io/fsp/group___r_m___b_l_e___m_e_s_h___n_e_t_w_o_r_k.html) * [BLE Mesh Provision (rm_ble_mesh_provision)](https://renesas.github.io/fsp/group___r_m___b_l_e___m_e_s_h___p_r_o_v_i_s_i_o_n.html) * [BLE Mesh Upper Trans (rm_ble_mesh_upper_trans)](https://renesas.github.io/fsp/group___r_m___b_l_e___m_e_s_h___u_p_p_e_r___t_r_a_n_s.html) - * [AWS Cellular Interface on RYZ (rm_cellular_ryz_aws)](https://renesas.github.io/fsp/group___r_m___c_e_l_l_u_l_a_r___r_y_z___a_w_s.html) + * [AWS Cellular Interface on RYZ (rm_cellular_ryz_aws) [Deprecated]](https://renesas.github.io/fsp/group___r_m___c_e_l_l_u_l_a_r___r_y_z___a_w_s.html) * [AWS Core HTTP](https://docs.aws.amazon.com/freertos/latest/userguide/core-http.html) * [AWS Core MQTT](https://docs.aws.amazon.com/freertos/latest/userguide/coremqtt.html) * [AWS IoT Over-the-air Update Library](https://github.com/aws/ota-for-aws-iot-embedded-sdk) * [AWS Transport Interface on MbedTLS/PKCS11 (rm_aws_transport_interface_port)](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html) - * [Azure EWF Adapter on RYZ014A](https://renesas.github.io/fsp/group___r_m___a_z_u_r_e___e_w_f___r_y_z.html) - * [Azure EWF Adapter on RYZ024A](https://renesas.github.io/fsp/group___r_m___a_z_u_r_e___e_w_f___r_y_z.html) - * [Azure RTOS NetX Duo Auto IP](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-auto-ip/chapter1) - * [Azure RTOS NetX Duo BSD Support](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-bsd/chapter1) - * [Azure RTOS NetX Duo Common](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/) - * [Azure RTOS NetX Duo DHCP IPv4 Client](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-dhcp-client/chapter1) - * [Azure RTOS NetX Duo DHCP IPv4 Server](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-dhcp-server/chapter1) - * [Azure RTOS NetX Duo DHCP IPv6 Client](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-dhcpv6-client/chapter1) - * [Azure RTOS NetX Duo DHCP IPv6 Server](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-dhcpv6-server/chapter1) - * [Azure RTOS NetX Duo DNS Client](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-dns/chapter1) - * [Azure RTOS NetX Duo FTP Client](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-ftp/chapter1) - * [Azure RTOS NetX Duo FTP Server](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-ftp/chapter1) - * [Azure RTOS NetX Duo HTTP Client](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-http/chapter1) - * [Azure RTOS NetX Duo HTTP Server](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-http/chapter1) - * [Azure RTOS NetX Duo IP Instance](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/chapter3) - * [Azure RTOS NetX Duo IoT Middleware](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/overview-netx-duo) - * [Azure RTOS NetX Duo MQTT Client](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-mqtt/chapter1) - * [Azure RTOS NetX Duo NAT](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-nat/chapter1) - * [Azure RTOS NetX Duo POP3 Client](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-pop3-client/chapter1) - * [Azure RTOS NetX Duo Packet Pool Instance](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/chapter3) - * [Azure RTOS NetX Duo SMTP Client](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-smtp-client/chapter1) - * [Azure RTOS NetX Duo SNMP Agent](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-snmp/chapter1) - * [Azure RTOS NetX Duo SNTP Client](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-sntp-client/chapter1) - * [Azure RTOS NetX Duo TFTP Client](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-tftp/chapter1) - * [Azure RTOS NetX Duo TFTP Server](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-tftp/chapter1) - * [Azure RTOS NetX Duo Telnet Client](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-telnet/chapter1) - * [Azure RTOS NetX Duo Telnet Server](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-telnet/chapter1) - * [Azure RTOS NetX Duo Web HTTP/HTTPS Client](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-web-http/chapter1) - * [Azure RTOS NetX Duo Web HTTP/HTTPS Server](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-web-http/chapter1) + * [Azure EWF Adapter on RYZ014A [Deprecated]](https://renesas.github.io/fsp/group___r_m___a_z_u_r_e___e_w_f___r_y_z.html) + * [Azure EWF Adapter on RYZ024A [Deprecated]](https://renesas.github.io/fsp/group___r_m___a_z_u_r_e___e_w_f___r_y_z.html) + * [Azure RTOS NetX Duo Auto IP](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-auto-ip/chapter1.md) + * [Azure RTOS NetX Duo BSD Support](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-bsd/chapter1.md) + * [Azure RTOS NetX Duo Common](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/index.md) + * [Azure RTOS NetX Duo DHCP IPv4 Client](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-dhcp-client/chapter1.md) + * [Azure RTOS NetX Duo DHCP IPv4 Server](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-dhcp-server/chapter1.md) + * [Azure RTOS NetX Duo DHCP IPv6 Client](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-dhcpv6-client/chapter1.md) + * [Azure RTOS NetX Duo DHCP IPv6 Server](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-dhcpv6-server/chapter1.md) + * [Azure RTOS NetX Duo DNS Client](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-dns/chapter1.md) + * [Azure RTOS NetX Duo FTP Client](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-ftp/chapter1.md) + * [Azure RTOS NetX Duo FTP Server](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-ftp/chapter1.md) + * [Azure RTOS NetX Duo HTTP Client](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-http/Chapter1.md) + * [Azure RTOS NetX Duo HTTP Server](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-http/Chapter1.md) + * [Azure RTOS NetX Duo IP Instance](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/chapter3.md) + * [Azure RTOS NetX Duo IoT Middleware](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/index.md) + * [Azure RTOS NetX Duo MQTT Client](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-mqtt/chapter1.md) + * [Azure RTOS NetX Duo NAT](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-nat/chapter1.md) + * [Azure RTOS NetX Duo POP3 Client](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-pop3-client/chapter1.md) + * [Azure RTOS NetX Duo Packet Pool Instance](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/chapter3.md) + * [Azure RTOS NetX Duo SMTP Client](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-smtp-client/chapter1.md) + * [Azure RTOS NetX Duo SNMP Agent](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-snmp/chapter1.md) + * [Azure RTOS NetX Duo SNTP Client](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-sntp-client/chapter1.md) + * [Azure RTOS NetX Duo TFTP Client](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-tftp/chapter1.md) + * [Azure RTOS NetX Duo TFTP Server](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-tftp/chapter1.md) + * [Azure RTOS NetX Duo Telnet Client](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-telnet/chapter1.md) + * [Azure RTOS NetX Duo Telnet Server](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-telnet/chapter1.md) + * [Azure RTOS NetX Duo Web HTTP/HTTPS Client](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-web-http/chapter1.md) + * [Azure RTOS NetX Duo Web HTTP/HTTPS Server](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-web-http/chapter1.md) * [BLE Abstraction (rm_ble_abs)](https://renesas.github.io/fsp/group___b_l_e___a_b_s.html) * [BLE SPP Transport on SPI (rm_ble_abs_spp_transport)](https://renesas.github.io/fsp/group___b_l_e___a_b_s.html) * [BLE SPP Transport on UART (rm_ble_abs_spp_transport)](https://renesas.github.io/fsp/group___b_l_e___a_b_s.html) @@ -231,8 +232,8 @@ * [FreeRTOS Heap 5](https://www.freertos.org/a00111.html#heap_5) * [FreeRTOS Port (rm_freertos_port)](https://renesas.github.io/fsp/group___r_m___f_r_e_e_r_t_o_s___p_o_r_t.html) * Security - * [Azure RTOS NetX Crypto](https://docs.microsoft.com/en-us/azure/rtos/netx/netx-crypto/chapter1) - * [Azure RTOS NetX Secure](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-secure-tls/chapter1) + * [Azure RTOS NetX Crypto](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-crypto/chapter1.md) + * [Azure RTOS NetX Secure](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-secure-tls/chapter1.md) * [MbedTLS](https://www.trustedfirmware.org/projects/mbed-tls/) * [MbedTLS (Crypto Only)](https://github.com/ARMmbed/mbed-crypto/blob/mbedcrypto-2.0.0/docs/getting_started.md) * [RSIP Protected Mode (r_rsip)](https://renesas.github.io/fsp/group___r_s_i_p___p_r_o_t_e_c_t_e_d.html) @@ -252,10 +253,10 @@ * [RRH46410 Gas Sensor Module (rm_rrh46410)](https://renesas.github.io/fsp/group___r_m___r_r_h46410.html) * [ZMOD4XXX Gas Sensor (rm_zmod4xxx)](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) * Storage - * [Azure RTOS FileX on Block Media](https://docs.microsoft.com/en-us/azure/rtos/filex/) - * [Azure RTOS FileX on LevelX NOR](https://docs.microsoft.com/en-us/azure/rtos/filex/) - * [Azure RTOS FileX on USBX](https://docs.microsoft.com/en-us/azure/rtos/filex/overview-filex) - * [Azure RTOS LevelX NOR on SPI Memory](https://docs.microsoft.com/en-us/azure/rtos/levelx/) + * [Azure RTOS FileX on Block Media](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/filex/index.md) + * [Azure RTOS FileX on LevelX NOR](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/filex/index.md) + * [Azure RTOS FileX on USBX](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/filex/index.md) + * [Azure RTOS LevelX NOR on SPI Memory](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/levelx/index.md) * [Block Media Custom Implementation (rm_block_media_user)](https://renesas.github.io/fsp/group___r_m___b_l_o_c_k___m_e_d_i_a___u_s_e_r.html) * [Block Media RAM Implementation (rm_block_media_ram)](https://renesas.github.io/fsp/group___r_m___b_l_o_c_k___m_e_d_i_a___r_a_m.html) * [Block Media SD/MMC (rm_block_media_sdmmc)](https://renesas.github.io/fsp/group___r_m___b_l_o_c_k___m_e_d_i_a___s_d_m_m_c.html) @@ -301,15 +302,17 @@ * [MCUboot ASN.1 Parser](https://github.com/mcu-tools/mcuboot) * [MCUboot Custom Crypto (Protected Mode)](https://renesas.github.io/fsp/group___r_m___m_c_u_b_o_o_t___p_o_r_t.html) * [MCUboot Example Keys (NOT FOR PRODUCTION)](https://github.com/mcu-tools/mcuboot) + * [MCUboot External Memory (OSPI_B)](https://renesas.github.io/fsp/) * [MCUboot External Memory (QSPI)](https://renesas.github.io/fsp/) * [MCUboot Port for RA (rm_mcuboot_port)](https://renesas.github.io/fsp/group___r_m___m_c_u_b_o_o_t___p_o_r_t.html) * [MCUboot config](https://github.com/mcu-tools/mcuboot) * [MCUboot logging](https://github.com/mcu-tools/mcuboot) * [MCUboot sysflash](https://github.com/mcu-tools/mcuboot) * Connectivity - * [Azure RTOS USBX HMSC](https://docs.microsoft.com/en-us/azure/rtos/usbx/) - * [Azure RTOS USBX OTG MSC](https://docs.microsoft.com/en-us/azure/rtos/usbx/) + * [Azure RTOS USBX HMSC](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/usbx/index.md) + * [Azure RTOS USBX OTG MSC](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/usbx/index.md) * [Azure RTOS USBX Port (rm_usbx_port)](https://renesas.github.io/fsp/group___u_s_b_x.html) + * [SMBus Resources control (rm_comms_smbus)](https://renesas.github.io/fsp/group___r_m___c_o_m_m_s___s_m_b_u_s.html) * [USB (r_usb_basic)](https://renesas.github.io/fsp/group___u_s_b.html) * [USB HCDC (r_usb_hcdc)](https://renesas.github.io/fsp/group___u_s_b___h_c_d_c.html) * [USB HHID (r_usb_hhid)](https://renesas.github.io/fsp/group___u_s_b___h_h_i_d.html) @@ -370,13 +373,13 @@ * [DA14531 GTL Driver Layer](https://renesas.github.io/fsp/group___b_l_e___a_b_s___g_t_l.html) * [DA16XXX Transport on UART (rm_at_transport_da16xxx_uart)](https://renesas.github.io/fsp/group___a_t___t_r_a_n_s_p_o_r_t___d_a16_x_x_x___u_a_r_t.html) * [FreeRTOS+TCP Wrapper to r_ether (rm_freertos_plus_tcp)](https://renesas.github.io/fsp/group___f_r_e_e_r_t_o_s___p_l_u_s___t_c_p.html) - * [NetX Duo Ethernet Driver (rm_netxduo_ether)](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/chapter5) + * [NetX Duo Ethernet Driver (rm_netxduo_ether)](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/chapter5.md) * [NetX Duo WiFi Driver (rm_netxduo_wifi)](https://renesas.github.io/fsp/group___r_m___n_e_t_x_d_u_o___w_i_f_i.html) * [RYZ012 SPP Driver Layer](https://renesas.github.io/fsp/group___b_l_e___a_b_s___s_p_p.html) * [TinyCBOR](https://github.com/intel/tinycbor/) * [WiFi Common](https://docs.aws.amazon.com/freertos/latest/userguide/freertos-wifi.html) * [WiFi DA16XXX Framework Driver (rm_wifi_da16xxx)](https://renesas.github.io/fsp/group___w_i_f_i___d_a16_x_x_x.html) - * [WiFi Onchip Silex Driver using r_sci_uart (rm_wifi_onchip_silex)](https://renesas.github.io/fsp/group___w_i_f_i___o_n_c_h_i_p___s_i_l_e_x.html) + * [WiFi Onchip Silex Driver using UART (rm_wifi_onchip_silex)](https://renesas.github.io/fsp/group___w_i_f_i___o_n_c_h_i_p___s_i_l_e_x.html) * Security * [Azure RTOS NetX Crypto HW Acceleration (rm_netx_secure_crypto)](https://renesas.github.io/fsp/group___r_m___n_e_t_x___s_e_c_u_r_e___c_r_y_p_t_o.html) * [Azure RTOS NetX Crypto Software Only](https://renesas.github.io/fsp/group___r_m___n_e_t_x___s_e_c_u_r_e___c_r_y_p_t_o.html) @@ -420,7 +423,7 @@ * [ZMOD4510 OAQ 2nd Generation (rm_zmod4xxx)](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) * Storage * [AWS OTA PAL (rm_aws_ota_pal_mcuboot)](https://renesas.github.io/fsp/group___r_m___a_w_s___o_t_a___p_a_l___m_c_u_b_o_o_t.html) - * [Azure RTOS FileX Stub for NetX Duo](https://docs.microsoft.com/en-us/azure/rtos/filex/) + * [Azure RTOS FileX Stub for NetX Duo](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/filex/index.md) * [Block Media Custom Implementation](https://renesas.github.io/fsp/group___r_m___b_l_o_c_k___m_e_d_i_a___u_s_e_r.html) * [FileX I/O (rm_filex_block_media)](https://renesas.github.io/fsp/group___r_m___f_i_l_e_x___b_l_o_c_k___m_e_d_i_a.html) * [FileX I/O (rm_filex_levelx_nor)](https://renesas.github.io/fsp/group___r_m___f_i_l_e_x___l_e_v_e_l_x___n_o_r.html) @@ -428,7 +431,7 @@ * [LevelX NOR Port (rm_levelx_nor_spi)](https://renesas.github.io/fsp/group___r_m___l_e_v_e_l_x___n_o_r___s_p_i.html) * [LittleFS on Flash (rm_littlefs_flash)](https://renesas.github.io/fsp/group___r_m___l_i_t_t_l_e_f_s___f_l_a_s_h.html) * System - * [Arm CMSIS5 Core (M)](https://arm-software.github.io/CMSIS_5/Core/html/index.html) + * [Arm CMSIS6 Core (M)](https://arm-software.github.io/CMSIS_6/latest/Core/index.html) * Timers * [TAU PWM Channel Configuration (r_tau_pwm)](https://renesas.github.io/fsp/group___t_a_u___p_w_m.html) * Transfer diff --git a/ra/board/ra8d1_ek/board.h b/ra/board/ra8d1_ek/board.h index 6d57ed340..4ffdb6c3d 100644 --- a/ra/board/ra8d1_ek/board.h +++ b/ra/board/ra8d1_ek/board.h @@ -23,9 +23,9 @@ /* BSP Board Specific Includes. */ #include "board_init.h" -#include "board_sdram.h" #include "board_leds.h" #include "board_ethernet_phy.h" +#include "../../src/bsp/mcu/all/board_sdram.h" /*********************************************************************************************************************** * Macro definitions diff --git a/ra/board/ra8d1_ek/board_sdram.c b/ra/board/ra8d1_ek/board_sdram.c deleted file mode 100644 index c060a37ff..000000000 --- a/ra/board/ra8d1_ek/board_sdram.c +++ /dev/null @@ -1,232 +0,0 @@ -/* -* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -#include "r_ioport.h" -#include "bsp_cfg.h" -#include "bsp_pin_cfg.h" - -#include "board_sdram.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* SDRAM size, in bytes */ -#define SDRAM_SIZE (64 * 1024 * 1024) - -/* - * Set ACTIVE-to-PRECHARGE command (tRAS) timing - * e.g. tRAS = 42ns -> 6cycles are needed at SDCLK 120MHz - * tRAS = 37ns -> 5cycles are needed at SDCLK 120MHz - */ -#define BSP_PRV_SDRAM_TRAS (6U) - -/* - * Set ACTIVE-to-READ or WRITE delay tRCD (tRCD) timing - * e.g. tRCD = 18ns -> 3cycles are needed at SDCLK 120MHz - * tRCD = 15ns -> 2cycles are needed at SDCLK 120MHz - */ -#define BSP_PRV_SDRAM_TRCD (3U) - -/* - * Set PRECHARGE command period (tRP) timing - * e.g. tRP = 18ns -> 3cycles are needed at SDCLK 120MHz - * tRP = 15ns -> 2cycles are needed at SDCLK 120MHz - */ -#define BSP_PRV_SDRAM_TRP (3U) - -/* - * Set WRITE recovery time (tWR) timing - * e.g. tWR = 1CLK + 6ns -> 2cycles are needed at SDCLK 120MHz - * tWR = 1CLK + 7ns -> 2cycles are needed at SDCLK 120MHz - */ -#define BSP_PRV_SDRAM_TWR (2U) - -/* - * Set CAS (READ) latency (CL) timing - * e.g. CL = 18ns -> 3cycles are needed at SDCLK 120MHz - * e.g. CL = 15ns -> 2cycles are needed at SDCLK 120MHz - */ -#define BSP_PRV_SDRAM_CL (3U) - -/* - * Set AUTO REFRESH period (tRFC) timing - * e.g. tRFC = 60nS -> 8cycles are needed at SDCLK 120MHz - * tRFC = 66nS -> 8cycles are needed at SDCLK 120MHz - */ -#define BSP_PRV_SDRAM_TRFC (8U) - -/* - * Set Average Refresh period - * e.g. tREF = 64ms/8192rows -> 7.8125us/each row. 937cycles are needed at SDCLK 120MHz - */ -#define BSP_PRV_SDRAM_REF_CMD_INTERVAL (937U) - -/* - * Set Auto-Refresh issue times in initialization sequence needed for SDRAM device - * Typical SDR SDRAM device needs twice of Auto-Refresh command issue - */ -#define BSP_PRV_SDRAM_SDIR_REF_TIMES (2U) - -/* - * Set RAW address offset - * Available settings are - * 8 : 8-bit - * 9 : 9-bit - * 10 : 10-bit - * 11 : 11-bit - */ -#define BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET (10U) - -/* - * Select endian mode for SDRAM address space - * 0 : Endian of SDRAM address space is the same as the endian of operating mode - * 1 : Endian of SDRAM address space is not the endian of operating mode - */ -#define BSP_PRV_SDRAM_ENDIAN_MODE (0U) - -/* - * Select access mode - * Typically Continuous access should be enabled to get better SDRAM bandwidth - * 0: Continuous access is disabled - * 1: Continuous access is enabled - */ -#define BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE (1U) - -/* - * Select bus width - * 0: 16-bit - * 1: 32-bit - * 2: 8-bit - */ -#define BSP_PRV_SDRAM_BUS_WIDTH (0U) - -#if ((BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET != 8U) && (BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET != 9U) \ - && (BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET != 10U) && (BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET > 11U)) - #error "BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET must be either of 8,9,10 or 11" -#endif - -#if ((BSP_PRV_SDRAM_BUS_WIDTH != 0) && (BSP_PRV_SDRAM_BUS_WIDTH != 1U) && (BSP_PRV_SDRAM_BUS_WIDTH != 2U)) - #error "BSP_PRV_SDRAM_BUS_WIDTH must be either of 0(16-bit) or 1(32-bit) or 2(8-bit)" -#endif - -#if ((BSP_PRV_SDRAM_ENDIAN_MODE != 0) && (BSP_PRV_SDRAM_ENDIAN_MODE != 1)) - #error \ - "BSP_PRV_SDRAM_ENDIAN_MODE must be either of 0(same endian as operating mode) or 2(another endian against operating mode)" -#endif - -#if ((BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE != 0) && (BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE != 1)) - #error \ - "BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE must be either of 0(continuous access is disabled) or 1(continuous access is enabled)" -#endif - -#define BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC (1U) /* MR.M9 : Single Location Access */ -#define BSP_PRV_SDRAM_MR_OP_MODE (0U) /* MR.M8:M7 : Standard Operation */ -#define BSP_PRV_SDRAM_MR_BT_SEQUENCTIAL (0U) /* MR.M3 Burst Type : Sequential */ -#define BSP_PRV_SDRAM_MR_BURST_LENGTH (0U) /* MR.M2:M0 Burst Length: 0(1 burst) */ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables (to be accessed by other files) - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Private global variables and functions - **********************************************************************************************************************/ - -void bsp_sdram_init (void) -{ - /** Setting for SDRAM initialization sequence */ -#if (BSP_PRV_SDRAM_TRP < 3) - R_BUS->SDRAM.SDIR_b.PRC = 3U; -#else - R_BUS->SDRAM.SDIR_b.PRC = BSP_PRV_SDRAM_TRP - 3U; -#endif - - while (R_BUS->SDRAM.SDSR) - { - /* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDIR modification. */ - } - - R_BUS->SDRAM.SDIR_b.ARFC = BSP_PRV_SDRAM_SDIR_REF_TIMES; - - while (R_BUS->SDRAM.SDSR) - { - /* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDIR modification. */ - } - -#if (BSP_PRV_SDRAM_TRFC < 3) - R_BUS->SDRAM.SDIR_b.ARFI = 0U; -#else - R_BUS->SDRAM.SDIR_b.ARFI = BSP_PRV_SDRAM_TRFC - 3U; -#endif - - while (R_BUS->SDRAM.SDSR) - { - /* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDICR modification. */ - } - - /** Start SDRAM initialization sequence. - * Following operation is automatically done when set SDICR.INIRQ bit. - * Perform a PRECHARGE ALL command and wait at least tRP time. - * Issue an AUTO REFRESH command and wait at least tRFC time. - * Issue an AUTO REFRESH command and wait at least tRFC time. - */ - R_BUS->SDRAM.SDICR_b.INIRQ = 1U; - while (R_BUS->SDRAM.SDSR_b.INIST) - { - /* Wait the end of initialization sequence. */ - } - - /** Setting for SDRAM controller */ - R_BUS->SDRAM.SDCCR_b.BSIZE = BSP_PRV_SDRAM_BUS_WIDTH; /* set SDRAM bus width */ - R_BUS->SDRAM.SDAMOD_b.BE = BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE; /* enable continuous access */ - R_BUS->SDRAM.SDCMOD_b.EMODE = BSP_PRV_SDRAM_ENDIAN_MODE; /* set endian mode for SDRAM address space */ - - while (R_BUS->SDRAM.SDSR) - { - /* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDMOD modification. */ - } - - /** Using LMR command, program the mode register */ - R_BUS->SDRAM.SDMOD = ((((uint16_t) (BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC << 9) | - (uint16_t) (BSP_PRV_SDRAM_MR_OP_MODE << 7)) | - (uint16_t) (BSP_PRV_SDRAM_CL << 4)) | - (uint16_t) (BSP_PRV_SDRAM_MR_BT_SEQUENCTIAL << 3)) | - (uint16_t) (BSP_PRV_SDRAM_MR_BURST_LENGTH << 0); - - /** wait at least tMRD time */ - while (R_BUS->SDRAM.SDSR_b.MRSST) - { - /* Wait until Mode Register setting done. */ - } - - /** Set timing parameters for SDRAM */ - R_BUS->SDRAM.SDTR_b.RAS = BSP_PRV_SDRAM_TRAS - 1U; /* set ACTIVE-to-PRECHARGE command cycles*/ - R_BUS->SDRAM.SDTR_b.RCD = BSP_PRV_SDRAM_TRCD - 1U; /* set ACTIVE to READ/WRITE delay cycles */ - R_BUS->SDRAM.SDTR_b.RP = BSP_PRV_SDRAM_TRP - 1U; /* set PRECHARGE command period cycles */ - R_BUS->SDRAM.SDTR_b.WR = BSP_PRV_SDRAM_TWR - 1U; /* set write recovery cycles */ - R_BUS->SDRAM.SDTR_b.CL = BSP_PRV_SDRAM_CL; /* set SDRAM column latency cycles */ - - /** Set row address offset for target SDRAM */ - R_BUS->SDRAM.SDADR_b.MXC = BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET - 8U; - - R_BUS->SDRAM.SDRFCR_b.REFW = (uint16_t) (BSP_PRV_SDRAM_TRFC - 1U); /* set Auto-Refresh issuing cycle */ - R_BUS->SDRAM.SDRFCR_b.RFC = BSP_PRV_SDRAM_REF_CMD_INTERVAL - 1U; /* set Auto-Refresh period */ - - /** Start Auto-refresh */ - R_BUS->SDRAM.SDRFEN_b.RFEN = 1U; - - /** Enable SDRAM access */ - R_BUS->SDRAM.SDCCR_b.EXENB = 1U; -} diff --git a/ra/fsp/inc/api/bsp_api.h b/ra/fsp/inc/api/bsp_api.h index 66f32bf7a..55f1f12c6 100644 --- a/ra/fsp/inc/api/bsp_api.h +++ b/ra/fsp/inc/api/bsp_api.h @@ -65,6 +65,10 @@ #include "../../src/bsp/mcu/all/bsp_delay.h" #include "../../src/bsp/mcu/all/bsp_mcu_api.h" + #if __has_include("../../src/bsp/mcu/all/internal/bsp_internal.h") + #include "../../src/bsp/mcu/all/internal/bsp_internal.h" + #endif + #endif /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ diff --git a/ra/fsp/inc/api/r_cgc_api.h b/ra/fsp/inc/api/r_cgc_api.h index c6a8b1eda..3f6891b3b 100644 --- a/ra/fsp/inc/api/r_cgc_api.h +++ b/ra/fsp/inc/api/r_cgc_api.h @@ -88,14 +88,15 @@ typedef enum e_cgc_pll_div /** PLL clock output divisor. */ typedef enum e_cgc_pll_out_div { - CGC_PLL_OUT_DIV_2 = 2, ///< PLL output clock divided by 2 - CGC_PLL_OUT_DIV_3 = 3, ///< PLL output clock divided by 3 - CGC_PLL_OUT_DIV_4 = 4, ///< PLL output clock divided by 4 - CGC_PLL_OUT_DIV_5 = 5, ///< PLL output clock divided by 5 - CGC_PLL_OUT_DIV_6 = 6, ///< PLL output clock divided by 6 - CGC_PLL_OUT_DIV_8 = 8, ///< PLL output clock divided by 8 - CGC_PLL_OUT_DIV_9 = 9, ///< PLL output clock divided by 9 - CGC_PLL_OUT_DIV_16 = 16, ///< PLL output clock divided by 16 + CGC_PLL_OUT_DIV_2 = 2, ///< PLL output clock divided by 2 + CGC_PLL_OUT_DIV_3 = 3, ///< PLL output clock divided by 3 + CGC_PLL_OUT_DIV_4 = 4, ///< PLL output clock divided by 4 + CGC_PLL_OUT_DIV_5 = 5, ///< PLL output clock divided by 5 + CGC_PLL_OUT_DIV_6 = 6, ///< PLL output clock divided by 6 + CGC_PLL_OUT_DIV_8 = 8, ///< PLL output clock divided by 8 + CGC_PLL_OUT_DIV_9 = 9, ///< PLL output clock divided by 9 + CGC_PLL_OUT_DIV_1_5 = 10, ///< PLL output clock divided by 1.5 + CGC_PLL_OUT_DIV_16 = 16, ///< PLL output clock divided by 16 } cgc_pll_out_div_t; #ifndef BSP_OVERRIDE_CGC_SYS_CLOCK_DIV_T diff --git a/ra/fsp/inc/api/r_crc_api.h b/ra/fsp/inc/api/r_crc_api.h index 81130c0c8..abebea2f5 100644 --- a/ra/fsp/inc/api/r_crc_api.h +++ b/ra/fsp/inc/api/r_crc_api.h @@ -72,9 +72,9 @@ typedef enum e_crc_snoop_direction /** Structure for CRC inputs */ typedef struct st_crc_input_t { - uint32_t num_bytes; // Length of input buffer - uint32_t crc_seed; // CRC seed value - void * p_input_buffer; // Pointer to input buffer + uint32_t num_bytes; ///< Length of input buffer. It must be 4-byte aligned when a 32-bit CRC polynomial function is used. + uint32_t crc_seed; ///< CRC seed value + const void * p_input_buffer; ///< Pointer to input buffer } crc_input_t; /** CRC control block. Allocate an instance specific control block to pass into the CRC API calls. diff --git a/ra/fsp/inc/api/r_ether_api.h b/ra/fsp/inc/api/r_ether_api.h index cb0231756..7b3907513 100644 --- a/ra/fsp/inc/api/r_ether_api.h +++ b/ra/fsp/inc/api/r_ether_api.h @@ -96,7 +96,13 @@ typedef enum e_ether_event ETHER_EVENT_WAKEON_LAN, ///< Magic packet detection event ETHER_EVENT_LINK_ON, ///< Link up detection event ETHER_EVENT_LINK_OFF, ///< Link down detection event - ETHER_EVENT_INTERRUPT, ///< Interrupt event + ETHER_EVENT_INTERRUPT, ///< DEPRECATED Interrupt event + ETHER_EVENT_RX_COMPLETE, ///< Receive complete event. + ETHER_EVENT_RX_MESSAGE_LOST, ///< Receive FIFO overflow or Receive descriptor is full. + ETHER_EVENT_TX_COMPLETE, ///< Transmit complete event. + ETHER_EVENT_TX_BUFFER_EMPTY, ///< Transmit descriptor or FIFO is empty. + ETHER_EVENT_TX_ABORTED, ///< Transmit abort event. + ETHER_EVENT_ERR_GLOBAL, ///< Global error has occurred. } ether_event_t; #endif diff --git a/ra/fsp/inc/api/r_i2c_master_api.h b/ra/fsp/inc/api/r_i2c_master_api.h index 0b8456281..04abee079 100644 --- a/ra/fsp/inc/api/r_i2c_master_api.h +++ b/ra/fsp/inc/api/r_i2c_master_api.h @@ -60,7 +60,9 @@ typedef enum e_i2c_master_event { I2C_MASTER_EVENT_ABORTED = 1, ///< A transfer was aborted I2C_MASTER_EVENT_RX_COMPLETE = 2, ///< A receive operation was completed successfully - I2C_MASTER_EVENT_TX_COMPLETE = 3 ///< A transmit operation was completed successfully + I2C_MASTER_EVENT_TX_COMPLETE = 3, ///< A transmit operation was completed successfully + I2C_MASTER_EVENT_START = 4, ///< I2C sent a start condition + I2C_MASTER_EVENT_BYTE_ACK = 5, ///< I2C finished sending/receiving 1 data byte } i2c_master_event_t; /** I2C callback parameter definition */ diff --git a/ra/fsp/inc/api/r_i3c_api.h b/ra/fsp/inc/api/r_i3c_api.h index 6f65a1f0c..5e24b0c26 100644 --- a/ra/fsp/inc/api/r_i3c_api.h +++ b/ra/fsp/inc/api/r_i3c_api.h @@ -40,28 +40,34 @@ FSP_HEADER typedef enum e_i3c_common_command_code { /* Broadcast Common Command Codes */ - I3C_CCC_BROADCAST_ENEC = (0x00), ///< Enable Slave initiated events. - I3C_CCC_BROADCAST_DISEC = (0x01), ///< Disable Slave initiated events. - I3C_CCC_BROADCAST_ENTAS0 = (0x02), ///< Enter Activity State 0. - I3C_CCC_BROADCAST_ENTAS1 = (0x03), ///< Enter Activity State 1. - I3C_CCC_BROADCAST_ENTAS2 = (0x04), ///< Enter Activity State 2. - I3C_CCC_BROADCAST_ENTAS3 = (0x05), ///< Enter Activity State 3. - I3C_CCC_BROADCAST_RSTDAA = (0x06), ///< Reset Dynamic Address Assignment. - I3C_CCC_BROADCAST_ENTDAA = (0x07), ///< Enter Dynamic Address Assignment. - I3C_CCC_BROADCAST_DEFSVLS = (0x08), ///< Define List of Slaves. - I3C_CCC_BROADCAST_SETMWL = (0x09), ///< Set Max Write Length. - I3C_CCC_BROADCAST_SETMRL = (0x0A), ///< Set Max Read Length. - I3C_CCC_BROADCAST_ENTTM = (0x0B), ///< Enter Test Mode. - I3C_CCC_BROADCAST_ENTHDR0 = (0x20), ///< Enter HDR Mode 0. - I3C_CCC_BROADCAST_ENTHDR1 = (0x21), ///< Enter HDR Mode 1. - I3C_CCC_BROADCAST_ENTHDR2 = (0x22), ///< Enter HDR Mode 2. - I3C_CCC_BROADCAST_ENTHDR3 = (0x23), ///< Enter HDR Mode 3. - I3C_CCC_BROADCAST_ENTHDR4 = (0x24), ///< Enter HDR Mode 4 (Reserved for future definition). - I3C_CCC_BROADCAST_ENTHDR5 = (0x25), ///< Enter HDR Mode 5 (Reserved for future definition). - I3C_CCC_BROADCAST_ENTHDR6 = (0x26), ///< Enter HDR Mode 6 (Reserved for future definition). - I3C_CCC_BROADCAST_ENTHDR7 = (0x27), ///< Enter HDR Mode 7 (Reserved for future definition). - I3C_CCC_BROADCAST_SETXTIME = (0x28), ///< Set Exchange Timing Info. - I3C_CCC_BROADCAST_SETAASA = (0x29), ///< Set All Addresses to Static Address. + I3C_CCC_BROADCAST_ENEC = (0x00), ///< Enable Slave initiated events. + I3C_CCC_BROADCAST_DISEC = (0x01), ///< Disable Slave initiated events. + I3C_CCC_BROADCAST_ENTAS0 = (0x02), ///< Enter Activity State 0. + I3C_CCC_BROADCAST_ENTAS1 = (0x03), ///< Enter Activity State 1. + I3C_CCC_BROADCAST_ENTAS2 = (0x04), ///< Enter Activity State 2. + I3C_CCC_BROADCAST_ENTAS3 = (0x05), ///< Enter Activity State 3. + I3C_CCC_BROADCAST_RSTDAA = (0x06), ///< Reset Dynamic Address Assignment. + I3C_CCC_BROADCAST_ENTDAA = (0x07), ///< Enter Dynamic Address Assignment. + I3C_CCC_BROADCAST_DEFSVLS = (0x08), ///< Define List of Slaves. + I3C_CCC_BROADCAST_SETMWL = (0x09), ///< Set Max Write Length. + I3C_CCC_BROADCAST_SETMRL = (0x0A), ///< Set Max Read Length. + I3C_CCC_BROADCAST_ENTTM = (0x0B), ///< Enter Test Mode. + I3C_CCC_BROADCAST_SETBUSCON = (0x0C), ///< Set BUS Context. + I3C_CCC_BROADCAST_ENDXFER = (0x12), ///< Data Transfer Ending Procedure Control. + I3C_CCC_BROADCAST_ENTHDR0 = (0x20), ///< Enter HDR Mode 0. + I3C_CCC_BROADCAST_ENTHDR1 = (0x21), ///< Enter HDR Mode 1. + I3C_CCC_BROADCAST_ENTHDR2 = (0x22), ///< Enter HDR Mode 2. + I3C_CCC_BROADCAST_ENTHDR3 = (0x23), ///< Enter HDR Mode 3. + I3C_CCC_BROADCAST_ENTHDR4 = (0x24), ///< Enter HDR Mode 4 (Reserved for future definition). + I3C_CCC_BROADCAST_ENTHDR5 = (0x25), ///< Enter HDR Mode 5 (Reserved for future definition). + I3C_CCC_BROADCAST_ENTHDR6 = (0x26), ///< Enter HDR Mode 6 (Reserved for future definition). + I3C_CCC_BROADCAST_ENTHDR7 = (0x27), ///< Enter HDR Mode 7 (Reserved for future definition). + I3C_CCC_BROADCAST_SETXTIME = (0x28), ///< Set Exchange Timing Info. + I3C_CCC_BROADCAST_SETAASA = (0x29), ///< Set All Addresses to Static Address. + I3C_CCC_BROADCAST_RSTACT = (0x2A), ///< Slave Reset Action. + I3C_CCC_BROADCAST_DEFGRPA = (0x2B), ///< Define List of Group Address. + I3C_CCC_BROADCAST_RSTGRPA = (0x2C), ///< Reset Group Address. + I3C_CCC_BROADCAST_MLANE = (0x2D), ///< Multi-Lane Data Transfer Control. /* Direct Common Command Codes */ I3C_CCC_DIRECT_ENEC = (0x80), ///< Enable Slave initiated events. @@ -70,7 +76,7 @@ typedef enum e_i3c_common_command_code I3C_CCC_DIRECT_ENTAS1 = (0x83), ///< Enter Activity State 1. I3C_CCC_DIRECT_ENTAS2 = (0x84), ///< Enter Activity State 2. I3C_CCC_DIRECT_ENTAS3 = (0x85), ///< Enter Activity State 3. - I3C_CCC_DIRECT_RSTDAA = (0x86), ///< Reset Dynamic Address Assignment. + I3C_CCC_DIRECT_RSTDAA = (0x86), ///< Reset Dynamic Address Assignment (DEPRECATED v1.0). I3C_CCC_DIRECT_SETDASA = (0x87), ///< Set Dynamic Address from Static Address. I3C_CCC_DIRECT_SETNEWDA = (0x88), ///< Set New Dynamic Address. I3C_CCC_DIRECT_SETMWL = (0x89), ///< Set Max Write Length. @@ -82,9 +88,18 @@ typedef enum e_i3c_common_command_code I3C_CCC_DIRECT_GETDCR = (0x8F), ///< Get Device Characteristic Register. I3C_CCC_DIRECT_GETSTATUS = (0x90), ///< Get Device Status. I3C_CCC_DIRECT_GETACCMST = (0x91), ///< Get Accept Mastership. + I3C_CCC_DIRECT_ENDXFER = (0x92), ///< Data Transfer Ending Procedure Control. + I3C_CCC_DIRECT_SETBRGTGT = (0x93), ///< Set Bridge Targets. I3C_CCC_DIRECT_GETMXDS = (0x94), ///< Get Max Data Speed. + I3C_CCC_DIRECT_GETHDRCAP = (0x95), ///< Get HDR Capability. + I3C_CCC_DIRECT_SETROUTE = (0x96), ///< Set Route. + I3C_CCC_DIRECT_D2DXFER = (0x97), ///< Device to Device(s) Tunneling Control. I3C_CCC_DIRECT_SETXTIME = (0x98), ///< Set Exchange Timing Information. I3C_CCC_DIRECT_GETXTIME = (0x99), ///< Get Exchange Timing Information. + I3C_CCC_DIRECT_RSTACT = (0x9A), ///< Reset Slave Action. + I3C_CCC_DIRECT_SETGRPA = (0x9B), ///< Set Group Address. + I3C_CCC_DIRECT_RSTGRPA = (0x9C), ///< Reset Group Address. + I3C_CCC_DIRECT_MLANE = (0x9D), ///< Multi-Lane Data Transfer Control. } i3c_common_command_code_t; /** I3C Events that result in a callback. */ @@ -218,7 +233,13 @@ typedef struct s_i3c_slave_info * - 1: Is a Bridge Device. */ uint8_t bridge_identifier : 1; - uint8_t : 1; /* Reserved */ + + /** + * HDR Capable: + * - 0: Not Capable. + * - 1: Capable. + */ + uint8_t hdr_capable : 1; /** * Device Role: @@ -270,10 +291,10 @@ typedef struct s_i3c_slave_device_cfg i3c_slave_info_t slave_info; ///< PID, BCR, and DCR registers for the device (Slave mode only). } i3c_device_cfg_t; -/** Descriptor for completing CCC transfers. */ +/** Descriptor for completing CCC/HDR transfers. */ typedef struct s_i3c_command_descriptor { - uint8_t command_code; ///< Common Command Code for the transfer. + uint8_t command_code; ///< Common Command Code / HDR Command Code for the transfer. uint8_t * p_buffer; ///< Buffer for reading or writing data. uint32_t length; ///< Length of the data portion of the command. bool restart; ///< If true, issue a repeated-start after the transfer is completed. @@ -396,7 +417,7 @@ typedef struct st_i3c_api fsp_err_t (* slaveStatusSet)(i3c_ctrl_t * const p_ctrl, i3c_device_status_t device_status); /** - * Send a broadcast or directed command to slave devices on the bus. + * Send a read/write/broadcast CCC or HDR command. * * Note: This function is not used in slave mode. * @@ -404,7 +425,7 @@ typedef struct st_i3c_api * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. * @param[in] p_command_descriptor A descriptor for executing the command. */ - fsp_err_t (* commandSend)(i3c_ctrl_t * const p_ctrl, i3c_command_descriptor_t * p_command_descriptor); + fsp_err_t (* commandSend)(i3c_ctrl_t * const p_ctrl, i3c_command_descriptor_t const * const p_command_descriptor); /** * In master mode: Start a write transfer. When the transfer is completed send a stop condition or a repeated-start. diff --git a/ra/fsp/inc/api/r_rtc_api.h b/ra/fsp/inc/api/r_rtc_api.h index 6376da19f..3857e0cf2 100644 --- a/ra/fsp/inc/api/r_rtc_api.h +++ b/ra/fsp/inc/api/r_rtc_api.h @@ -136,6 +136,8 @@ typedef enum e_rtc_periodic_irq_select } rtc_periodic_irq_select_t; #endif +#ifndef BSP_OVERRIDE_RTC_TIME_CAPTURE_SOURCE_T + /** Time capture trigger source */ typedef enum e_rtc_time_capture_source { @@ -146,6 +148,7 @@ typedef enum e_rtc_time_capture_source RTC_TIME_CAPTURE_SOURCE_SOFTWARE = 4, ///< Software trigger RTC_TIME_CAPTURE_SOURCE_ELC_EVENT = 5, ///< ELC event trigger } rtc_time_capture_source_t; +#endif /** Time capture trigger mode */ typedef enum e_rtc_time_capture_mode diff --git a/ra/fsp/inc/api/r_timer_api.h b/ra/fsp/inc/api/r_timer_api.h index fc0f43550..49410c9b0 100644 --- a/ra/fsp/inc/api/r_timer_api.h +++ b/ra/fsp/inc/api/r_timer_api.h @@ -73,6 +73,12 @@ typedef enum e_timer_compare_match { TIMER_COMPARE_MATCH_A = 0U, ///< Compare match A value TIMER_COMPARE_MATCH_B = 1U, ///< Compare match B value + TIMER_COMPARE_MATCH_C = 2U, ///< Compare match C value + TIMER_COMPARE_MATCH_D = 3U, ///< Compare match D value + TIMER_COMPARE_MATCH_E = 4U, ///< Compare match E value + TIMER_COMPARE_MATCH_F = 5U, ///< Compare match F value + TIMER_COMPARE_MATCH_G = 6U, ///< Compare match G value + TIMER_COMPARE_MATCH_H = 7U, ///< Compare match H value } timer_compare_match_t; /** Callback function parameter data */ diff --git a/ra/fsp/inc/api/r_usb_basic_api.h b/ra/fsp/inc/api/r_usb_basic_api.h index 575ff0036..38496ab7c 100644 --- a/ra/fsp/inc/api/r_usb_basic_api.h +++ b/ra/fsp/inc/api/r_usb_basic_api.h @@ -291,6 +291,40 @@ typedef enum e_usb_address USB_ADDRESS5, } usb_address_t; +/** USB TypeC operation_mode */ +typedef enum e_usb_typec_mode +{ + USB_TYPEC_MODE_SINK = 0, ///< Sink Only Mode + USB_TYPEC_MODE_USB20_ONLY_SINK, ///< USB 2.0 Only Sink Mode +} usb_typec_mode_t; + +/** USB TypeC Connection of Plug Orientation */ +typedef enum e_usb_typec_plug +{ + USB_TYPEC_PLUG_CC1_CONNECTED = 0, ///< CC1 connected + USB_TYPEC_PLUG_CC2_CONNECTED, ///< CC2 connected +} usb_typec_plug_t; + +/** USB TypeC Status of Connection State Machine */ +typedef enum e_usb_typec_connection_status +{ + USB_TYPEC_CONNECTION_STATUS_DISABLED = 0, ///< Disabled + USB_TYPEC_CONNECTION_STATUS_UNATTACHED, ///< Unattached.SNK + USB_TYPEC_CONNECTION_STATUS_ATTACHED_WAIT, ///< AttachedWait.SNK + USB_TYPEC_CONNECTION_STATUS_ATTACHED, ///< Attached.SNK + USB_TYPEC_CONNECTION_STATUS_ATTACHED_POWER_DEFAULT, ///< Attached.SNK (PowerDefault.SNK) + USB_TYPEC_CONNECTION_STATUS_ATTACHED_POWER_15, ///< Attached.SNK (Power1.5.SNK) + USB_TYPEC_CONNECTION_STATUS_ATTACHED_POWER_30, ///< Attached.SNK (Power3.0.SNK) +} usb_typec_connection_status_t; + +/** USB TypeC VBUS status */ +typedef enum e_usb_typec_vbus_status +{ + USB_TYPEC_VBUS_STATUS_OFF = 0, ///< VBUS Off State + USB_TYPEC_VBUS_STATUS_ON, ///< VBUS On State +} usb_typec_vbus_status_t; + + /** USB control block. Allocate an instance specific control block to pass into the USB API calls. */ typedef void usb_ctrl_t; @@ -352,6 +386,14 @@ typedef struct st_usb_event_info const transfer_instance_t * p_transfer_rx; ///< Receive context } usb_event_info_t; +typedef struct st_usb_typec_info +{ + usb_typec_mode_t operation_mode; ///< Connection State Mode + usb_typec_plug_t plug; ///< Connection of Plug Orientation + usb_typec_connection_status_t connection_status; ///< Status of Connection Statue Machine + usb_typec_vbus_status_t vbus_status; ///< Status of VBUS +} usb_typec_info_t; + typedef usb_event_info_t usb_callback_args_t; #if (BSP_CFG_RTOS == 0) @@ -386,6 +428,7 @@ typedef struct st_usb_cfg IRQn_Type irq_d0; ///< FS D0FIFO dedicated interrupt number storage variable. IRQn_Type irq_d1; ///< FS D1FIFO dedicated interrupt number storage variable. IRQn_Type hsirq; ///< USBIR dedicated interrupt number storage variable. + IRQn_Type irq_typec; ///< USB Type-C IR dedicated interrupt number storage variable. IRQn_Type hsirq_d0; ///< HS D0FIFO dedicated interrupt number storage variable. IRQn_Type hsirq_d1; ///< HS D1FIFO dedicated interrupt number storage variable. uint8_t ipl; ///< Variable to store the interrupt priority of USBI @@ -393,6 +436,7 @@ typedef struct st_usb_cfg uint8_t ipl_d0; ///< Variable to store the interrupt priority of FS D0FIFO. uint8_t ipl_d1; ///< Variable to store the interrupt priority of FS D1FIFO. uint8_t hsipl; ///< Variable to store the interrupt priority of USBIR. + uint8_t ipl_typec; ///< Variable to store the interrupt priority of USB Type-C IR. uint8_t hsipl_d0; ///< Variable to store the interrupt priority of HS D0FIFO. uint8_t hsipl_d1; ///< Variable to store the interrupt priority of HS D1FIFO. usb_callback_t * p_usb_apl_callback; ///< Application Callback @@ -645,6 +689,14 @@ typedef struct st_usb_api * @param[in] p_ctrl USB control structure. */ fsp_err_t (* otgSRP)(usb_ctrl_t * const p_ctrl); + + /** Get information on USB Type-C Connection. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_info Pointer to usb_typec_info_t structure area. + */ + fsp_err_t (* typecInfoGet)(usb_ctrl_t * const p_ctrl, usb_typec_info_t * p_info); + } usb_api_t; /** This structure encompasses everything that is needed to use an instance of this interface. */ diff --git a/ra/fsp/inc/fsp_features.h b/ra/fsp/inc/fsp_features.h index 9a8db8212..692175d08 100644 --- a/ra/fsp/inc/fsp_features.h +++ b/ra/fsp/inc/fsp_features.h @@ -114,6 +114,7 @@ typedef enum e_fsp_ip FSP_IP_TAU = 81, ///< Timer Array Unit FSP_IP_TML = 82, ///< 32-bit Interval Timer FSP_IP_MACL = 83, ///< 32-bit Multiply-Accumulator + FSP_IP_USBCC = 84, ///< USB Type-C Controller } fsp_ip_t; /** Signals that can be mapped to an interrupt. */ diff --git a/ra/fsp/inc/fsp_version.h b/ra/fsp/inc/fsp_version.h index 8053c475c..c9206d27b 100644 --- a/ra/fsp/inc/fsp_version.h +++ b/ra/fsp/inc/fsp_version.h @@ -31,7 +31,7 @@ extern "C" { #define FSP_VERSION_MAJOR (5U) /** FSP pack minor version. */ - #define FSP_VERSION_MINOR (3U) + #define FSP_VERSION_MINOR (4U) /** FSP pack patch version. */ #define FSP_VERSION_PATCH (0U) @@ -40,10 +40,10 @@ extern "C" { #define FSP_VERSION_BUILD (0U) /** Public FSP version name. */ - #define FSP_VERSION_STRING ("5.3.0") + #define FSP_VERSION_STRING ("5.4.0") /** Unique FSP version ID. */ - #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 5.3.0") + #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 5.4.0") /********************************************************************************************************************** * Typedef definitions diff --git a/ra/fsp/inc/instances/r_adc_d.h b/ra/fsp/inc/instances/r_adc_d.h index 7b9ae1771..c60286138 100644 --- a/ra/fsp/inc/instances/r_adc_d.h +++ b/ra/fsp/inc/instances/r_adc_d.h @@ -169,6 +169,9 @@ fsp_err_t R_ADC_D_CallbackSet(adc_ctrl_t * const p_api_ctrl, void const * const p_context, adc_callback_args_t * const p_callback_memory); +fsp_err_t R_ADC_D_SnoozeModePrepare(adc_ctrl_t * const p_ctrl); +fsp_err_t R_ADC_D_SnoozeModeExit(adc_ctrl_t * const p_ctrl); + /*******************************************************************************************************************//** * @} (end defgroup ADC_D) **********************************************************************************************************************/ diff --git a/ra/fsp/inc/instances/r_dtc.h b/ra/fsp/inc/instances/r_dtc.h index a454b9d25..d881cd84e 100644 --- a/ra/fsp/inc/instances/r_dtc.h +++ b/ra/fsp/inc/instances/r_dtc.h @@ -38,6 +38,9 @@ FSP_HEADER /** Max configurable number of blocks to transfer in BLOCK MODE */ #define DTC_MAX_BLOCK_COUNT (0x10000) +/** Alignment required for transfer_info_t structures. */ +#define DTC_TRANSFER_INFO_ALIGNMENT BSP_ALIGN_VARIABLE(BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT) + /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ diff --git a/ra/fsp/inc/instances/r_ether.h b/ra/fsp/inc/instances/r_ether.h index e934aec5d..d556a3f24 100644 --- a/ra/fsp/inc/instances/r_ether.h +++ b/ra/fsp/inc/instances/r_ether.h @@ -77,11 +77,50 @@ typedef struct st_ether_instance_descriptor struct st_ether_instance_descriptor * p_next; } ether_instance_descriptor_t; +/** Event mask for EESR register */ +typedef enum e_ether_eesr_event_mask +{ + ETHER_EESR_EVENT_MASK_CERF = (1U << 0U), ///< CERF event + ETHER_EESR_EVENT_MASK_PRE = (1U << 1U), ///< PRE event + ETHER_EESR_EVENT_MASK_RTSF = (1U << 2U), ///< RTSF event + ETHER_EESR_EVENT_MASK_RTLF = (1U << 3U), ///< RTLF event + ETHER_EESR_EVENT_MASK_RRF = (1U << 4U), ///< PRF event + ETHER_EESR_EVENT_MASK_RMAF = (1U << 7U), ///< RMAF event + ETHER_EESR_EVENT_MASK_TRO = (1U << 8U), ///< TRO event + ETHER_EESR_EVENT_MASK_CD = (1U << 9U), ///< CD event + ETHER_EESR_EVENT_MASK_DLC = (1U << 10U), ///< DLC event + ETHER_EESR_EVENT_MASK_CND = (1U << 11U), ///< CND event + ETHER_EESR_EVENT_MASK_RFOF = (1U << 16U), ///< RFOF event + ETHER_EESR_EVENT_MASK_RDE = (1U << 17U), ///< RDE event + ETHER_EESR_EVENT_MASK_FR = (1U << 18U), ///< FR event + ETHER_EESR_EVENT_MASK_TFUF = (1U << 19U), ///< TFUF event + ETHER_EESR_EVENT_MASK_TDE = (1U << 20U), ///< TDE event + ETHER_EESR_EVENT_MASK_TC = (1U << 21U), ///< TC event + ETHER_EESR_EVENT_MASK_ECI = (1U << 22U), ///< ECI event + ETHER_EESR_EVENT_MASK_ADE = (1U << 23U), ///< ADE event + ETHER_EESR_EVENT_MASK_RFCOF = (1U << 24U), ///< RFCOF event + ETHER_EESR_EVENT_MASK_RABT = (1U << 25U), ///< RABT event + ETHER_EESR_EVENT_MASK_TABT = (1U << 26U), ///< TABT event + ETHER_EESR_EVENT_MASK_TWB = (1U << 30U), ///< TWB event +} ether_eesr_event_mask_t; + +/** Event mask for ECSR register */ +typedef enum e_ether_ecsr_event_mask +{ + ETHER_ECSR_EVENT_MASK_ICD = (1U << 0U), ///< ICD event + ETHER_ECSR_EVENT_MASK_MPD = (1U << 1U), ///< MPD event + ETHER_ECSR_EVENT_MASK_LCHNG = (1U << 2U), ///< LCHNG event + ETHER_ECSR_EVENT_MASK_PSRTO = (1U << 4U), ///< PSRTO event + ETHER_ECSR_EVENT_MASK_BFR = (1U << 5U), ///< BFR event +} ether_ecsr_event_mask_t; + /** ETHER extension configures the buffer descriptor for ETHER. */ typedef struct st_ether_extended_cfg { ether_instance_descriptor_t * p_rx_descriptors; ///< Receive descriptor buffer pool ether_instance_descriptor_t * p_tx_descriptors; ///< Transmit descriptor buffer pool + uint32_t eesr_event_filter; ///< Filter for EESR related event + uint8_t ecsr_event_filter; ///< Filter for ECSR related event } ether_extended_cfg_t; /** ETHER control block. DO NOT INITIALIZE. Initialization occurs when @ref ether_api_t::open is called. */ diff --git a/ra/fsp/inc/instances/r_i3c.h b/ra/fsp/inc/instances/r_i3c.h index 96a6bc80f..ee7a9a7f0 100644 --- a/ra/fsp/inc/instances/r_i3c.h +++ b/ra/fsp/inc/instances/r_i3c.h @@ -41,6 +41,7 @@ FSP_HEADER #define I3C_EVENT_STATUS_OVERFLOW (0x6) ///< A Receive FIFO overflow or Transmit FIFO underflow occurred. #define I3C_EVENT_STATUS_ABORTED_TO_MASTER (0x7) ///< In slave mode, the write transfer was ended via the 'T' bit. #define I3C_EVENT_STATUS_ABORTED (0x8) ///< In master mode, the transfer was aborted. +#define I3C_EVENT_STATUS_NOT_SUPPORTED (0xA) ///< Operation is not supported. #define I3C_EVENT_STATUS_IBI_NACK_DISABLED (0x20) ///< An IBI was NACK'd and the a DISEC command was sent. /*********************************************************************************************************************** @@ -50,13 +51,14 @@ FSP_HEADER /** Bitrate settings that can be selected at run-time using @ref i3c_api_t::deviceSelect. */ typedef enum e_i3c_bitrate_setting { - I3C_BITRATE_MODE_I2C_STDBR = 0U, ///< Use the period settings defined in STDBRH/L. - I3C_BITRATE_MODE_I2C_EXTBR = 1U, ///< Use the period settings defined in EXTBRH/L. - I3C_BITRATE_MODE_I3C_SDR0_STDBR = 0U, ///< Use the period settings defined in STDBRH/L (I3C Devices only). - I3C_BITRATE_MODE_I3C_SDR1_EXTBR = 1U, ///< Use the period settings defined in EXTBRH/L (I3C Devices only). - I3C_BITRATE_MODE_I3C_SDR2_STDBR_X2 = 2U, ///< Use the period settings defined in STDBRH/L x 2 (I3C Devices only). - I3C_BITRATE_MODE_I3C_SDR3_EXTBR_X2 = 3U, ///< Use the period settings defined in EXTBRH/L x 2 (I3C Devices only). - I3C_BITRATE_MODE_I3C_SDR4_EXTBR_X4 = 4U, ///< Use the period settings defined in EXTBRH/L x 4 (I3C Devices only). + I3C_BITRATE_MODE_I2C_STDBR = 0U, ///< Use standard period setting for subsequent I2C transfers. + I3C_BITRATE_MODE_I2C_EXTBR = 1U, ///< Use extended period setting for subsequent I2C transfers. + I3C_BITRATE_MODE_I3C_SDR0_STDBR = 0U, ///< Use standard period setting for subsequent I3C SDR transfers. + I3C_BITRATE_MODE_I3C_SDR1_EXTBR = 1U, ///< Use extended period setting for subsequent I3C SDR transfers. + I3C_BITRATE_MODE_I3C_SDR2_STDBR_X2 = 2U, ///< Use standard period setting x 2 for subsequent I3C SDR transfers. + I3C_BITRATE_MODE_I3C_SDR3_EXTBR_X2 = 3U, ///< Use extended period setting x 2 for subsequent I3C SDR transfers. + I3C_BITRATE_MODE_I3C_SDR4_EXTBR_X4 = 4U, ///< Use extended period setting x 4 for subsequent I3C SDR transfers. + I3C_BITRATE_MODE_I3C_HDR_DDR_STDBR = 6U, ///< Use standard period setting for subsequent I3C HDR-DDR transfers. } i3c_bitrate_mode_t; /** Supported activity states for ENTASn Command (See ENTASn in the MIPI I3C Specification v1.0). */ @@ -151,6 +153,10 @@ typedef struct s_slave_command_response_info /** Oscillator inaccuracy in 0.5% increments of 0% up to 25.5% (See GETXTIME in the MIPI I3C Specification v1.1). */ uint8_t oscillator_inaccuracy; + + bool hdr_ddr_support; ///< HDR-DDR mode is supported. + bool hdr_tsp_support; ///< HDR-TSP mode is supported. + bool hdr_tsl_support; ///< HDR-TSL mode is supported. } i3c_slave_command_response_info_t; /* Buffer descriptor for keeping track of a read transfer. */ @@ -257,7 +263,7 @@ fsp_err_t R_I3C_DynamicAddressAssignmentStart(i3c_ctrl_t * const p_ap i3c_address_assignment_mode_t address_assignment_mode, uint32_t starting_device_index, uint32_t device_count); -fsp_err_t R_I3C_CommandSend(i3c_ctrl_t * const p_api_ctrl, i3c_command_descriptor_t * p_command_descriptor); +fsp_err_t R_I3C_CommandSend(i3c_ctrl_t * const p_api_ctrl, i3c_command_descriptor_t const * const p_command_descriptor); fsp_err_t R_I3C_Write(i3c_ctrl_t * const p_api_ctrl, uint8_t const * const p_data, uint32_t length, bool restart); fsp_err_t R_I3C_Read(i3c_ctrl_t * const p_api_ctrl, uint8_t * const p_data, uint32_t length, bool restart); fsp_err_t R_I3C_IbiWrite(i3c_ctrl_t * const p_api_ctrl, diff --git a/ra/fsp/inc/instances/r_iic_b_master.h b/ra/fsp/inc/instances/r_iic_b_master.h index 4cd8ca111..4d78923c0 100644 --- a/ra/fsp/inc/instances/r_iic_b_master.h +++ b/ra/fsp/inc/instances/r_iic_b_master.h @@ -46,6 +46,8 @@ typedef struct iic_b_master_clock_settings uint8_t cks_value; ///< Internal Reference Clock Select uint8_t brh_value; ///< High-level period of SCL clock uint8_t brl_value; ///< Low-level period of SCL clock + uint8_t sdod_value; // < SDA Output Delay Counter + bool sdodcs_value; // < SDA Output Delay Clock Source } iic_b_master_clock_settings_t; /** I2C control structure. DO NOT INITIALIZE. */ @@ -79,6 +81,9 @@ typedef struct st_iic_b_master_instance_ctrl volatile bool activation_on_txi; // Tracks whether the transfer is activated on TXI interrupt volatile bool address_restarted; // Tracks whether the restart condition is send on 10 bit read + uint8_t sdod_value; // SDOD value when using SMBus + bool sdodcs_value; // SDODCS value when using SMBus + /* Pointer to callback and optional working memory */ void (* p_callback)(i2c_master_callback_args_t *); i2c_master_callback_args_t * p_callback_memory; @@ -94,6 +99,7 @@ typedef struct st_iic_b_master_extended_cfg iic_b_master_timeout_scl_low_t timeout_scl_low; ///< Allows timeouts to occur when SCL is held low. iic_b_master_clock_settings_t clock_settings; ///< I2C Clock settings uint32_t iic_clock_freq; ///< I2C Clock frequency in Hz + bool smbus_operation; ///< SMBus operation on I2C bus } iic_b_master_extended_cfg_t; /********************************************************************************************************************** diff --git a/ra/fsp/inc/instances/r_iic_master.h b/ra/fsp/inc/instances/r_iic_master.h index 990da24a5..3440f4534 100644 --- a/ra/fsp/inc/instances/r_iic_master.h +++ b/ra/fsp/inc/instances/r_iic_master.h @@ -46,6 +46,8 @@ typedef struct iic_master_clock_settings uint8_t cks_value; ///< Internal Reference Clock Select uint8_t brh_value; ///< High-level period of SCL clock uint8_t brl_value; ///< Low-level period of SCL clock + uint8_t sddl_value; // < SDA Output Delay Counter + bool dlcs_value; // < SDA Output Delay Clock Source } iic_master_clock_settings_t; /** I2C control structure. DO NOT INITIALIZE. */ @@ -93,6 +95,7 @@ typedef struct st_iic_master_extended_cfg iic_master_timeout_mode_t timeout_mode; ///< Timeout Detection Time Select: Long Mode = 0 and Short Mode = 1. iic_master_timeout_scl_low_t timeout_scl_low; ///< Allows timeouts to occur when SCL is held low. iic_master_clock_settings_t clock_settings; ///< I2C Clock settings + bool smbus_operation; ///< SMBus operation on I2C bus } iic_master_extended_cfg_t; /********************************************************************************************************************** diff --git a/ra/fsp/inc/instances/r_ioport.h b/ra/fsp/inc/instances/r_ioport.h index 4410dc0e5..b410276f6 100644 --- a/ra/fsp/inc/instances/r_ioport.h +++ b/ra/fsp/inc/instances/r_ioport.h @@ -446,6 +446,9 @@ typedef enum e_ioport_peripheral /** Pin will function as a MIPI DSI peripheral pin */ IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an UARTA peripheral pin */ + IOPORT_PERIPHERAL_UARTA = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), } ioport_peripheral_t; #endif diff --git a/ra/fsp/inc/instances/r_lvd.h b/ra/fsp/inc/instances/r_lvd.h index 01243a84b..cb75ccb5b 100644 --- a/ra/fsp/inc/instances/r_lvd.h +++ b/ra/fsp/inc/instances/r_lvd.h @@ -71,5 +71,5 @@ FSP_FOOTER #endif /*******************************************************************************************************************//** - * @} (end defgroup LVD) + * @} (end defgroup LVD-PVD) **********************************************************************************************************************/ diff --git a/ra/fsp/inc/instances/r_sau_spi.h b/ra/fsp/inc/instances/r_sau_spi.h index 52291e2a8..2424664ad 100644 --- a/ra/fsp/inc/instances/r_sau_spi.h +++ b/ra/fsp/inc/instances/r_sau_spi.h @@ -44,7 +44,7 @@ typedef enum e_sau_spi_operation_clock typedef enum e_sau_spi_transfer_mode { SAU_SPI_TRANSFER_MODE_SINGLE = 0, ///< Single transfer mode - SAU_SPI_TRANSFER_MODE_CONTINUOUS = 1, ///< Continuous transfer mode + SAU_SPI_TRANSFER_MODE_CONTINUOUS = 1, ///< Continuous transfer mode will be deprecated. } sau_spi_transfer_mode_t; /** Data phase */ @@ -90,6 +90,7 @@ typedef struct st_sau_spi_instance_ctrl uint32_t rx_count; uint32_t count; bool transfer_in_progress; + bool activation_on_tei; /* Pointer to callback and optional working memory. */ void (* p_callback)(spi_callback_args_t *); diff --git a/ra/fsp/inc/instances/r_sau_uart.h b/ra/fsp/inc/instances/r_sau_uart.h index 9502ef6e5..536ff2fcf 100644 --- a/ra/fsp/inc/instances/r_sau_uart.h +++ b/ra/fsp/inc/instances/r_sau_uart.h @@ -61,6 +61,7 @@ typedef struct { sau_operation_clock_t operation_clock; ///< Select operation clock uint8_t stclk; ///< Transfer clock setting by dividing the operation clock + uint8_t prs; ///< Operation clock divider register setting } sau_uart_baudrate_setting_t; /** UART Configuration */ diff --git a/ra/fsp/inc/instances/r_tau_pwm.h b/ra/fsp/inc/instances/r_tau_pwm.h index 9df318028..2567d7a99 100644 --- a/ra/fsp/inc/instances/r_tau_pwm.h +++ b/ra/fsp/inc/instances/r_tau_pwm.h @@ -26,7 +26,16 @@ FSP_HEADER * Macro definitions **********************************************************************************************************************/ -#define TAU_PWM_PRV_MAX_NUM_CHANNELS (7U) +/* Even though there are 8 channels, there always has to be one slave.. (slave > master) + * so valid master channels numbers are 0-6, and valid slave numbers are 1-7 */ +#define TAU_PWM_MAX_CHANNEL_NUM (7U) + +#if TAU_PWM_CFG_MULTI_SLAVE_ENABLE + #define TAU_PWM_MAX_NUM_SLAVE_CHANNELS (TAU_PWM_MAX_CHANNEL_NUM) +#else + #define TAU_PWM_MAX_NUM_SLAVE_CHANNELS (1) +#endif +#define TAU_PWM_SLAVE_CHANNEL_UNUSED (0) /* 0 is an invalid slave channel since master channel < slave channel*/ /*********************************************************************************************************************** * Typedef definitions @@ -98,13 +107,13 @@ typedef struct st_tau_pwm_channel_cfg /** Extended configuration structure for TAU_PWM */ typedef struct st_tau_pwm_extended_cfg { - tau_pwm_operation_clock_t operation_clock; ///< Setting of operation clock for master and slave channels + tau_pwm_operation_clock_t operation_clock; ///< Setting of operation clock for master and slave channels /* Input settings. */ - tau_pwm_source_t trigger_source; ///< Trigger source for master channel - tau_pwm_detect_edge_t detect_edge; ///< Trigger edge to start pulse period measurement + tau_pwm_source_t trigger_source; ///< Trigger source for master channel + tau_pwm_detect_edge_t detect_edge; ///< Trigger edge to start pulse period measurement - tau_pwm_channel_cfg_t const * p_slave_channel_cfgs[TAU_PWM_PRV_MAX_NUM_CHANNELS]; ///< Configuration for each slave channel, at least 1 slave channel is required + tau_pwm_channel_cfg_t const * p_slave_channel_cfgs[TAU_PWM_MAX_NUM_SLAVE_CHANNELS]; ///< Configuration for each slave channel, at least 1 slave channel is required } tau_pwm_extended_cfg_t; /** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ @@ -137,8 +146,9 @@ fsp_err_t R_TAU_PWM_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const fsp_err_t R_TAU_PWM_Stop(timer_ctrl_t * const p_ctrl); fsp_err_t R_TAU_PWM_Start(timer_ctrl_t * const p_ctrl); fsp_err_t R_TAU_PWM_Reset(timer_ctrl_t * const p_ctrl); + fsp_err_t R_TAU_PWM_Enable(timer_ctrl_t * const p_ctrl); -fsp_err_t R_TAU_PWM_Disable(timer_ctrl_t * const p_ctrl); + fsp_err_t R_TAU_PWM_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); fsp_err_t R_TAU_PWM_CompareMatchSet(timer_ctrl_t * const p_ctrl, uint32_t const compare_match_value, diff --git a/ra/fsp/inc/instances/r_uarta.h b/ra/fsp/inc/instances/r_uarta.h index f943fd473..93222488b 100644 --- a/ra/fsp/inc/instances/r_uarta.h +++ b/ra/fsp/inc/instances/r_uarta.h @@ -54,13 +54,6 @@ typedef enum e_uarta_clock_div UARTA_CLOCK_DIV_COUNT, ///< Total number of clock divider options. } uarta_clock_div_t; -/** Receive interrupt mode select */ -typedef enum e_uarta_rxi_mode -{ - UARTA_RXI_MODE_ERROR_TRIGGER_ERI = 0U, ///< The receive error interrupt is generated when a reception error occurs. - UARTA_RXI_MODE_ERROR_TRIGGER_RXI = 1U, ///< The receive interrupt is generated when a reception error occurs. -} uarta_rxi_mode_t; - /** Transmission/reception order configuration. */ typedef enum e_uarta_dir_bit { @@ -89,13 +82,13 @@ typedef struct st_uarta_baud_setting uint8_t : 2; } uta0ck_clock_b; }; - uint8_t brgca; ///< Baud rate generator control setting + uint8_t brgca; ///< Baud rate generator control setting + uint16_t delay_time; ///< Delay time (us) required to enable TX at open } uarta_baud_setting_t; /** UART on UARTA device Configuration */ typedef struct st_uarta_extended_cfg { - uarta_rxi_mode_t rxi_mode; ///< Receive interrupt mode select uarta_dir_bit_t transfer_dir; ///< Transmission/reception order configuration uarta_alv_bit_t transfer_level; ///< Transmission/reception level configuration uarta_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. diff --git a/ra/fsp/inc/instances/r_usb_basic.h b/ra/fsp/inc/instances/r_usb_basic.h index a56133211..44c655554 100644 --- a/ra/fsp/inc/instances/r_usb_basic.h +++ b/ra/fsp/inc/instances/r_usb_basic.h @@ -113,6 +113,8 @@ fsp_err_t R_USB_DriverActivate(usb_ctrl_t * const p_api_ctrl); fsp_err_t R_USB_CallbackMemorySet(usb_ctrl_t * const p_api_ctrl, usb_callback_args_t * p_callback_memory); +fsp_err_t R_USB_TypeCInfoGet(usb_ctrl_t * const p_api_ctrl, usb_typec_info_t * p_info); + /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ FSP_FOOTER diff --git a/ra/fsp/inc/instances/rm_comms_i2c.h b/ra/fsp/inc/instances/rm_comms_i2c.h index ff7568fc9..b48f0c323 100644 --- a/ra/fsp/inc/instances/rm_comms_i2c.h +++ b/ra/fsp/inc/instances/rm_comms_i2c.h @@ -94,6 +94,9 @@ typedef struct st_rm_comms_i2c_bus_extended_cfg uint32_t bus_timeout; ///< Possible in ticks. rm_comms_ctrl_t * p_current_ctrl; ///< Current device using the bus (by switching the address) void const * p_driver_instance; ///< Pointer to I2C HAL interface to be used in the framework + + void const * p_elc; ///< Pointer to ELC instance. + void const * p_timer; ///< Pointer to GPT instance. } rm_comms_i2c_bus_extended_cfg_t; /** Communications middleware control structure. */ @@ -106,6 +109,9 @@ typedef struct st_rm_comms_i2c_instance_ctrl uint32_t transfer_data_bytes; ///< Size of transfer data. uint8_t * p_transfer_data; ///< Pointer to transfer data buffer. + /* Specific control variable for SMBus */ + bool smbus_operation; ///< SMBus operation on I2C bus + /* Pointer to callback and optional working memory */ void (* p_callback)(rm_comms_callback_args_t * p_args); diff --git a/ra/fsp/inc/instances/rm_comms_smbus.h b/ra/fsp/inc/instances/rm_comms_smbus.h new file mode 100644 index 000000000..6f79095cb --- /dev/null +++ b/ra/fsp/inc/instances/rm_comms_smbus.h @@ -0,0 +1,104 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup RM_COMMS_SMBUS + * @{ + **********************************************************************************************************************/ + +#ifndef RM_COMMS_SMBUS_H +#define RM_COMMS_SMBUS_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "rm_comms_api.h" +#include "r_i2c_master_api.h" +#include "r_elc_api.h" +#include "r_elc.h" +#include "r_timer_api.h" +#include "r_gpt.h" +#include "rm_comms_smbus_cfg.h" +#include "rm_comms_i2c.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* This macro contains 32 data bytes + 1 command code byte + 2 count bytes + 1 PEC byte + 1 address byte */ +#define RM_COMMS_SMBUS_TRANSMISSION_MAX_BYTES (37U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern rm_comms_api_t const g_comms_on_comms_smbus; + +/** @endcond */ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Extend configuration of SMBus **/ +typedef struct st_rm_comms_smbus_extended_cfg +{ + bool pec_enable; ///< Calculate PEC byte for SMBus transmission. + rm_comms_i2c_bus_extended_cfg_t * p_comms_i2c_extend_cfg; ///< Pointer to extend configuration block of rm_comms_i2c + rm_comms_i2c_instance_ctrl_t * p_comms_i2c_ctrl; ///< Control block of rm_comms_i2c +} rm_comms_smbus_extended_cfg_t; + +/** SMBus middleware control block **/ +typedef struct st_rm_comms_smbus_instance_ctrl +{ + bool timer_is_enabled; ///< Validate that external event triggers stop the timer is enabled + uint8_t write_buff[RM_COMMS_SMBUS_TRANSMISSION_MAX_BYTES]; ///< Intermediate buffer + uint8_t receive_crc_seed; ///< CRC seed value + uint32_t open; ///< Open flag. + + rm_comms_i2c_instance_ctrl_t * p_comms_i2c_ctrl; ///< Control block of rm_comms_i2c + + const void * p_context; +} rm_comms_smbus_instance_ctrl_t; + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t RM_COMMS_SMBUS_Open(rm_comms_ctrl_t * const p_api_ctrl, rm_comms_cfg_t const * const p_cfg); + +fsp_err_t RM_COMMS_SMBUS_Close(rm_comms_ctrl_t * const p_api_ctrl); + +fsp_err_t RM_COMMS_SMBUS_Read(rm_comms_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes); + +fsp_err_t RM_COMMS_SMBUS_Write(rm_comms_ctrl_t * const p_api_ctrl, uint8_t * const p_src, uint32_t const bytes); + +fsp_err_t RM_COMMS_SMBUS_WriteRead(rm_comms_ctrl_t * const p_api_ctrl, + rm_comms_write_read_params_t const write_read_params); + +fsp_err_t RM_COMMS_SMBUS_CallbackSet(rm_comms_ctrl_t * const p_api_ctrl, + void ( * p_callback)(rm_comms_callback_args_t *), + void const * const p_context); + +void rm_comms_smbus_transmission_callback(i2c_master_callback_args_t * p_args); + +void rm_comms_smbus_timeout_callback(timer_callback_args_t * p_args); + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_FOOTER +#endif /* RM_COMMS_SMBUS_H */ + +/*******************************************************************************************************************//** + * @} (end addtogroup RM_COMM_SMBUS) + **********************************************************************************************************************/ diff --git a/ra/fsp/inc/instances/rm_wifi_da16xxx.h b/ra/fsp/inc/instances/rm_wifi_da16xxx.h index 18eab41ba..a080f6ae3 100644 --- a/ra/fsp/inc/instances/rm_wifi_da16xxx.h +++ b/ra/fsp/inc/instances/rm_wifi_da16xxx.h @@ -207,6 +207,12 @@ fsp_err_t RM_WIFI_DA16XXX_SntpServerIpAddressSet(uint8_t * p_server_ip_addr); *************************************************************************************************************************************/ fsp_err_t RM_WIFI_DA16XXX_SntpEnableSet(wifi_da16xxx_sntp_enable_t enable); +/**********************************************************************************************************************************//** + * Send a generic AT command to the DA16XXX and optionally receive a response + * + *************************************************************************************************************************************/ +fsp_err_t RM_WIFI_DA16XXX_GenericAtSendRcv(char const * const at_string, char * const response_buffer, uint32_t length); + /**********************************************************************************************************************************//** * Update the SNTP Timezone * diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA0E107.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA0E107.h index f96953363..8793c43b2 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA0E107.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA0E107.h @@ -466,24 +466,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -700,27 +717,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; - - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1293,9 +1296,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -1303,16 +1319,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -1515,11 +1531,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -1531,7 +1558,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -1554,15 +1581,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -1577,7 +1623,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -4696,7 +4779,7 @@ typedef struct /*!< (@ 0x400A2C00) R_RTC_C Structure #define R_PORT2_BASE 0x400A0040UL #define R_PORT3_BASE 0x400A0060UL #define R_PORT4_BASE 0x400A0080UL - #define R_PORT9_BASE 0x400A0100UL + #define R_PORT9_BASE 0x400A0120UL #define R_PORGA_BASE 0x400A1000UL #define R_PFS_BASE 0x400A0200UL #define R_PMISC_BASE 0x400A0340UL @@ -4958,6 +5041,9 @@ typedef struct /*!< (@ 0x400A2C00) R_RTC_C Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -5022,9 +5108,6 @@ typedef struct /*!< (@ 0x400A2C00) R_RTC_C Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -5244,6 +5327,9 @@ typedef struct /*!< (@ 0x400A2C00) R_RTC_C Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CRC ================ */ @@ -5319,30 +5405,49 @@ typedef struct /*!< (@ 0x400A2C00) R_RTC_C Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h index c6ad0e3ef..579766b69 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h @@ -466,24 +466,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -700,27 +717,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -3476,9 +3479,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3486,16 +3502,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -4781,11 +4797,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -4797,7 +4824,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -4820,15 +4847,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -4843,7 +4889,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -5474,17 +5557,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -6884,47 +6971,43 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -6977,7 +7060,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -7140,7 +7224,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -8529,14 +8633,16 @@ typedef struct /*!< (@ 0x40044000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -11322,23 +11428,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -13995,6 +14116,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -14059,9 +14183,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -15171,6 +15292,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -15888,30 +16012,49 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -16147,19 +16290,27 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -16865,10 +17016,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -16905,166 +17052,179 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -17494,20 +17654,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -19074,32 +19224,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A2AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A2AD.h index 06cecbfe4..9d3099773 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A2AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A2AD.h @@ -466,24 +466,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -700,27 +717,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -3389,9 +3392,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3399,16 +3415,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -3776,11 +3792,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -3792,7 +3819,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -3815,15 +3842,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -3838,7 +3884,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -5810,47 +5893,43 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -13147,6 +13226,9 @@ typedef struct /*!< (@ 0x4009C000) R_SDADC_B Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -13211,9 +13293,6 @@ typedef struct /*!< (@ 0x4009C000) R_SDADC_B Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -14269,6 +14348,9 @@ typedef struct /*!< (@ 0x4009C000) R_SDADC_B Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -14419,30 +14501,49 @@ typedef struct /*!< (@ 0x4009C000) R_SDADC_B Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -15378,10 +15479,6 @@ typedef struct /*!< (@ 0x4009C000) R_SDADC_B Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h index 753dc54bf..5e385cfaf 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h @@ -466,24 +466,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -700,27 +717,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -3275,9 +3278,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3285,16 +3301,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -3686,9 +3702,9 @@ typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure struct { __IOM uint32_t CHAC00 : 1; /*!< [0..0] CTSU Channel Enable Control A */ - uint32_t : 1; + __IOM uint32_t CHAC01 : 1; /*!< [1..1] CTSU Channel Enable Control A */ __IOM uint32_t CHAC02 : 1; /*!< [2..2] CTSU Channel Enable Control A */ - uint32_t : 1; + __IOM uint32_t CHAC03 : 1; /*!< [3..3] CTSU Channel Enable Control A */ __IOM uint32_t CHAC04 : 1; /*!< [4..4] CTSU Channel Enable Control A */ __IOM uint32_t CHAC05 : 1; /*!< [5..5] CTSU Channel Enable Control A */ __IOM uint32_t CHAC06 : 1; /*!< [6..6] CTSU Channel Enable Control A */ @@ -3774,9 +3790,9 @@ typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure struct { __IOM uint32_t CHTRC : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control A */ - uint32_t : 1; + __IOM uint32_t CHTRC01 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control A */ __IOM uint32_t CHTRC02 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control A */ - uint32_t : 1; + __IOM uint32_t CHTRC03 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control A */ __IOM uint32_t CHTRC04 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control A */ __IOM uint32_t CHTRC05 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control A */ __IOM uint32_t CHTRC06 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control A */ @@ -3962,7 +3978,8 @@ typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure __IOM uint32_t IOC : 1; /*!< [9..9] TS Pin Fixed Output Value Set */ __IOM uint32_t CFCRDMD : 1; /*!< [10..10] CFC Counter Read Mode Select */ __IOM uint32_t DCOFF : 1; /*!< [11..11] Down Converter Control */ - uint32_t : 4; + __IOM uint32_t IOCSEL : 1; /*!< [12..12] TS Pins Fixed Output Select */ + uint32_t : 3; __IOM uint32_t CFCSEL : 6; /*!< [21..16] Observation CFC Clock Select */ __IOM uint32_t CFCMODE : 1; /*!< [22..22] CFC Oscillator Calibration Mode Select */ uint32_t : 1; @@ -4046,7 +4063,294 @@ typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure }; __IM uint16_t CTSUCFCCNTL; /*!< (@ 0x00000034) CTSU CFC Counter Register */ }; -} R_CTSU2_Type; /*!< Size = 56 (0x38) */ + __IM uint32_t RESERVED1[2]; + + union + { + union + { + __IOM uint32_t CTSUOPT; /*!< (@ 0x00000040) CTSU Option Setting Register */ + + struct + { + __IOM uint32_t CCOCFEN : 1; /*!< [0..0] CCO Characteristics Correction Function Enable */ + __IOM uint32_t MCACEFN : 1; /*!< [1..1] Multi-clock Correction Function Enable */ + __IOM uint32_t MAJIRIMD : 1; /*!< [2..2] Majority Mode */ + uint32_t : 1; + __IOM uint32_t DTCLESS : 1; /*!< [4..4] Data Transfer Request Disable */ + __IOM uint32_t MTUCFEN : 1; /*!< [5..5] 5 MTUCFEN Mutual Capacitance Calculation Enable */ + uint32_t : 2; + __IOM uint32_t AJFEN : 1; /*!< [8..8] Automatic Judgment Function Enable */ + __IOM uint32_t AJINTC : 1; /*!< [9..9] Automatic Judgment Interrupt Control */ + uint32_t : 6; + __IOM uint32_t SCACTB : 4; /*!< [19..16] Sensor Counter Automatic Correction Table Number Setting */ + uint32_t : 12; + } CTSUOPT_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUOPTL; /*!< (@ 0x00000040) CTSU Option Setting Register */ + + struct + { + __IOM uint8_t AC; /*!< (@ 0x00000040) CTSU Option Setting Register */ + __IOM uint8_t AJ; /*!< (@ 0x00000041) CTSU Option Setting Register */ + }; + }; + + union + { + __IOM uint16_t CTSUOPTH; /*!< (@ 0x00000042) CTSU Option Setting Register */ + __IOM uint8_t ACTB; /*!< (@ 0x00000042) CTSU Option Setting Register */ + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUSCNTACT; /*!< (@ 0x00000044) CTSU Sensor Counter Automatic Correction Table + * Access Register */ + + struct + { + __IOM uint32_t SCNTACCOEFF : 16; /*!< [15..0] Sensor Counter Correction Coefficient Setting */ + __IOM uint32_t SCNTACCOUNT : 16; /*!< [31..16] Set the measurement value to be compared */ + } CTSUSCNTACT_b; + }; + + struct + { + __IOM uint16_t CTSUSCNTACTL; /*!< (@ 0x00000044) CTSU Option Setting Register */ + __IOM uint16_t CTSUSCNTACTH; /*!< (@ 0x00000046) CTSU Option Setting Register */ + }; + }; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t CTSUMACT1; /*!< (@ 0x0000004C) Multi-Clock Automatic Correction Table Access + * Register */ + + struct + { + __IOM uint32_t SO : 10; /*!< [9..0] Sensor offset adjustment bits for multi-clock */ + uint32_t : 6; + __IOM uint32_t OFFSETCOEFF : 16; /*!< [31..16] Offset coefficient bits for multi-clock */ + } CTSUMACT1_b; + }; + + struct + { + __IOM uint16_t CTSUMACT1L; /*!< (@ 0x0000004C) CTSU Option Setting Register */ + __IOM uint16_t CTSUMACT1H; /*!< (@ 0x0000004E) CTSU Option Setting Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUMACT2; /*!< (@ 0x00000050) Multi-Clock Automatic Correction Table Access + * Register */ + + struct + { + __IOM uint32_t SO : 10; /*!< [9..0] Sensor offset adjustment bits for multi-clock */ + uint32_t : 6; + __IOM uint32_t OFFSETCOEFF : 16; /*!< [31..16] Offset coefficient bits for multi-clock */ + } CTSUMACT2_b; + }; + + struct + { + __IOM uint16_t CTSUMACT2L; /*!< (@ 0x00000050) CTSU Option Setting Register */ + __IOM uint16_t CTSUMACT2H; /*!< (@ 0x00000052) CTSU Option Setting Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUMACT3; /*!< (@ 0x00000054) Multi-Clock Automatic Correction Table Access + * Register */ + + struct + { + __IOM uint32_t SO : 10; /*!< [9..0] Sensor offset adjustment bits for multi-clock */ + uint32_t : 6; + __IOM uint32_t OFFSETCOEFF : 16; /*!< [31..16] Offset coefficient bits for multi-clock */ + } CTSUMACT3_b; + }; + + struct + { + __IOM uint16_t CTSUMACT3L; /*!< (@ 0x00000054) CTSU Option Setting Register */ + __IOM uint16_t CTSUMACT3H; /*!< (@ 0x00000056) CTSU Option Setting Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUAJCR; /*!< (@ 0x00000058) CTSU Automatic Judgment Control Registe */ + + struct + { + __IOM uint32_t TLOT : 8; /*!< [7..0] Non-Touch Judgment Criterion Setting */ + __IOM uint32_t THOT : 8; /*!< [15..8] Touch Judgment Criterion Setting */ + __IOM uint32_t BLINI : 1; /*!< [16..16] Baseline Initialization */ + uint32_t : 3; + __IOM uint32_t JC : 2; /*!< [21..20] Judgment Condition Setting */ + uint32_t : 2; + __IOM uint32_t AJMMAT : 4; /*!< [27..24] Measured Value Moving Average Number Setting */ + __IOM uint32_t AJBMAT : 4; /*!< [31..28] Baseline Average Number Setting */ + } CTSUAJCR_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUAJCRL; /*!< (@ 0x00000058) CTSU Automatic Judgment Control Register */ + + struct + { + __IOM uint8_t AJCR0; /*!< (@ 0x00000058) CTSU Automatic Judgment Control Register */ + __IOM uint8_t AJCR1; /*!< (@ 0x00000059) CTSU Automatic Judgment Control Register */ + }; + }; + + union + { + __IOM uint16_t CTSUAJCRH; /*!< (@ 0x0000005A) CTSU Automatic Judgment Control Register */ + + struct + { + __IOM uint8_t AJCR2; /*!< (@ 0x0000005A) CTSU Automatic Judgment Control Register */ + __IOM uint8_t AJCR3; /*!< (@ 0x0000005B) CTSU Automatic Judgment Control Register */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUAJTHR; /*!< (@ 0x0000005C) CTSU Automatic Judgment Control Register */ + + struct + { + __IOM uint32_t AJTHL : 16; /*!< [15..0] Lower Threshold Setting */ + __IOM uint32_t AJTHH : 16; /*!< [31..16] Upper Threshold Setting */ + } CTSUAJTHR_b; + }; + + struct + { + __IOM uint16_t CTSUAJTHRL; /*!< (@ 0x0000005C) CTSU Automatic Judgment Control Register */ + __IOM uint16_t CTSUAJTHRH; /*!< (@ 0x0000005E) CTSU Automatic Judgment Control Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUAJMMAR; /*!< (@ 0x00000060) CTSU Threshold Register */ + + struct + { + __IOM uint32_t AJMMATI : 4; /*!< [3..0] Moving Average Count */ + uint32_t : 1; + __IOM uint32_t AJMMR : 27; /*!< [31..5] Moving Average Result */ + } CTSUAJMMAR_b; + }; + + struct + { + __IOM uint16_t CTSUAJMMARL; /*!< (@ 0x00000060) CTSU Threshold Register */ + __IOM uint16_t CTSUAJMMARH; /*!< (@ 0x00000062) CTSU Threshold Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUAJBLACT; /*!< (@ 0x00000064) CTSU Baseline Average Intermediate Result Register */ + + struct + { + __IOM uint32_t AJBLACT : 32; /*!< [31..0] Automatic determination baseline average calculation + * bits */ + } CTSUAJBLACT_b; + }; + + struct + { + __IOM uint16_t CTSUAJBLACTL; /*!< (@ 0x00000064) CTSU Baseline Average Intermediate Result Register */ + __IOM uint16_t CTSUAJBLACTH; /*!< (@ 0x00000066) CTSU Baseline Average Intermediate Result Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUAJBLAR; /*!< (@ 0x00000068) CTSU Baseline Average Result Register */ + + struct + { + __IOM uint32_t AJBLAC : 16; /*!< [15..0] Baseline Average Count */ + __IOM uint32_t AJBLAR : 16; /*!< [31..16] Baseline Average Result */ + } CTSUAJBLAR_b; + }; + + struct + { + __IOM uint16_t CTSUAJBLARL; /*!< (@ 0x00000068) CTSU Baseline Average Result Register */ + __IOM uint16_t CTSUAJBLARH; /*!< (@ 0x0000006A) CTSU Baseline Average Result Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUAJRR; /*!< (@ 0x0000006C) CTSU Automatic Judgment Result Register */ + + struct + { + __IOM uint32_t TJR0 : 1; /*!< [0..0] The judgment result when using SUCLK0 is stored. */ + __IOM uint32_t TJR1 : 1; /*!< [1..1] The judgment result when using SUCLK1 is stored. */ + __IOM uint32_t TJR2 : 1; /*!< [2..2] The judgment result when using SUCLK2 is stored. */ + __IOM uint32_t TJR3 : 1; /*!< [3..3] The judgment result when using SUCLK3 is stored. */ + __IOM uint32_t FJR : 1; /*!< [4..4] The final judgment result on multi-clock measurement + * is stored. */ + uint32_t : 3; + __IOM uint32_t SJCCR : 8; /*!< [15..8] Remaining Number of Consecutive Detections */ + uint32_t : 16; + } CTSUAJRR_b; + }; + __IOM uint16_t CTSUAJRRL; /*!< (@ 0x0000006C) CTSU Automatic Judgment Result Register */ + + struct + { + __IOM uint8_t CTSUAJRR0; /*!< (@ 0x0000006C) CTSU Automatic Judgment Result Register */ + __IOM uint8_t CTSUAJRR1; /*!< (@ 0x0000006D) CTSU Automatic Judgment Result Register */ + }; + }; +} R_CTSU2_Type; /*!< Size = 112 (0x70) */ /* =========================================================================================================================== */ /* ================ R_DEBUG ================ */ @@ -4191,11 +4495,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -4207,7 +4522,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -4230,15 +4545,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -4253,7 +4587,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -6275,47 +6646,43 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -6368,7 +6735,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -6531,7 +6899,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -7762,14 +8150,16 @@ typedef struct /*!< (@ 0x40044000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -10386,23 +10776,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -11962,6 +12367,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -12026,9 +12434,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -13049,6 +13454,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -13238,8 +13646,12 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= CTSUCHACA ======================================================= */ #define R_CTSU2_CTSUCHACA_CHAC00_Pos (0UL) /*!< CHAC00 (Bit 0) */ #define R_CTSU2_CTSUCHACA_CHAC00_Msk (0x1UL) /*!< CHAC00 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC01_Pos (1UL) /*!< CHAC01 (Bit 1) */ + #define R_CTSU2_CTSUCHACA_CHAC01_Msk (0x2UL) /*!< CHAC01 (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCHACA_CHAC02_Pos (2UL) /*!< CHAC02 (Bit 2) */ #define R_CTSU2_CTSUCHACA_CHAC02_Msk (0x4UL) /*!< CHAC02 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC03_Pos (3UL) /*!< CHAC03 (Bit 3) */ + #define R_CTSU2_CTSUCHACA_CHAC03_Msk (0x8UL) /*!< CHAC03 (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCHACA_CHAC04_Pos (4UL) /*!< CHAC04 (Bit 4) */ #define R_CTSU2_CTSUCHACA_CHAC04_Msk (0x10UL) /*!< CHAC04 (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCHACA_CHAC05_Pos (5UL) /*!< CHAC05 (Bit 5) */ @@ -13312,8 +13724,12 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ====================================================== CTSUCHTRCA ======================================================= */ #define R_CTSU2_CTSUCHTRCA_CHTRC_Pos (0UL) /*!< CHTRC (Bit 0) */ #define R_CTSU2_CTSUCHTRCA_CHTRC_Msk (0x1UL) /*!< CHTRC (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC01_Pos (1UL) /*!< CHTRC01 (Bit 1) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC01_Msk (0x2UL) /*!< CHTRC01 (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCHTRCA_CHTRC02_Pos (2UL) /*!< CHTRC02 (Bit 2) */ #define R_CTSU2_CTSUCHTRCA_CHTRC02_Msk (0x4UL) /*!< CHTRC02 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC03_Pos (3UL) /*!< CHTRC03 (Bit 3) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC03_Msk (0x8UL) /*!< CHTRC03 (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCHTRCA_CHTRC04_Pos (4UL) /*!< CHTRC04 (Bit 4) */ #define R_CTSU2_CTSUCHTRCA_CHTRC04_Msk (0x10UL) /*!< CHTRC04 (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCHTRCA_CHTRC05_Pos (5UL) /*!< CHTRC05 (Bit 5) */ @@ -13445,6 +13861,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_CTSU2_CTSUCALIB_CFCRDMD_Msk (0x400UL) /*!< CFCRDMD (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCALIB_DCOFF_Pos (11UL) /*!< DCOFF (Bit 11) */ #define R_CTSU2_CTSUCALIB_DCOFF_Msk (0x800UL) /*!< DCOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_IOCSEL_Pos (12UL) /*!< IOCSEL (Bit 12) */ + #define R_CTSU2_CTSUCALIB_IOCSEL_Msk (0x1000UL) /*!< IOCSEL (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCALIB_CFCSEL_Pos (16UL) /*!< CFCSEL (Bit 16) */ #define R_CTSU2_CTSUCALIB_CFCSEL_Msk (0x3f0000UL) /*!< CFCSEL (Bitfield-Mask: 0x3f) */ #define R_CTSU2_CTSUCALIB_CFCMODE_Pos (22UL) /*!< CFCMODE (Bit 22) */ @@ -13493,6 +13911,117 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_CTSU2_CTSUCFCCNT_CFCCNT_Pos (0UL) /*!< CFCCNT (Bit 0) */ #define R_CTSU2_CTSUCFCCNT_CFCCNT_Msk (0xffffUL) /*!< CFCCNT (Bitfield-Mask: 0xffff) */ /* ====================================================== CTSUCFCCNTL ====================================================== */ +/* ======================================================== CTSUOPT ======================================================== */ + #define R_CTSU2_CTSUOPT_CCOCFEN_Pos (0UL) /*!< CCOCFEN (Bit 0) */ + #define R_CTSU2_CTSUOPT_CCOCFEN_Msk (0x1UL) /*!< CCOCFEN (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUOPT_MCACEFN_Pos (1UL) /*!< MCACEFN (Bit 1) */ + #define R_CTSU2_CTSUOPT_MCACEFN_Msk (0x2UL) /*!< MCACEFN (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUOPT_MAJIRIMD_Pos (2UL) /*!< MAJIRIMD (Bit 2) */ + #define R_CTSU2_CTSUOPT_MAJIRIMD_Msk (0x4UL) /*!< MAJIRIMD (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUOPT_DTCLESS_Pos (4UL) /*!< DTCLESS (Bit 4) */ + #define R_CTSU2_CTSUOPT_DTCLESS_Msk (0x10UL) /*!< DTCLESS (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUOPT_MTUCFEN_Pos (5UL) /*!< MTUCFEN (Bit 5) */ + #define R_CTSU2_CTSUOPT_MTUCFEN_Msk (0x20UL) /*!< MTUCFEN (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUOPT_AJFEN_Pos (8UL) /*!< AJFEN (Bit 8) */ + #define R_CTSU2_CTSUOPT_AJFEN_Msk (0x100UL) /*!< AJFEN (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUOPT_AJINTC_Pos (9UL) /*!< AJINTC (Bit 9) */ + #define R_CTSU2_CTSUOPT_AJINTC_Msk (0x200UL) /*!< AJINTC (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUOPT_SCACTB_Pos (16UL) /*!< SCACTB (Bit 16) */ + #define R_CTSU2_CTSUOPT_SCACTB_Msk (0xf0000UL) /*!< SCACTB (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTSUOPTL ======================================================== */ +/* ========================================================== AC =========================================================== */ +/* ========================================================== AJ =========================================================== */ +/* ======================================================= CTSUOPTH ======================================================== */ +/* ========================================================= ACTB ========================================================== */ +/* ====================================================== CTSUSCNTACT ====================================================== */ + #define R_CTSU2_CTSUSCNTACT_SCNTACCOEFF_Pos (0UL) /*!< SCNTACCOEFF (Bit 0) */ + #define R_CTSU2_CTSUSCNTACT_SCNTACCOEFF_Msk (0xffffUL) /*!< SCNTACCOEFF (Bitfield-Mask: 0xffff) */ + #define R_CTSU2_CTSUSCNTACT_SCNTACCOUNT_Pos (16UL) /*!< SCNTACCOUNT (Bit 16) */ + #define R_CTSU2_CTSUSCNTACT_SCNTACCOUNT_Msk (0xffff0000UL) /*!< SCNTACCOUNT (Bitfield-Mask: 0xffff) */ +/* ===================================================== CTSUSCNTACTL ====================================================== */ +/* ===================================================== CTSUSCNTACTH ====================================================== */ +/* ======================================================= CTSUMACT1 ======================================================= */ + #define R_CTSU2_CTSUMACT1_SO_Pos (0UL) /*!< SO (Bit 0) */ + #define R_CTSU2_CTSUMACT1_SO_Msk (0x3ffUL) /*!< SO (Bitfield-Mask: 0x3ff) */ + #define R_CTSU2_CTSUMACT1_OFFSETCOEFF_Pos (16UL) /*!< OFFSETCOEFF (Bit 16) */ + #define R_CTSU2_CTSUMACT1_OFFSETCOEFF_Msk (0xffff0000UL) /*!< OFFSETCOEFF (Bitfield-Mask: 0xffff) */ +/* ====================================================== CTSUMACT1L ======================================================= */ +/* ====================================================== CTSUMACT1H ======================================================= */ +/* ======================================================= CTSUMACT2 ======================================================= */ + #define R_CTSU2_CTSUMACT2_SO_Pos (0UL) /*!< SO (Bit 0) */ + #define R_CTSU2_CTSUMACT2_SO_Msk (0x3ffUL) /*!< SO (Bitfield-Mask: 0x3ff) */ + #define R_CTSU2_CTSUMACT2_OFFSETCOEFF_Pos (16UL) /*!< OFFSETCOEFF (Bit 16) */ + #define R_CTSU2_CTSUMACT2_OFFSETCOEFF_Msk (0xffff0000UL) /*!< OFFSETCOEFF (Bitfield-Mask: 0xffff) */ +/* ====================================================== CTSUMACT2L ======================================================= */ +/* ====================================================== CTSUMACT2H ======================================================= */ +/* ======================================================= CTSUMACT3 ======================================================= */ + #define R_CTSU2_CTSUMACT3_SO_Pos (0UL) /*!< SO (Bit 0) */ + #define R_CTSU2_CTSUMACT3_SO_Msk (0x3ffUL) /*!< SO (Bitfield-Mask: 0x3ff) */ + #define R_CTSU2_CTSUMACT3_OFFSETCOEFF_Pos (16UL) /*!< OFFSETCOEFF (Bit 16) */ + #define R_CTSU2_CTSUMACT3_OFFSETCOEFF_Msk (0xffff0000UL) /*!< OFFSETCOEFF (Bitfield-Mask: 0xffff) */ +/* ====================================================== CTSUMACT3L ======================================================= */ +/* ====================================================== CTSUMACT3H ======================================================= */ +/* ======================================================= CTSUAJCR ======================================================== */ + #define R_CTSU2_CTSUAJCR_TLOT_Pos (0UL) /*!< TLOT (Bit 0) */ + #define R_CTSU2_CTSUAJCR_TLOT_Msk (0xffUL) /*!< TLOT (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUAJCR_THOT_Pos (8UL) /*!< THOT (Bit 8) */ + #define R_CTSU2_CTSUAJCR_THOT_Msk (0xff00UL) /*!< THOT (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUAJCR_BLINI_Pos (16UL) /*!< BLINI (Bit 16) */ + #define R_CTSU2_CTSUAJCR_BLINI_Msk (0x10000UL) /*!< BLINI (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUAJCR_JC_Pos (20UL) /*!< JC (Bit 20) */ + #define R_CTSU2_CTSUAJCR_JC_Msk (0x300000UL) /*!< JC (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUAJCR_AJMMAT_Pos (24UL) /*!< AJMMAT (Bit 24) */ + #define R_CTSU2_CTSUAJCR_AJMMAT_Msk (0xf000000UL) /*!< AJMMAT (Bitfield-Mask: 0x0f) */ + #define R_CTSU2_CTSUAJCR_AJBMAT_Pos (28UL) /*!< AJBMAT (Bit 28) */ + #define R_CTSU2_CTSUAJCR_AJBMAT_Msk (0xf0000000UL) /*!< AJBMAT (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTSUAJCRL ======================================================= */ +/* ========================================================= AJCR0 ========================================================= */ +/* ========================================================= AJCR1 ========================================================= */ +/* ======================================================= CTSUAJCRH ======================================================= */ +/* ========================================================= AJCR2 ========================================================= */ +/* ========================================================= AJCR3 ========================================================= */ +/* ======================================================= CTSUAJTHR ======================================================= */ + #define R_CTSU2_CTSUAJTHR_AJTHL_Pos (0UL) /*!< AJTHL (Bit 0) */ + #define R_CTSU2_CTSUAJTHR_AJTHL_Msk (0xffffUL) /*!< AJTHL (Bitfield-Mask: 0xffff) */ + #define R_CTSU2_CTSUAJTHR_AJTHH_Pos (16UL) /*!< AJTHH (Bit 16) */ + #define R_CTSU2_CTSUAJTHR_AJTHH_Msk (0xffff0000UL) /*!< AJTHH (Bitfield-Mask: 0xffff) */ +/* ====================================================== CTSUAJTHRL ======================================================= */ +/* ====================================================== CTSUAJTHRH ======================================================= */ +/* ====================================================== CTSUAJMMAR ======================================================= */ + #define R_CTSU2_CTSUAJMMAR_AJMMATI_Pos (0UL) /*!< AJMMATI (Bit 0) */ + #define R_CTSU2_CTSUAJMMAR_AJMMATI_Msk (0xfUL) /*!< AJMMATI (Bitfield-Mask: 0x0f) */ + #define R_CTSU2_CTSUAJMMAR_AJMMR_Pos (5UL) /*!< AJMMR (Bit 5) */ + #define R_CTSU2_CTSUAJMMAR_AJMMR_Msk (0xffffffe0UL) /*!< AJMMR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== CTSUAJMMARL ====================================================== */ +/* ====================================================== CTSUAJMMARH ====================================================== */ +/* ====================================================== CTSUAJBLACT ====================================================== */ + #define R_CTSU2_CTSUAJBLACT_AJBLACT_Pos (0UL) /*!< AJBLACT (Bit 0) */ + #define R_CTSU2_CTSUAJBLACT_AJBLACT_Msk (0xffffffffUL) /*!< AJBLACT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CTSUAJBLACTL ====================================================== */ +/* ===================================================== CTSUAJBLACTH ====================================================== */ +/* ====================================================== CTSUAJBLAR ======================================================= */ + #define R_CTSU2_CTSUAJBLAR_AJBLAC_Pos (0UL) /*!< AJBLAC (Bit 0) */ + #define R_CTSU2_CTSUAJBLAR_AJBLAC_Msk (0xffffUL) /*!< AJBLAC (Bitfield-Mask: 0xffff) */ + #define R_CTSU2_CTSUAJBLAR_AJBLAR_Pos (16UL) /*!< AJBLAR (Bit 16) */ + #define R_CTSU2_CTSUAJBLAR_AJBLAR_Msk (0xffff0000UL) /*!< AJBLAR (Bitfield-Mask: 0xffff) */ +/* ====================================================== CTSUAJBLARL ====================================================== */ +/* ====================================================== CTSUAJBLARH ====================================================== */ +/* ======================================================= CTSUAJRR ======================================================== */ + #define R_CTSU2_CTSUAJRR_TJR0_Pos (0UL) /*!< TJR0 (Bit 0) */ + #define R_CTSU2_CTSUAJRR_TJR0_Msk (0x1UL) /*!< TJR0 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUAJRR_TJR1_Pos (1UL) /*!< TJR1 (Bit 1) */ + #define R_CTSU2_CTSUAJRR_TJR1_Msk (0x2UL) /*!< TJR1 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUAJRR_TJR2_Pos (2UL) /*!< TJR2 (Bit 2) */ + #define R_CTSU2_CTSUAJRR_TJR2_Msk (0x4UL) /*!< TJR2 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUAJRR_TJR3_Pos (3UL) /*!< TJR3 (Bit 3) */ + #define R_CTSU2_CTSUAJRR_TJR3_Msk (0x8UL) /*!< TJR3 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUAJRR_FJR_Pos (4UL) /*!< FJR (Bit 4) */ + #define R_CTSU2_CTSUAJRR_FJR_Msk (0x10UL) /*!< FJR (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUAJRR_SJCCR_Pos (8UL) /*!< SJCCR (Bit 8) */ + #define R_CTSU2_CTSUAJRR_SJCCR_Msk (0xff00UL) /*!< SJCCR (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUAJRRL ======================================================= */ +/* ======================================================= CTSUAJRR0 ======================================================= */ +/* ======================================================= CTSUAJRR1 ======================================================= */ /* =========================================================================================================================== */ /* ================ R_DEBUG ================ */ @@ -13553,30 +14082,49 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -14534,10 +15082,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -14574,166 +15118,179 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -15118,20 +15675,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -16613,32 +17160,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h index e8f0a20a6..0bd5793d2 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h @@ -466,24 +466,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -700,27 +717,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -3030,9 +3033,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3040,16 +3056,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -3417,11 +3433,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -3433,7 +3460,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -3456,15 +3483,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -3479,7 +3525,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -5457,47 +5540,43 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -5550,7 +5629,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -5713,7 +5793,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -6662,7 +6762,9 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ uint32_t : 3; __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; } BST_b; }; @@ -6683,7 +6785,9 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ uint32_t : 3; __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; } BSTE_b; }; @@ -6704,28 +6808,32 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ uint32_t : 3; __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; } BIE_b; }; union { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ struct { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 11; + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; } BSTFC_b; }; @@ -7008,7 +7116,8 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT0_b; @@ -7025,7 +7134,8 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT1_b; @@ -7042,7 +7152,8 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT2_b; @@ -7059,7 +7170,8 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT3_b; @@ -7077,7 +7189,8 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } SVDCT_b; @@ -7227,7 +7340,20 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28[2]; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; union { @@ -10205,23 +10331,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -11777,6 +11918,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -11841,9 +11985,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -12748,6 +12889,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -12898,30 +13042,49 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -13856,10 +14019,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -13896,166 +14055,179 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -14550,6 +14722,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ /* ========================================================= BSTE ========================================================== */ #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ @@ -14565,6 +14739,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ /* ========================================================== BIE ========================================================== */ #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ @@ -14580,6 +14756,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ /* ========================================================= BSTFC ========================================================= */ #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ @@ -14595,6 +14773,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ /* ========================================================= NTST ========================================================== */ #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ @@ -14797,6 +14977,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT1 ========================================================= */ @@ -14808,6 +14992,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT2 ========================================================= */ @@ -14819,6 +15007,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT3 ========================================================= */ @@ -14830,6 +15022,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ @@ -14843,6 +15039,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================= SDCTPIDL ======================================================== */ @@ -14904,6 +15104,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ /* ======================================================== BITCNT ========================================================= */ #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ @@ -16381,32 +16588,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E307.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E307.h index 955c9ed0f..9f3f77d80 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E307.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E307.h @@ -466,24 +466,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -700,27 +717,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -3189,9 +3192,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3199,16 +3215,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -3576,11 +3592,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -3592,7 +3619,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -3615,15 +3642,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -3638,7 +3684,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -5616,47 +5699,43 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -5709,7 +5788,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -5872,7 +5952,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -7103,14 +7203,16 @@ typedef struct /*!< (@ 0x40044000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -9727,23 +9829,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -11178,6 +11295,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -11242,9 +11362,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -12207,6 +12324,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -12357,30 +12477,49 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -13315,10 +13454,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -13355,166 +13490,179 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -13899,20 +14047,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -15394,32 +15532,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h index ed89f0ffc..fd96fcf47 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h @@ -466,24 +466,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -700,27 +717,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -3334,9 +3337,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3344,16 +3360,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -4212,9 +4228,9 @@ typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure struct { __IOM uint32_t CHAC00 : 1; /*!< [0..0] CTSU Channel Enable Control A */ - uint32_t : 1; + __IOM uint32_t CHAC01 : 1; /*!< [1..1] CTSU Channel Enable Control A */ __IOM uint32_t CHAC02 : 1; /*!< [2..2] CTSU Channel Enable Control A */ - uint32_t : 1; + __IOM uint32_t CHAC03 : 1; /*!< [3..3] CTSU Channel Enable Control A */ __IOM uint32_t CHAC04 : 1; /*!< [4..4] CTSU Channel Enable Control A */ __IOM uint32_t CHAC05 : 1; /*!< [5..5] CTSU Channel Enable Control A */ __IOM uint32_t CHAC06 : 1; /*!< [6..6] CTSU Channel Enable Control A */ @@ -4300,9 +4316,9 @@ typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure struct { __IOM uint32_t CHTRC : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control A */ - uint32_t : 1; + __IOM uint32_t CHTRC01 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control A */ __IOM uint32_t CHTRC02 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control A */ - uint32_t : 1; + __IOM uint32_t CHTRC03 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control A */ __IOM uint32_t CHTRC04 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control A */ __IOM uint32_t CHTRC05 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control A */ __IOM uint32_t CHTRC06 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control A */ @@ -4488,7 +4504,8 @@ typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure __IOM uint32_t IOC : 1; /*!< [9..9] TS Pin Fixed Output Value Set */ __IOM uint32_t CFCRDMD : 1; /*!< [10..10] CFC Counter Read Mode Select */ __IOM uint32_t DCOFF : 1; /*!< [11..11] Down Converter Control */ - uint32_t : 4; + __IOM uint32_t IOCSEL : 1; /*!< [12..12] TS Pins Fixed Output Select */ + uint32_t : 3; __IOM uint32_t CFCSEL : 6; /*!< [21..16] Observation CFC Clock Select */ __IOM uint32_t CFCMODE : 1; /*!< [22..22] CFC Oscillator Calibration Mode Select */ uint32_t : 1; @@ -4572,7 +4589,294 @@ typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure }; __IM uint16_t CTSUCFCCNTL; /*!< (@ 0x00000034) CTSU CFC Counter Register */ }; -} R_CTSU2_Type; /*!< Size = 56 (0x38) */ + __IM uint32_t RESERVED1[2]; + + union + { + union + { + __IOM uint32_t CTSUOPT; /*!< (@ 0x00000040) CTSU Option Setting Register */ + + struct + { + __IOM uint32_t CCOCFEN : 1; /*!< [0..0] CCO Characteristics Correction Function Enable */ + __IOM uint32_t MCACEFN : 1; /*!< [1..1] Multi-clock Correction Function Enable */ + __IOM uint32_t MAJIRIMD : 1; /*!< [2..2] Majority Mode */ + uint32_t : 1; + __IOM uint32_t DTCLESS : 1; /*!< [4..4] Data Transfer Request Disable */ + __IOM uint32_t MTUCFEN : 1; /*!< [5..5] 5 MTUCFEN Mutual Capacitance Calculation Enable */ + uint32_t : 2; + __IOM uint32_t AJFEN : 1; /*!< [8..8] Automatic Judgment Function Enable */ + __IOM uint32_t AJINTC : 1; /*!< [9..9] Automatic Judgment Interrupt Control */ + uint32_t : 6; + __IOM uint32_t SCACTB : 4; /*!< [19..16] Sensor Counter Automatic Correction Table Number Setting */ + uint32_t : 12; + } CTSUOPT_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUOPTL; /*!< (@ 0x00000040) CTSU Option Setting Register */ + + struct + { + __IOM uint8_t AC; /*!< (@ 0x00000040) CTSU Option Setting Register */ + __IOM uint8_t AJ; /*!< (@ 0x00000041) CTSU Option Setting Register */ + }; + }; + + union + { + __IOM uint16_t CTSUOPTH; /*!< (@ 0x00000042) CTSU Option Setting Register */ + __IOM uint8_t ACTB; /*!< (@ 0x00000042) CTSU Option Setting Register */ + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUSCNTACT; /*!< (@ 0x00000044) CTSU Sensor Counter Automatic Correction Table + * Access Register */ + + struct + { + __IOM uint32_t SCNTACCOEFF : 16; /*!< [15..0] Sensor Counter Correction Coefficient Setting */ + __IOM uint32_t SCNTACCOUNT : 16; /*!< [31..16] Set the measurement value to be compared */ + } CTSUSCNTACT_b; + }; + + struct + { + __IOM uint16_t CTSUSCNTACTL; /*!< (@ 0x00000044) CTSU Option Setting Register */ + __IOM uint16_t CTSUSCNTACTH; /*!< (@ 0x00000046) CTSU Option Setting Register */ + }; + }; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t CTSUMACT1; /*!< (@ 0x0000004C) Multi-Clock Automatic Correction Table Access + * Register */ + + struct + { + __IOM uint32_t SO : 10; /*!< [9..0] Sensor offset adjustment bits for multi-clock */ + uint32_t : 6; + __IOM uint32_t OFFSETCOEFF : 16; /*!< [31..16] Offset coefficient bits for multi-clock */ + } CTSUMACT1_b; + }; + + struct + { + __IOM uint16_t CTSUMACT1L; /*!< (@ 0x0000004C) CTSU Option Setting Register */ + __IOM uint16_t CTSUMACT1H; /*!< (@ 0x0000004E) CTSU Option Setting Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUMACT2; /*!< (@ 0x00000050) Multi-Clock Automatic Correction Table Access + * Register */ + + struct + { + __IOM uint32_t SO : 10; /*!< [9..0] Sensor offset adjustment bits for multi-clock */ + uint32_t : 6; + __IOM uint32_t OFFSETCOEFF : 16; /*!< [31..16] Offset coefficient bits for multi-clock */ + } CTSUMACT2_b; + }; + + struct + { + __IOM uint16_t CTSUMACT2L; /*!< (@ 0x00000050) CTSU Option Setting Register */ + __IOM uint16_t CTSUMACT2H; /*!< (@ 0x00000052) CTSU Option Setting Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUMACT3; /*!< (@ 0x00000054) Multi-Clock Automatic Correction Table Access + * Register */ + + struct + { + __IOM uint32_t SO : 10; /*!< [9..0] Sensor offset adjustment bits for multi-clock */ + uint32_t : 6; + __IOM uint32_t OFFSETCOEFF : 16; /*!< [31..16] Offset coefficient bits for multi-clock */ + } CTSUMACT3_b; + }; + + struct + { + __IOM uint16_t CTSUMACT3L; /*!< (@ 0x00000054) CTSU Option Setting Register */ + __IOM uint16_t CTSUMACT3H; /*!< (@ 0x00000056) CTSU Option Setting Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUAJCR; /*!< (@ 0x00000058) CTSU Automatic Judgment Control Registe */ + + struct + { + __IOM uint32_t TLOT : 8; /*!< [7..0] Non-Touch Judgment Criterion Setting */ + __IOM uint32_t THOT : 8; /*!< [15..8] Touch Judgment Criterion Setting */ + __IOM uint32_t BLINI : 1; /*!< [16..16] Baseline Initialization */ + uint32_t : 3; + __IOM uint32_t JC : 2; /*!< [21..20] Judgment Condition Setting */ + uint32_t : 2; + __IOM uint32_t AJMMAT : 4; /*!< [27..24] Measured Value Moving Average Number Setting */ + __IOM uint32_t AJBMAT : 4; /*!< [31..28] Baseline Average Number Setting */ + } CTSUAJCR_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUAJCRL; /*!< (@ 0x00000058) CTSU Automatic Judgment Control Register */ + + struct + { + __IOM uint8_t AJCR0; /*!< (@ 0x00000058) CTSU Automatic Judgment Control Register */ + __IOM uint8_t AJCR1; /*!< (@ 0x00000059) CTSU Automatic Judgment Control Register */ + }; + }; + + union + { + __IOM uint16_t CTSUAJCRH; /*!< (@ 0x0000005A) CTSU Automatic Judgment Control Register */ + + struct + { + __IOM uint8_t AJCR2; /*!< (@ 0x0000005A) CTSU Automatic Judgment Control Register */ + __IOM uint8_t AJCR3; /*!< (@ 0x0000005B) CTSU Automatic Judgment Control Register */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUAJTHR; /*!< (@ 0x0000005C) CTSU Automatic Judgment Control Register */ + + struct + { + __IOM uint32_t AJTHL : 16; /*!< [15..0] Lower Threshold Setting */ + __IOM uint32_t AJTHH : 16; /*!< [31..16] Upper Threshold Setting */ + } CTSUAJTHR_b; + }; + + struct + { + __IOM uint16_t CTSUAJTHRL; /*!< (@ 0x0000005C) CTSU Automatic Judgment Control Register */ + __IOM uint16_t CTSUAJTHRH; /*!< (@ 0x0000005E) CTSU Automatic Judgment Control Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUAJMMAR; /*!< (@ 0x00000060) CTSU Threshold Register */ + + struct + { + __IOM uint32_t AJMMATI : 4; /*!< [3..0] Moving Average Count */ + uint32_t : 1; + __IOM uint32_t AJMMR : 27; /*!< [31..5] Moving Average Result */ + } CTSUAJMMAR_b; + }; + + struct + { + __IOM uint16_t CTSUAJMMARL; /*!< (@ 0x00000060) CTSU Threshold Register */ + __IOM uint16_t CTSUAJMMARH; /*!< (@ 0x00000062) CTSU Threshold Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUAJBLACT; /*!< (@ 0x00000064) CTSU Baseline Average Intermediate Result Register */ + + struct + { + __IOM uint32_t AJBLACT : 32; /*!< [31..0] Automatic determination baseline average calculation + * bits */ + } CTSUAJBLACT_b; + }; + + struct + { + __IOM uint16_t CTSUAJBLACTL; /*!< (@ 0x00000064) CTSU Baseline Average Intermediate Result Register */ + __IOM uint16_t CTSUAJBLACTH; /*!< (@ 0x00000066) CTSU Baseline Average Intermediate Result Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUAJBLAR; /*!< (@ 0x00000068) CTSU Baseline Average Result Register */ + + struct + { + __IOM uint32_t AJBLAC : 16; /*!< [15..0] Baseline Average Count */ + __IOM uint32_t AJBLAR : 16; /*!< [31..16] Baseline Average Result */ + } CTSUAJBLAR_b; + }; + + struct + { + __IOM uint16_t CTSUAJBLARL; /*!< (@ 0x00000068) CTSU Baseline Average Result Register */ + __IOM uint16_t CTSUAJBLARH; /*!< (@ 0x0000006A) CTSU Baseline Average Result Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUAJRR; /*!< (@ 0x0000006C) CTSU Automatic Judgment Result Register */ + + struct + { + __IOM uint32_t TJR0 : 1; /*!< [0..0] The judgment result when using SUCLK0 is stored. */ + __IOM uint32_t TJR1 : 1; /*!< [1..1] The judgment result when using SUCLK1 is stored. */ + __IOM uint32_t TJR2 : 1; /*!< [2..2] The judgment result when using SUCLK2 is stored. */ + __IOM uint32_t TJR3 : 1; /*!< [3..3] The judgment result when using SUCLK3 is stored. */ + __IOM uint32_t FJR : 1; /*!< [4..4] The final judgment result on multi-clock measurement + * is stored. */ + uint32_t : 3; + __IOM uint32_t SJCCR : 8; /*!< [15..8] Remaining Number of Consecutive Detections */ + uint32_t : 16; + } CTSUAJRR_b; + }; + __IOM uint16_t CTSUAJRRL; /*!< (@ 0x0000006C) CTSU Automatic Judgment Result Register */ + + struct + { + __IOM uint8_t CTSUAJRR0; /*!< (@ 0x0000006C) CTSU Automatic Judgment Result Register */ + __IOM uint8_t CTSUAJRR1; /*!< (@ 0x0000006D) CTSU Automatic Judgment Result Register */ + }; + }; +} R_CTSU2_Type; /*!< Size = 112 (0x70) */ /* =========================================================================================================================== */ /* ================ R_DAC ================ */ @@ -4865,11 +5169,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -4881,7 +5196,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -4904,15 +5219,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -4927,7 +5261,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -6949,47 +7320,43 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -7042,7 +7409,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -7205,7 +7573,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -8436,14 +8824,16 @@ typedef struct /*!< (@ 0x40044000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -11060,23 +11450,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -12642,6 +13047,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -12706,9 +13114,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -13754,6 +14159,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -14345,8 +14753,12 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= CTSUCHACA ======================================================= */ #define R_CTSU2_CTSUCHACA_CHAC00_Pos (0UL) /*!< CHAC00 (Bit 0) */ #define R_CTSU2_CTSUCHACA_CHAC00_Msk (0x1UL) /*!< CHAC00 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC01_Pos (1UL) /*!< CHAC01 (Bit 1) */ + #define R_CTSU2_CTSUCHACA_CHAC01_Msk (0x2UL) /*!< CHAC01 (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCHACA_CHAC02_Pos (2UL) /*!< CHAC02 (Bit 2) */ #define R_CTSU2_CTSUCHACA_CHAC02_Msk (0x4UL) /*!< CHAC02 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC03_Pos (3UL) /*!< CHAC03 (Bit 3) */ + #define R_CTSU2_CTSUCHACA_CHAC03_Msk (0x8UL) /*!< CHAC03 (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCHACA_CHAC04_Pos (4UL) /*!< CHAC04 (Bit 4) */ #define R_CTSU2_CTSUCHACA_CHAC04_Msk (0x10UL) /*!< CHAC04 (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCHACA_CHAC05_Pos (5UL) /*!< CHAC05 (Bit 5) */ @@ -14419,8 +14831,12 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ====================================================== CTSUCHTRCA ======================================================= */ #define R_CTSU2_CTSUCHTRCA_CHTRC_Pos (0UL) /*!< CHTRC (Bit 0) */ #define R_CTSU2_CTSUCHTRCA_CHTRC_Msk (0x1UL) /*!< CHTRC (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC01_Pos (1UL) /*!< CHTRC01 (Bit 1) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC01_Msk (0x2UL) /*!< CHTRC01 (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCHTRCA_CHTRC02_Pos (2UL) /*!< CHTRC02 (Bit 2) */ #define R_CTSU2_CTSUCHTRCA_CHTRC02_Msk (0x4UL) /*!< CHTRC02 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC03_Pos (3UL) /*!< CHTRC03 (Bit 3) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC03_Msk (0x8UL) /*!< CHTRC03 (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCHTRCA_CHTRC04_Pos (4UL) /*!< CHTRC04 (Bit 4) */ #define R_CTSU2_CTSUCHTRCA_CHTRC04_Msk (0x10UL) /*!< CHTRC04 (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCHTRCA_CHTRC05_Pos (5UL) /*!< CHTRC05 (Bit 5) */ @@ -14552,6 +14968,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_CTSU2_CTSUCALIB_CFCRDMD_Msk (0x400UL) /*!< CFCRDMD (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCALIB_DCOFF_Pos (11UL) /*!< DCOFF (Bit 11) */ #define R_CTSU2_CTSUCALIB_DCOFF_Msk (0x800UL) /*!< DCOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_IOCSEL_Pos (12UL) /*!< IOCSEL (Bit 12) */ + #define R_CTSU2_CTSUCALIB_IOCSEL_Msk (0x1000UL) /*!< IOCSEL (Bitfield-Mask: 0x01) */ #define R_CTSU2_CTSUCALIB_CFCSEL_Pos (16UL) /*!< CFCSEL (Bit 16) */ #define R_CTSU2_CTSUCALIB_CFCSEL_Msk (0x3f0000UL) /*!< CFCSEL (Bitfield-Mask: 0x3f) */ #define R_CTSU2_CTSUCALIB_CFCMODE_Pos (22UL) /*!< CFCMODE (Bit 22) */ @@ -14600,6 +15018,117 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_CTSU2_CTSUCFCCNT_CFCCNT_Pos (0UL) /*!< CFCCNT (Bit 0) */ #define R_CTSU2_CTSUCFCCNT_CFCCNT_Msk (0xffffUL) /*!< CFCCNT (Bitfield-Mask: 0xffff) */ /* ====================================================== CTSUCFCCNTL ====================================================== */ +/* ======================================================== CTSUOPT ======================================================== */ + #define R_CTSU2_CTSUOPT_CCOCFEN_Pos (0UL) /*!< CCOCFEN (Bit 0) */ + #define R_CTSU2_CTSUOPT_CCOCFEN_Msk (0x1UL) /*!< CCOCFEN (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUOPT_MCACEFN_Pos (1UL) /*!< MCACEFN (Bit 1) */ + #define R_CTSU2_CTSUOPT_MCACEFN_Msk (0x2UL) /*!< MCACEFN (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUOPT_MAJIRIMD_Pos (2UL) /*!< MAJIRIMD (Bit 2) */ + #define R_CTSU2_CTSUOPT_MAJIRIMD_Msk (0x4UL) /*!< MAJIRIMD (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUOPT_DTCLESS_Pos (4UL) /*!< DTCLESS (Bit 4) */ + #define R_CTSU2_CTSUOPT_DTCLESS_Msk (0x10UL) /*!< DTCLESS (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUOPT_MTUCFEN_Pos (5UL) /*!< MTUCFEN (Bit 5) */ + #define R_CTSU2_CTSUOPT_MTUCFEN_Msk (0x20UL) /*!< MTUCFEN (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUOPT_AJFEN_Pos (8UL) /*!< AJFEN (Bit 8) */ + #define R_CTSU2_CTSUOPT_AJFEN_Msk (0x100UL) /*!< AJFEN (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUOPT_AJINTC_Pos (9UL) /*!< AJINTC (Bit 9) */ + #define R_CTSU2_CTSUOPT_AJINTC_Msk (0x200UL) /*!< AJINTC (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUOPT_SCACTB_Pos (16UL) /*!< SCACTB (Bit 16) */ + #define R_CTSU2_CTSUOPT_SCACTB_Msk (0xf0000UL) /*!< SCACTB (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTSUOPTL ======================================================== */ +/* ========================================================== AC =========================================================== */ +/* ========================================================== AJ =========================================================== */ +/* ======================================================= CTSUOPTH ======================================================== */ +/* ========================================================= ACTB ========================================================== */ +/* ====================================================== CTSUSCNTACT ====================================================== */ + #define R_CTSU2_CTSUSCNTACT_SCNTACCOEFF_Pos (0UL) /*!< SCNTACCOEFF (Bit 0) */ + #define R_CTSU2_CTSUSCNTACT_SCNTACCOEFF_Msk (0xffffUL) /*!< SCNTACCOEFF (Bitfield-Mask: 0xffff) */ + #define R_CTSU2_CTSUSCNTACT_SCNTACCOUNT_Pos (16UL) /*!< SCNTACCOUNT (Bit 16) */ + #define R_CTSU2_CTSUSCNTACT_SCNTACCOUNT_Msk (0xffff0000UL) /*!< SCNTACCOUNT (Bitfield-Mask: 0xffff) */ +/* ===================================================== CTSUSCNTACTL ====================================================== */ +/* ===================================================== CTSUSCNTACTH ====================================================== */ +/* ======================================================= CTSUMACT1 ======================================================= */ + #define R_CTSU2_CTSUMACT1_SO_Pos (0UL) /*!< SO (Bit 0) */ + #define R_CTSU2_CTSUMACT1_SO_Msk (0x3ffUL) /*!< SO (Bitfield-Mask: 0x3ff) */ + #define R_CTSU2_CTSUMACT1_OFFSETCOEFF_Pos (16UL) /*!< OFFSETCOEFF (Bit 16) */ + #define R_CTSU2_CTSUMACT1_OFFSETCOEFF_Msk (0xffff0000UL) /*!< OFFSETCOEFF (Bitfield-Mask: 0xffff) */ +/* ====================================================== CTSUMACT1L ======================================================= */ +/* ====================================================== CTSUMACT1H ======================================================= */ +/* ======================================================= CTSUMACT2 ======================================================= */ + #define R_CTSU2_CTSUMACT2_SO_Pos (0UL) /*!< SO (Bit 0) */ + #define R_CTSU2_CTSUMACT2_SO_Msk (0x3ffUL) /*!< SO (Bitfield-Mask: 0x3ff) */ + #define R_CTSU2_CTSUMACT2_OFFSETCOEFF_Pos (16UL) /*!< OFFSETCOEFF (Bit 16) */ + #define R_CTSU2_CTSUMACT2_OFFSETCOEFF_Msk (0xffff0000UL) /*!< OFFSETCOEFF (Bitfield-Mask: 0xffff) */ +/* ====================================================== CTSUMACT2L ======================================================= */ +/* ====================================================== CTSUMACT2H ======================================================= */ +/* ======================================================= CTSUMACT3 ======================================================= */ + #define R_CTSU2_CTSUMACT3_SO_Pos (0UL) /*!< SO (Bit 0) */ + #define R_CTSU2_CTSUMACT3_SO_Msk (0x3ffUL) /*!< SO (Bitfield-Mask: 0x3ff) */ + #define R_CTSU2_CTSUMACT3_OFFSETCOEFF_Pos (16UL) /*!< OFFSETCOEFF (Bit 16) */ + #define R_CTSU2_CTSUMACT3_OFFSETCOEFF_Msk (0xffff0000UL) /*!< OFFSETCOEFF (Bitfield-Mask: 0xffff) */ +/* ====================================================== CTSUMACT3L ======================================================= */ +/* ====================================================== CTSUMACT3H ======================================================= */ +/* ======================================================= CTSUAJCR ======================================================== */ + #define R_CTSU2_CTSUAJCR_TLOT_Pos (0UL) /*!< TLOT (Bit 0) */ + #define R_CTSU2_CTSUAJCR_TLOT_Msk (0xffUL) /*!< TLOT (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUAJCR_THOT_Pos (8UL) /*!< THOT (Bit 8) */ + #define R_CTSU2_CTSUAJCR_THOT_Msk (0xff00UL) /*!< THOT (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUAJCR_BLINI_Pos (16UL) /*!< BLINI (Bit 16) */ + #define R_CTSU2_CTSUAJCR_BLINI_Msk (0x10000UL) /*!< BLINI (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUAJCR_JC_Pos (20UL) /*!< JC (Bit 20) */ + #define R_CTSU2_CTSUAJCR_JC_Msk (0x300000UL) /*!< JC (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUAJCR_AJMMAT_Pos (24UL) /*!< AJMMAT (Bit 24) */ + #define R_CTSU2_CTSUAJCR_AJMMAT_Msk (0xf000000UL) /*!< AJMMAT (Bitfield-Mask: 0x0f) */ + #define R_CTSU2_CTSUAJCR_AJBMAT_Pos (28UL) /*!< AJBMAT (Bit 28) */ + #define R_CTSU2_CTSUAJCR_AJBMAT_Msk (0xf0000000UL) /*!< AJBMAT (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTSUAJCRL ======================================================= */ +/* ========================================================= AJCR0 ========================================================= */ +/* ========================================================= AJCR1 ========================================================= */ +/* ======================================================= CTSUAJCRH ======================================================= */ +/* ========================================================= AJCR2 ========================================================= */ +/* ========================================================= AJCR3 ========================================================= */ +/* ======================================================= CTSUAJTHR ======================================================= */ + #define R_CTSU2_CTSUAJTHR_AJTHL_Pos (0UL) /*!< AJTHL (Bit 0) */ + #define R_CTSU2_CTSUAJTHR_AJTHL_Msk (0xffffUL) /*!< AJTHL (Bitfield-Mask: 0xffff) */ + #define R_CTSU2_CTSUAJTHR_AJTHH_Pos (16UL) /*!< AJTHH (Bit 16) */ + #define R_CTSU2_CTSUAJTHR_AJTHH_Msk (0xffff0000UL) /*!< AJTHH (Bitfield-Mask: 0xffff) */ +/* ====================================================== CTSUAJTHRL ======================================================= */ +/* ====================================================== CTSUAJTHRH ======================================================= */ +/* ====================================================== CTSUAJMMAR ======================================================= */ + #define R_CTSU2_CTSUAJMMAR_AJMMATI_Pos (0UL) /*!< AJMMATI (Bit 0) */ + #define R_CTSU2_CTSUAJMMAR_AJMMATI_Msk (0xfUL) /*!< AJMMATI (Bitfield-Mask: 0x0f) */ + #define R_CTSU2_CTSUAJMMAR_AJMMR_Pos (5UL) /*!< AJMMR (Bit 5) */ + #define R_CTSU2_CTSUAJMMAR_AJMMR_Msk (0xffffffe0UL) /*!< AJMMR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== CTSUAJMMARL ====================================================== */ +/* ====================================================== CTSUAJMMARH ====================================================== */ +/* ====================================================== CTSUAJBLACT ====================================================== */ + #define R_CTSU2_CTSUAJBLACT_AJBLACT_Pos (0UL) /*!< AJBLACT (Bit 0) */ + #define R_CTSU2_CTSUAJBLACT_AJBLACT_Msk (0xffffffffUL) /*!< AJBLACT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CTSUAJBLACTL ====================================================== */ +/* ===================================================== CTSUAJBLACTH ====================================================== */ +/* ====================================================== CTSUAJBLAR ======================================================= */ + #define R_CTSU2_CTSUAJBLAR_AJBLAC_Pos (0UL) /*!< AJBLAC (Bit 0) */ + #define R_CTSU2_CTSUAJBLAR_AJBLAC_Msk (0xffffUL) /*!< AJBLAC (Bitfield-Mask: 0xffff) */ + #define R_CTSU2_CTSUAJBLAR_AJBLAR_Pos (16UL) /*!< AJBLAR (Bit 16) */ + #define R_CTSU2_CTSUAJBLAR_AJBLAR_Msk (0xffff0000UL) /*!< AJBLAR (Bitfield-Mask: 0xffff) */ +/* ====================================================== CTSUAJBLARL ====================================================== */ +/* ====================================================== CTSUAJBLARH ====================================================== */ +/* ======================================================= CTSUAJRR ======================================================== */ + #define R_CTSU2_CTSUAJRR_TJR0_Pos (0UL) /*!< TJR0 (Bit 0) */ + #define R_CTSU2_CTSUAJRR_TJR0_Msk (0x1UL) /*!< TJR0 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUAJRR_TJR1_Pos (1UL) /*!< TJR1 (Bit 1) */ + #define R_CTSU2_CTSUAJRR_TJR1_Msk (0x2UL) /*!< TJR1 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUAJRR_TJR2_Pos (2UL) /*!< TJR2 (Bit 2) */ + #define R_CTSU2_CTSUAJRR_TJR2_Msk (0x4UL) /*!< TJR2 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUAJRR_TJR3_Pos (3UL) /*!< TJR3 (Bit 3) */ + #define R_CTSU2_CTSUAJRR_TJR3_Msk (0x8UL) /*!< TJR3 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUAJRR_FJR_Pos (4UL) /*!< FJR (Bit 4) */ + #define R_CTSU2_CTSUAJRR_FJR_Msk (0x10UL) /*!< FJR (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUAJRR_SJCCR_Pos (8UL) /*!< SJCCR (Bit 8) */ + #define R_CTSU2_CTSUAJRR_SJCCR_Msk (0xff00UL) /*!< SJCCR (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUAJRRL ======================================================= */ +/* ======================================================= CTSUAJRR0 ======================================================= */ +/* ======================================================= CTSUAJRR1 ======================================================= */ /* =========================================================================================================================== */ /* ================ R_DAC ================ */ @@ -14698,30 +15227,49 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -15679,10 +16227,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -15719,166 +16263,179 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -16263,20 +16820,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -17758,32 +18305,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h index f4c02722e..e3fff4b58 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h @@ -468,24 +468,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -702,27 +719,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1184,7 +1187,7 @@ typedef struct } R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) */ typedef struct { @@ -3205,15 +3208,16 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - uint32_t : 1; + __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; + __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ @@ -3252,7 +3256,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ uint32_t : 1; __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; + __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ + uint32_t : 3; __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ uint32_t : 3; __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ @@ -3293,7 +3298,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - uint32_t : 3; + __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ + uint32_t : 2; } PSARD_b; }; @@ -3333,7 +3339,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ + uint32_t : 27; } MSSAR_b; }; @@ -3498,9 +3505,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3508,16 +3528,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -4441,7 +4461,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -4457,7 +4493,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -4755,11 +4791,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -4771,7 +4818,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -4794,15 +4841,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -4817,7 +4883,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -5300,17 +5403,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -6654,47 +6761,43 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -6747,7 +6850,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -6910,7 +7014,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -7354,9 +7478,7 @@ typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -8295,14 +8417,16 @@ typedef struct /*!< (@ 0x40083000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -10919,23 +11043,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -13062,20 +13201,7 @@ typedef struct /*!< (@ 0x40000E00) R_TZF Structure __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ } TZFPT_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[94]; - - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; -} R_TZF_Type; /*!< Size = 388 (0x184) */ +} R_TZF_Type; /*!< Size = 6 (0x6) */ /* =========================================================================================================================== */ /* ================ R_CPSCU ================ */ @@ -13200,21 +13326,22 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure struct { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 3; - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ } ICUSARE_b; }; @@ -13228,7 +13355,8 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 4; + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ @@ -13239,7 +13367,21 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 17; } ICUSARF_b; }; - __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + uint32_t : 28; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; union { @@ -13293,7 +13435,30 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } BUSSARB_b; }; - __IM uint32_t RESERVED5[10]; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; union { @@ -13318,7 +13483,33 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } MMPUSARB_b; }; - __IM uint32_t RESERVED6[26]; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; union { @@ -13331,7 +13522,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 24; } DMACCHSAR_b; }; - __IM uint32_t RESERVED7[3]; + __IM uint32_t RESERVED9[3]; union { @@ -13343,7 +13534,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[147]; + __IM uint32_t RESERVED10[147]; union { @@ -13372,7 +13563,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 11; } SRAMSABAR1_b; }; - __IM uint32_t RESERVED9[126]; + __IM uint32_t RESERVED11[126]; union { @@ -13855,6 +14046,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -13919,9 +14113,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -14892,12 +15083,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ + #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ + #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ + #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ @@ -14945,6 +15142,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ + #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ @@ -14992,6 +15191,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ + #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ /* ========================================================= PSARE ========================================================= */ #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ @@ -15032,6 +15233,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ + #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ /* ======================================================= CFSAMONA ======================================================== */ #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ @@ -15070,6 +15273,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -15654,6 +15860,11 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -15769,30 +15980,49 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -15979,19 +16209,27 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -16657,10 +16895,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -16697,166 +16931,179 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -17278,20 +17525,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -18773,32 +19010,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ @@ -19516,9 +19731,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CPSCU ================ */ @@ -19568,6 +19780,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ @@ -19591,6 +19805,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ @@ -19614,18 +19830,39 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== ICUSARI ======================================================== */ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARA ======================================================== */ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARB ======================================================== */ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ /* ======================================================= MMPUSARA ======================================================== */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ /* ======================================================= DMACCHSAR ======================================================= */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h index 9c26ec03c..c597f5f58 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h @@ -468,24 +468,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -702,27 +719,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; - - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1357,7 +1360,7 @@ typedef struct struct { __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry enable */ __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ } ID_b; @@ -1414,7 +1417,7 @@ typedef struct struct { __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ } ID_b; @@ -1639,7 +1642,7 @@ typedef struct } R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) */ typedef struct { @@ -3660,15 +3663,16 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - uint32_t : 1; + __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; + __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ @@ -3707,7 +3711,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ uint32_t : 1; __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; + __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ + uint32_t : 3; __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ uint32_t : 3; __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ @@ -3748,7 +3753,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - uint32_t : 3; + __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ + uint32_t : 2; } PSARD_b; }; @@ -3788,7 +3794,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ + uint32_t : 27; } MSSAR_b; }; @@ -3953,9 +3960,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3963,16 +3983,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -5054,7 +5074,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -5070,7 +5106,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -5368,11 +5404,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -5384,7 +5431,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -5407,15 +5454,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -5430,7 +5496,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -5913,17 +6016,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -7323,47 +7430,43 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -7416,7 +7519,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -7579,7 +7683,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -8469,7 +8593,9 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ uint32_t : 3; __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; } BST_b; }; @@ -8490,7 +8616,9 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ uint32_t : 3; __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; } BSTE_b; }; @@ -8511,28 +8639,32 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ uint32_t : 3; __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; } BIE_b; }; union { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ struct { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 11; + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; } BSTFC_b; }; @@ -8815,7 +8947,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT0_b; @@ -8832,7 +8965,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT1_b; @@ -8849,7 +8983,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT2_b; @@ -8866,7 +9001,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT3_b; @@ -8884,7 +9020,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } SVDCT_b; @@ -9034,7 +9171,20 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28[2]; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; union { @@ -9160,9 +9310,7 @@ typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -9897,14 +10045,16 @@ typedef struct /*!< (@ 0x40083000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -12723,23 +12873,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -14920,20 +15085,7 @@ typedef struct /*!< (@ 0x40000E00) R_TZF Structure __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ } TZFPT_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[94]; - - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; -} R_TZF_Type; /*!< Size = 388 (0x184) */ +} R_TZF_Type; /*!< Size = 6 (0x6) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -15161,21 +15313,22 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure struct { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 3; - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ } ICUSARE_b; }; @@ -15189,7 +15342,8 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 4; + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ @@ -15200,7 +15354,21 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 17; } ICUSARF_b; }; - __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + uint32_t : 28; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; union { @@ -15254,7 +15422,30 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } BUSSARB_b; }; - __IM uint32_t RESERVED5[10]; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; union { @@ -15279,7 +15470,33 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } MMPUSARB_b; }; - __IM uint32_t RESERVED6[26]; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; union { @@ -15292,7 +15509,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 24; } DMACCHSAR_b; }; - __IM uint32_t RESERVED7[3]; + __IM uint32_t RESERVED9[3]; union { @@ -15304,7 +15521,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[147]; + __IM uint32_t RESERVED10[147]; union { @@ -15333,7 +15550,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 11; } SRAMSABAR1_b; }; - __IM uint32_t RESERVED9[126]; + __IM uint32_t RESERVED11[126]; union { @@ -16187,6 +16404,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -16251,9 +16471,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -16598,6 +16815,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ @@ -16629,6 +16848,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ @@ -17548,12 +17769,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ + #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ + #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ + #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ @@ -17601,6 +17828,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ + #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ @@ -17648,6 +17877,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ + #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ /* ========================================================= PSARE ========================================================= */ #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ @@ -17688,6 +17919,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ + #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ /* ======================================================= CFSAMONA ======================================================== */ #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ @@ -17726,6 +17959,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -18207,6 +18443,11 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -18322,30 +18563,49 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -18532,19 +18792,27 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -19250,10 +19518,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -19290,166 +19554,179 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -19900,6 +20177,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ /* ========================================================= BSTE ========================================================== */ #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ @@ -19915,6 +20194,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ /* ========================================================== BIE ========================================================== */ #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ @@ -19930,6 +20211,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ /* ========================================================= BSTFC ========================================================= */ #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ @@ -19945,6 +20228,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ /* ========================================================= NTST ========================================================== */ #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ @@ -20147,6 +20432,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT1 ========================================================= */ @@ -20158,6 +20447,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT2 ========================================================= */ @@ -20169,6 +20462,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT3 ========================================================= */ @@ -20180,6 +20477,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ @@ -20193,6 +20494,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================= SDCTPIDL ======================================================== */ @@ -20254,6 +20559,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ /* ======================================================== BITCNT ========================================================= */ #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ @@ -20420,20 +20732,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -22032,32 +22334,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ @@ -22799,9 +23079,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -22882,6 +23159,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ @@ -22905,6 +23184,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ @@ -22928,18 +23209,39 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== ICUSARI ======================================================== */ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARA ======================================================== */ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARB ======================================================== */ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ /* ======================================================= MMPUSARA ======================================================== */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ /* ======================================================= DMACCHSAR ======================================================= */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h index b6ce55b32..5ced06ec5 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h @@ -465,24 +465,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -699,27 +716,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -3400,9 +3403,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3410,16 +3426,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -4646,7 +4662,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -4662,7 +4694,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -4960,11 +4992,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -4976,7 +5019,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -4999,15 +5042,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -5022,7 +5084,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -5653,17 +5752,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -7063,47 +7166,43 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -7156,7 +7255,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -7319,7 +7419,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -8670,14 +8790,16 @@ typedef struct /*!< (@ 0x40044000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -11572,23 +11694,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -14134,6 +14271,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -14198,9 +14338,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -15278,6 +15415,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -15989,6 +16129,11 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -16104,30 +16249,49 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -16363,19 +16527,27 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -17081,10 +17253,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -17121,166 +17289,179 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -17695,20 +17876,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -19347,32 +19518,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h index 77d826a6f..f1ae62e6c 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h @@ -468,24 +468,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -702,27 +719,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1184,7 +1187,7 @@ typedef struct } R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) */ typedef struct { @@ -3205,15 +3208,16 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - uint32_t : 1; + __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; + __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ @@ -3252,7 +3256,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ uint32_t : 1; __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; + __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ + uint32_t : 3; __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ uint32_t : 3; __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ @@ -3293,7 +3298,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - uint32_t : 3; + __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ + uint32_t : 2; } PSARD_b; }; @@ -3333,7 +3339,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ + uint32_t : 27; } MSSAR_b; }; @@ -3498,9 +3505,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3508,16 +3528,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -4684,7 +4704,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -4700,7 +4736,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -4998,11 +5034,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -5014,7 +5061,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -5037,15 +5084,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -5060,7 +5126,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -5543,17 +5646,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -6953,47 +7060,43 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -7046,7 +7149,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -7209,7 +7313,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -7653,9 +7777,7 @@ typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -8594,14 +8716,16 @@ typedef struct /*!< (@ 0x40083000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -11908,23 +12032,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -14053,20 +14192,7 @@ typedef struct /*!< (@ 0x40000E00) R_TZF Structure __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ } TZFPT_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[94]; - - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; -} R_TZF_Type; /*!< Size = 388 (0x184) */ +} R_TZF_Type; /*!< Size = 6 (0x6) */ /* =========================================================================================================================== */ /* ================ R_CPSCU ================ */ @@ -14191,21 +14317,22 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure struct { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 3; - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ } ICUSARE_b; }; @@ -14219,7 +14346,8 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 4; + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ @@ -14230,7 +14358,21 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 17; } ICUSARF_b; }; - __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + uint32_t : 28; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; union { @@ -14284,7 +14426,30 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } BUSSARB_b; }; - __IM uint32_t RESERVED5[10]; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; union { @@ -14309,7 +14474,33 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } MMPUSARB_b; }; - __IM uint32_t RESERVED6[26]; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; union { @@ -14322,7 +14513,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 24; } DMACCHSAR_b; }; - __IM uint32_t RESERVED7[3]; + __IM uint32_t RESERVED9[3]; union { @@ -14334,7 +14525,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[147]; + __IM uint32_t RESERVED10[147]; union { @@ -14363,7 +14554,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 11; } SRAMSABAR1_b; }; - __IM uint32_t RESERVED9[126]; + __IM uint32_t RESERVED11[126]; union { @@ -14860,6 +15051,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -14924,9 +15118,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -15897,12 +16088,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ + #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ + #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ + #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ @@ -15950,6 +16147,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ + #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ @@ -15997,6 +16196,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ + #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ /* ========================================================= PSARE ========================================================= */ #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ @@ -16037,6 +16238,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ + #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ /* ======================================================= CFSAMONA ======================================================== */ #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ @@ -16075,6 +16278,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -16763,6 +16969,11 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -16878,30 +17089,49 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -17088,19 +17318,27 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -17806,10 +18044,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -17846,166 +18080,179 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -18427,20 +18674,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -20276,32 +20513,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ @@ -21025,9 +21240,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CPSCU ================ */ @@ -21077,6 +21289,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ @@ -21100,6 +21314,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ @@ -21123,18 +21339,39 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== ICUSARI ======================================================== */ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARA ======================================================== */ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARB ======================================================== */ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ /* ======================================================= MMPUSARA ======================================================== */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ /* ======================================================= DMACCHSAR ======================================================= */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h index 44e7d7219..778be37a1 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h @@ -468,24 +468,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -702,27 +719,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1184,7 +1187,7 @@ typedef struct } R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) */ typedef struct { @@ -3205,15 +3208,16 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - uint32_t : 1; + __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; + __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ @@ -3252,7 +3256,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ uint32_t : 1; __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; + __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ + uint32_t : 3; __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ uint32_t : 3; __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ @@ -3293,7 +3298,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - uint32_t : 3; + __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ + uint32_t : 2; } PSARD_b; }; @@ -3333,7 +3339,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ + uint32_t : 27; } MSSAR_b; }; @@ -3498,9 +3505,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3508,16 +3528,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -4684,7 +4704,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -4700,7 +4736,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -4998,11 +5034,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -5014,7 +5061,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -5037,15 +5084,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -5060,7 +5126,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -5543,17 +5646,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -6953,47 +7060,43 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -7046,7 +7149,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -7209,7 +7313,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -7653,9 +7777,7 @@ typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -8594,14 +8716,16 @@ typedef struct /*!< (@ 0x40083000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -11908,23 +12032,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -14053,20 +14192,7 @@ typedef struct /*!< (@ 0x40000E00) R_TZF Structure __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ } TZFPT_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[94]; - - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; -} R_TZF_Type; /*!< Size = 388 (0x184) */ +} R_TZF_Type; /*!< Size = 6 (0x6) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -14294,21 +14420,22 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure struct { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 3; - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ } ICUSARE_b; }; @@ -14322,7 +14449,8 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 4; + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ @@ -14333,7 +14461,21 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 17; } ICUSARF_b; }; - __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + uint32_t : 28; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; union { @@ -14387,7 +14529,30 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } BUSSARB_b; }; - __IM uint32_t RESERVED5[10]; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; union { @@ -14412,7 +14577,33 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } MMPUSARB_b; }; - __IM uint32_t RESERVED6[26]; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; union { @@ -14425,7 +14616,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 24; } DMACCHSAR_b; }; - __IM uint32_t RESERVED7[3]; + __IM uint32_t RESERVED9[3]; union { @@ -14437,7 +14628,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[147]; + __IM uint32_t RESERVED10[147]; union { @@ -14466,7 +14657,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 11; } SRAMSABAR1_b; }; - __IM uint32_t RESERVED9[126]; + __IM uint32_t RESERVED11[126]; union { @@ -14965,6 +15156,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -15029,9 +15223,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -16002,12 +16193,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ + #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ + #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ + #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ @@ -16055,6 +16252,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ + #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ @@ -16102,6 +16301,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ + #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ /* ========================================================= PSARE ========================================================= */ #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ @@ -16142,6 +16343,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ + #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ /* ======================================================= CFSAMONA ======================================================== */ #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ @@ -16180,6 +16383,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -16868,6 +17074,11 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -16983,30 +17194,49 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -17193,19 +17423,27 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -17911,10 +18149,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -17951,166 +18185,179 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -18532,20 +18779,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -20381,32 +20618,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ @@ -21130,9 +21345,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -21213,6 +21425,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ @@ -21236,6 +21450,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ @@ -21259,18 +21475,39 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== ICUSARI ======================================================== */ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARA ======================================================== */ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARB ======================================================== */ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ /* ======================================================= MMPUSARA ======================================================== */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ /* ======================================================= DMACCHSAR ======================================================= */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4T1BB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4T1BB.h index d15a01305..e08d0cf60 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4T1BB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4T1BB.h @@ -468,24 +468,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -702,27 +719,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; - - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1357,7 +1360,7 @@ typedef struct struct { __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry enable */ __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ } ID_b; @@ -1414,7 +1417,7 @@ typedef struct struct { __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ } ID_b; @@ -1639,7 +1642,7 @@ typedef struct } R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) */ typedef struct { @@ -3565,15 +3568,16 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - uint32_t : 1; + __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; + __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ @@ -3612,7 +3616,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ uint32_t : 1; __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; + __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ + uint32_t : 3; __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ uint32_t : 3; __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ @@ -3653,7 +3658,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - uint32_t : 3; + __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ + uint32_t : 2; } PSARD_b; }; @@ -3693,7 +3699,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ + uint32_t : 27; } MSSAR_b; }; @@ -3858,9 +3865,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3868,16 +3888,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -4959,7 +4979,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -4975,7 +5011,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -5273,11 +5309,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -5289,7 +5336,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -5312,15 +5359,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -5335,7 +5401,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -5818,17 +5921,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -7228,47 +7335,43 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -7321,7 +7424,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -7484,7 +7588,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -8374,7 +8498,9 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ uint32_t : 3; __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; } BST_b; }; @@ -8395,7 +8521,9 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ uint32_t : 3; __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; } BSTE_b; }; @@ -8416,28 +8544,32 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ uint32_t : 3; __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; } BIE_b; }; union { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ struct { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 11; + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; } BSTFC_b; }; @@ -8720,7 +8852,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT0_b; @@ -8737,7 +8870,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT1_b; @@ -8754,7 +8888,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT2_b; @@ -8771,7 +8906,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT3_b; @@ -8789,7 +8925,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } SVDCT_b; @@ -8939,7 +9076,20 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28[2]; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; union { @@ -9065,9 +9215,7 @@ typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -11967,23 +12115,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -13095,20 +13258,7 @@ typedef struct /*!< (@ 0x40000E00) R_TZF Structure __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ } TZFPT_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[94]; - - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; -} R_TZF_Type; /*!< Size = 388 (0x184) */ +} R_TZF_Type; /*!< Size = 6 (0x6) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -13336,21 +13486,22 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure struct { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 3; - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ } ICUSARE_b; }; @@ -13364,7 +13515,8 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 4; + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ @@ -13375,7 +13527,21 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 17; } ICUSARF_b; }; - __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + uint32_t : 28; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; union { @@ -13429,7 +13595,30 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } BUSSARB_b; }; - __IM uint32_t RESERVED5[10]; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; union { @@ -13454,7 +13643,33 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } MMPUSARB_b; }; - __IM uint32_t RESERVED6[26]; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; union { @@ -13467,7 +13682,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 24; } DMACCHSAR_b; }; - __IM uint32_t RESERVED7[3]; + __IM uint32_t RESERVED9[3]; union { @@ -13479,7 +13694,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[147]; + __IM uint32_t RESERVED10[147]; union { @@ -13508,7 +13723,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 11; } SRAMSABAR1_b; }; - __IM uint32_t RESERVED9[126]; + __IM uint32_t RESERVED11[126]; union { @@ -14082,6 +14297,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -14146,9 +14364,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -14493,6 +14708,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ @@ -14524,6 +14741,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ @@ -15412,12 +15631,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ + #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ + #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ + #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ @@ -15465,6 +15690,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ + #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ @@ -15512,6 +15739,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ + #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ /* ========================================================= PSARE ========================================================= */ #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ @@ -15552,6 +15781,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ + #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ /* ======================================================= CFSAMONA ======================================================== */ #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ @@ -15590,6 +15821,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -16071,6 +16305,11 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -16186,30 +16425,49 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -16396,19 +16654,27 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -17114,10 +17380,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -17154,166 +17416,179 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -17764,6 +18039,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ /* ========================================================= BSTE ========================================================== */ #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ @@ -17779,6 +18056,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ /* ========================================================== BIE ========================================================== */ #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ @@ -17794,6 +18073,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ /* ========================================================= BSTFC ========================================================= */ #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ @@ -17809,6 +18090,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ /* ========================================================= NTST ========================================================== */ #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ @@ -18011,6 +18294,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT1 ========================================================= */ @@ -18022,6 +18309,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT2 ========================================================= */ @@ -18033,6 +18324,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT3 ========================================================= */ @@ -18044,6 +18339,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ @@ -18057,6 +18356,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================= SDCTPIDL ======================================================== */ @@ -18118,6 +18421,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ /* ======================================================== BITCNT ========================================================= */ #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ @@ -19606,32 +19916,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ @@ -19820,9 +20108,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -19903,6 +20188,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ @@ -19926,6 +20213,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ @@ -19949,18 +20238,39 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== ICUSARI ======================================================== */ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARA ======================================================== */ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARB ======================================================== */ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ /* ======================================================= MMPUSARA ======================================================== */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ /* ======================================================= DMACCHSAR ======================================================= */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h index 43be52d19..6c48ef516 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h @@ -465,24 +465,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -699,27 +716,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -3400,9 +3403,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3410,16 +3426,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -4646,7 +4662,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -4662,7 +4694,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -4960,11 +4992,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -4976,7 +5019,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -4999,15 +5042,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -5022,7 +5084,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -5653,17 +5752,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -7063,47 +7166,43 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -7156,7 +7255,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -7319,7 +7419,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -8708,14 +8828,16 @@ typedef struct /*!< (@ 0x40044000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -11408,23 +11530,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -13968,6 +14105,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -14032,9 +14172,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -15112,6 +15249,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -15823,6 +15963,11 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -15938,30 +16083,49 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -16197,19 +16361,27 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -16915,10 +17087,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -16955,166 +17123,179 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -17544,20 +17725,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -19079,32 +19250,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h index a7626d921..92c09d331 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h @@ -468,24 +468,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -702,27 +719,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1184,7 +1187,7 @@ typedef struct } R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) */ typedef struct { @@ -3205,15 +3208,16 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - uint32_t : 1; + __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; + __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ @@ -3252,7 +3256,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ uint32_t : 1; __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; + __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ + uint32_t : 3; __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ uint32_t : 3; __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ @@ -3293,7 +3298,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - uint32_t : 3; + __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ + uint32_t : 2; } PSARD_b; }; @@ -3333,7 +3339,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ + uint32_t : 27; } MSSAR_b; }; @@ -3498,9 +3505,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3508,16 +3528,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -4441,7 +4461,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -4457,7 +4493,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -4755,11 +4791,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -4771,7 +4818,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -4794,15 +4841,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -4817,7 +4883,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -6028,17 +6131,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -7382,47 +7489,43 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -7475,7 +7578,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -7638,7 +7742,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -8082,9 +8206,7 @@ typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -9023,14 +9145,16 @@ typedef struct /*!< (@ 0x40083000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -12337,23 +12461,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -14436,20 +14575,7 @@ typedef struct /*!< (@ 0x40000E00) R_TZF Structure __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ } TZFPT_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[94]; - - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; -} R_TZF_Type; /*!< Size = 388 (0x184) */ +} R_TZF_Type; /*!< Size = 6 (0x6) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -14677,21 +14803,22 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure struct { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 3; - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ } ICUSARE_b; }; @@ -14705,7 +14832,8 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 4; + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ @@ -14716,7 +14844,21 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 17; } ICUSARF_b; }; - __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + uint32_t : 28; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; union { @@ -14770,7 +14912,30 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } BUSSARB_b; }; - __IM uint32_t RESERVED5[10]; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; union { @@ -14795,7 +14960,33 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } MMPUSARB_b; }; - __IM uint32_t RESERVED6[26]; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; union { @@ -14808,7 +14999,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 24; } DMACCHSAR_b; }; - __IM uint32_t RESERVED7[3]; + __IM uint32_t RESERVED9[3]; union { @@ -14820,7 +15011,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[147]; + __IM uint32_t RESERVED10[147]; union { @@ -14849,7 +15040,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 11; } SRAMSABAR1_b; }; - __IM uint32_t RESERVED9[126]; + __IM uint32_t RESERVED11[126]; union { @@ -15344,6 +15535,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -15408,9 +15602,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -16381,12 +16572,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ + #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ + #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ + #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ @@ -16434,6 +16631,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ + #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ @@ -16481,6 +16680,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ + #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ /* ========================================================= PSARE ========================================================= */ #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ @@ -16521,6 +16722,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ + #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ /* ======================================================= CFSAMONA ======================================================== */ #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ @@ -16559,6 +16762,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -17143,6 +17349,11 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -17258,30 +17469,49 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -17762,19 +17992,27 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -18440,10 +18678,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -18480,166 +18714,179 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -19061,20 +19308,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -20910,32 +21147,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ @@ -21641,9 +21856,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -21724,6 +21936,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ @@ -21747,6 +21961,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ @@ -21770,18 +21986,39 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== ICUSARI ======================================================== */ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARA ======================================================== */ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARB ======================================================== */ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ /* ======================================================= MMPUSARA ======================================================== */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ /* ======================================================= DMACCHSAR ======================================================= */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h index b67840528..08053ff9e 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h @@ -468,24 +468,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -702,27 +719,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; - - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1357,7 +1360,7 @@ typedef struct struct { __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry enable */ __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ } ID_b; @@ -1414,7 +1417,7 @@ typedef struct struct { __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ } ID_b; @@ -1639,7 +1642,7 @@ typedef struct } R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) */ typedef struct { @@ -3660,15 +3663,16 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - uint32_t : 1; + __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; + __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ @@ -3707,7 +3711,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ uint32_t : 1; __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; + __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ + uint32_t : 3; __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ uint32_t : 3; __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ @@ -3748,7 +3753,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - uint32_t : 3; + __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ + uint32_t : 2; } PSARD_b; }; @@ -3788,7 +3794,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ + uint32_t : 27; } MSSAR_b; }; @@ -3953,9 +3960,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3963,16 +3983,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -5054,7 +5074,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -5070,7 +5106,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -5368,11 +5404,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -5384,7 +5431,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -5407,15 +5454,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -5430,7 +5496,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -5913,17 +6016,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -7323,47 +7430,43 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -7416,7 +7519,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -7579,7 +7683,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -8469,7 +8593,9 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ uint32_t : 3; __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; } BST_b; }; @@ -8490,7 +8616,9 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ uint32_t : 3; __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; } BSTE_b; }; @@ -8511,28 +8639,32 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ uint32_t : 3; __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; } BIE_b; }; union { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ struct { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 11; + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; } BSTFC_b; }; @@ -8815,7 +8947,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT0_b; @@ -8832,7 +8965,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT1_b; @@ -8849,7 +8983,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT2_b; @@ -8866,7 +9001,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT3_b; @@ -8884,7 +9020,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } SVDCT_b; @@ -9034,7 +9171,20 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28[2]; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; union { @@ -9160,9 +9310,7 @@ typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -10101,14 +10249,16 @@ typedef struct /*!< (@ 0x40083000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -12927,23 +13077,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -15124,20 +15289,7 @@ typedef struct /*!< (@ 0x40000E00) R_TZF Structure __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ } TZFPT_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[94]; - - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; -} R_TZF_Type; /*!< Size = 388 (0x184) */ +} R_TZF_Type; /*!< Size = 6 (0x6) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -15365,21 +15517,22 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure struct { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 3; - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ } ICUSARE_b; }; @@ -15393,7 +15546,8 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 4; + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ @@ -15404,7 +15558,21 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 17; } ICUSARF_b; }; - __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + uint32_t : 28; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; union { @@ -15458,7 +15626,30 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } BUSSARB_b; }; - __IM uint32_t RESERVED5[10]; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; union { @@ -15483,7 +15674,33 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } MMPUSARB_b; }; - __IM uint32_t RESERVED6[26]; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; union { @@ -15496,7 +15713,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 24; } DMACCHSAR_b; }; - __IM uint32_t RESERVED7[3]; + __IM uint32_t RESERVED9[3]; union { @@ -15508,7 +15725,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[147]; + __IM uint32_t RESERVED10[147]; union { @@ -15537,7 +15754,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 11; } SRAMSABAR1_b; }; - __IM uint32_t RESERVED9[126]; + __IM uint32_t RESERVED11[126]; union { @@ -16393,6 +16610,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -16457,9 +16677,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -16804,6 +17021,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ @@ -16835,6 +17054,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ @@ -17754,12 +17975,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ + #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ + #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ + #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ @@ -17807,6 +18034,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ + #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ @@ -17854,6 +18083,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ + #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ /* ========================================================= PSARE ========================================================= */ #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ @@ -17894,6 +18125,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ + #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ /* ======================================================= CFSAMONA ======================================================== */ #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ @@ -17932,6 +18165,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -18413,6 +18649,11 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -18528,30 +18769,49 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -18738,19 +18998,27 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -19456,10 +19724,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -19496,166 +19760,179 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -20106,6 +20383,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ /* ========================================================= BSTE ========================================================== */ #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ @@ -20121,6 +20400,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ /* ========================================================== BIE ========================================================== */ #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ @@ -20136,6 +20417,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ /* ========================================================= BSTFC ========================================================= */ #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ @@ -20151,6 +20434,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ /* ========================================================= NTST ========================================================== */ #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ @@ -20353,6 +20638,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT1 ========================================================= */ @@ -20364,6 +20653,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT2 ========================================================= */ @@ -20375,6 +20668,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT3 ========================================================= */ @@ -20386,6 +20683,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ @@ -20399,6 +20700,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================= SDCTPIDL ======================================================== */ @@ -20460,6 +20765,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ /* ======================================================== BITCNT ========================================================= */ #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ @@ -20708,20 +21020,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -22320,32 +22622,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ @@ -23087,9 +23367,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -23170,6 +23447,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ @@ -23193,6 +23472,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ @@ -23216,18 +23497,39 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== ICUSARI ======================================================== */ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARA ======================================================== */ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARB ======================================================== */ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ /* ======================================================= MMPUSARA ======================================================== */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ /* ======================================================= DMACCHSAR ======================================================= */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h index 6ec52b94a..a863332a3 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h @@ -465,24 +465,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -699,27 +716,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1116,8 +1119,8 @@ typedef struct struct { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 9; } A_b; }; @@ -1127,8 +1130,8 @@ typedef struct struct { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnB Output Rising Edge Delay Setting */ + uint16_t : 9; } B_b; }; } R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ @@ -3414,9 +3417,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3424,16 +3440,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -4600,7 +4616,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -4616,7 +4648,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -4914,11 +4946,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -4930,7 +4973,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -4953,15 +4996,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -4976,7 +5038,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -5459,17 +5558,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -6824,8 +6927,8 @@ typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ uint16_t : 6; - __IOM uint16_t FRANGE : 1; /*!< [8..8] GPT core clock Frequency Range */ - uint16_t : 7; + __IOM uint16_t FRANGE : 2; /*!< [9..8] GPT core clock Frequency Range */ + uint16_t : 6; } GTDLYCR1_b; }; @@ -6917,47 +7020,43 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -7010,7 +7109,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -7173,7 +7273,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -8671,14 +8791,16 @@ typedef struct /*!< (@ 0x40044000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -12104,23 +12226,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -15679,6 +15816,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -15743,9 +15883,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -15882,10 +16019,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================== A =========================================================== */ #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ - #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ /* =========================================================== B =========================================================== */ #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ - #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ /* =========================================================================================================================== */ /* ================ SAR ================ */ @@ -16802,6 +16939,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -17490,6 +17630,11 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -17605,30 +17750,49 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -17815,19 +17979,27 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -18488,7 +18660,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= GTDLYCR1 ======================================================== */ #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */ - #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x100UL) /*!< FRANGE (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x300UL) /*!< FRANGE (Bitfield-Mask: 0x03) */ #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ @@ -18552,10 +18724,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -18592,166 +18760,179 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -19245,20 +19426,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -21160,32 +21331,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h index 5ed9d54de..ba558caba 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h @@ -465,24 +465,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -699,27 +716,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1116,8 +1119,8 @@ typedef struct struct { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 9; } A_b; }; @@ -1127,8 +1130,8 @@ typedef struct struct { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnB Output Rising Edge Delay Setting */ + uint16_t : 9; } B_b; }; } R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ @@ -3414,9 +3417,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3424,16 +3440,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -4600,7 +4616,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -4616,7 +4648,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -4914,11 +4946,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -4930,7 +4973,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -4953,15 +4996,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -4976,7 +5038,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -6187,17 +6286,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -7552,8 +7655,8 @@ typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ uint16_t : 6; - __IOM uint16_t FRANGE : 1; /*!< [8..8] GPT core clock Frequency Range */ - uint16_t : 7; + __IOM uint16_t FRANGE : 2; /*!< [9..8] GPT core clock Frequency Range */ + uint16_t : 6; } GTDLYCR1_b; }; @@ -7645,47 +7748,43 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -7738,7 +7837,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -7901,7 +8001,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -8875,7 +8995,9 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ uint32_t : 3; __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; } BST_b; }; @@ -8896,7 +9018,9 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ uint32_t : 3; __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; } BSTE_b; }; @@ -8917,28 +9041,32 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ uint32_t : 3; __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; } BIE_b; }; union { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ struct { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 11; + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; } BSTFC_b; }; @@ -9221,7 +9349,8 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT0_b; @@ -9238,7 +9367,8 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT1_b; @@ -9255,7 +9385,8 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT2_b; @@ -9272,7 +9403,8 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT3_b; @@ -9290,7 +9422,8 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } SVDCT_b; @@ -9440,7 +9573,20 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28[2]; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; union { @@ -10652,14 +10798,16 @@ typedef struct /*!< (@ 0x40044000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -14085,23 +14233,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -17670,6 +17833,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -17734,9 +17900,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -17873,10 +18036,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================== A =========================================================== */ #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ - #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ /* =========================================================== B =========================================================== */ #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ - #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ /* =========================================================================================================================== */ /* ================ SAR ================ */ @@ -18793,6 +18956,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -19481,6 +19647,11 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -19596,30 +19767,49 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -20100,19 +20290,27 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -20773,7 +20971,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= GTDLYCR1 ======================================================== */ #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */ - #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x100UL) /*!< FRANGE (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x300UL) /*!< FRANGE (Bitfield-Mask: 0x03) */ #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ @@ -20837,10 +21035,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -20877,166 +21071,179 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -21543,6 +21750,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ /* ========================================================= BSTE ========================================================== */ #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ @@ -21558,6 +21767,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ /* ========================================================== BIE ========================================================== */ #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ @@ -21573,6 +21784,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ /* ========================================================= BSTFC ========================================================= */ #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ @@ -21588,6 +21801,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ /* ========================================================= NTST ========================================================== */ #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ @@ -21790,6 +22005,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT1 ========================================================= */ @@ -21801,6 +22020,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT2 ========================================================= */ @@ -21812,6 +22035,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT3 ========================================================= */ @@ -21823,6 +22050,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ @@ -21836,6 +22067,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================= SDCTPIDL ======================================================== */ @@ -21897,6 +22132,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ /* ======================================================== BITCNT ========================================================= */ #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ @@ -22229,20 +22471,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -24144,32 +24376,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h index 64dfd50e9..11ed480ce 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h @@ -465,24 +465,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -699,27 +716,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -2026,8 +2029,8 @@ typedef struct struct { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 9; } A_b; }; @@ -2037,8 +2040,8 @@ typedef struct struct { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnB Output Rising Edge Delay Setting */ + uint16_t : 9; } B_b; }; } R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ @@ -4324,9 +4327,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -4334,16 +4350,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -5510,7 +5526,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -5526,7 +5558,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -6479,7 +6511,20 @@ typedef struct /*!< (@ 0x400E4000) R_DRW Structure uint32_t : 8; } COLKEY_b; }; -} R_DRW_Type; /*!< Size = 236 (0xec) */ + __IM uint32_t RESERVED6[5]; + + union + { + __IOM uint32_t DBWER; /*!< (@ 0x00000100) DRW Bufferable Write Enable Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t BWE : 1; /*!< [2..2] Bufferable Write Enable */ + uint32_t : 29; + } DBWER_b; + }; +} R_DRW_Type; /*!< Size = 260 (0x104) */ /* =========================================================================================================================== */ /* ================ R_DTC ================ */ @@ -6511,11 +6556,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -6527,7 +6583,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -6550,15 +6606,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -6573,7 +6648,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -9384,17 +9496,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GLCDC ================ */ @@ -10825,8 +10941,8 @@ typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ uint16_t : 6; - __IOM uint16_t FRANGE : 1; /*!< [8..8] GPT core clock Frequency Range */ - uint16_t : 7; + __IOM uint16_t FRANGE : 2; /*!< [9..8] GPT core clock Frequency Range */ + uint16_t : 6; } GTDLYCR1_b; }; @@ -10918,47 +11034,43 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -11011,7 +11123,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -11174,7 +11287,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -13310,14 +13443,16 @@ typedef struct /*!< (@ 0x40044000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -16743,23 +16878,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -20340,6 +20490,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -20404,9 +20557,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -20897,10 +21047,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================== A =========================================================== */ #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ - #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ /* =========================================================== B =========================================================== */ #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ - #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ /* =========================================================================================================================== */ /* ================ SAR ================ */ @@ -21817,6 +21967,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -22505,6 +22658,11 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -22948,36 +23106,58 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ====================================================== PERFCOUNT2 ======================================================= */ #define R_DRW_PERFCOUNT2_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ #define R_DRW_PERFCOUNT2_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DBWER ========================================================= */ + #define R_DRW_DBWER_BWE_Pos (2UL) /*!< BWE (Bit 2) */ + #define R_DRW_DBWER_BWE_Msk (0x4UL) /*!< BWE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DTC ================ */ /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -24143,19 +24323,27 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GLCDC ================ */ @@ -24857,7 +25045,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= GTDLYCR1 ======================================================== */ #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */ - #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x100UL) /*!< FRANGE (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x300UL) /*!< FRANGE (Bitfield-Mask: 0x03) */ #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ @@ -24921,10 +25109,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -24961,166 +25145,179 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -25864,20 +26061,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -27779,32 +27966,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h index c6671c322..c2962cb37 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h @@ -468,24 +468,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -702,27 +719,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1184,7 +1187,7 @@ typedef struct } R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) */ typedef struct { @@ -3240,15 +3243,16 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - uint32_t : 1; + __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; + __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ @@ -3287,7 +3291,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ uint32_t : 1; __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; + __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ + uint32_t : 3; __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ uint32_t : 3; __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ @@ -3328,7 +3333,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - uint32_t : 3; + __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ + uint32_t : 2; } PSARD_b; }; @@ -3368,7 +3374,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ + uint32_t : 27; } MSSAR_b; }; @@ -3533,9 +3540,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3543,16 +3563,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -4719,7 +4739,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -4735,7 +4771,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -5033,11 +5069,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -5049,7 +5096,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -5072,15 +5119,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -5095,7 +5161,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -6306,17 +6409,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -7716,47 +7823,43 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -7809,7 +7912,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -7972,7 +8076,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -8416,9 +8540,7 @@ typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -9357,14 +9479,16 @@ typedef struct /*!< (@ 0x40083000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -12671,23 +12795,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -14816,20 +14955,7 @@ typedef struct /*!< (@ 0x40000E00) R_TZF Structure __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ } TZFPT_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[94]; - - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; -} R_TZF_Type; /*!< Size = 388 (0x184) */ +} R_TZF_Type; /*!< Size = 6 (0x6) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -15057,21 +15183,22 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure struct { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 3; - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ } ICUSARE_b; }; @@ -15085,7 +15212,8 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 4; + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ @@ -15096,7 +15224,21 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 17; } ICUSARF_b; }; - __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + uint32_t : 28; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; union { @@ -15150,7 +15292,30 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } BUSSARB_b; }; - __IM uint32_t RESERVED5[10]; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; union { @@ -15175,7 +15340,33 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } MMPUSARB_b; }; - __IM uint32_t RESERVED6[26]; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; union { @@ -15188,7 +15379,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 24; } DMACCHSAR_b; }; - __IM uint32_t RESERVED7[3]; + __IM uint32_t RESERVED9[3]; union { @@ -15200,7 +15391,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[147]; + __IM uint32_t RESERVED10[147]; union { @@ -15229,7 +15420,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 11; } SRAMSABAR1_b; }; - __IM uint32_t RESERVED9[126]; + __IM uint32_t RESERVED11[126]; union { @@ -17048,6 +17239,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -17112,9 +17306,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -18098,12 +18289,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ + #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ + #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ + #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ @@ -18151,6 +18348,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ + #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ @@ -18198,6 +18397,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ + #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ /* ========================================================= PSARE ========================================================= */ #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ @@ -18238,6 +18439,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ + #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ /* ======================================================= CFSAMONA ======================================================== */ #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ @@ -18276,6 +18479,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -18964,6 +19170,11 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -19079,30 +19290,49 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -19583,19 +19813,27 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -20301,10 +20539,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -20341,166 +20575,179 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -20922,20 +21169,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -22771,32 +23008,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ @@ -23520,9 +23735,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -23603,6 +23815,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ @@ -23626,6 +23840,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ @@ -23649,18 +23865,39 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== ICUSARI ======================================================== */ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARA ======================================================== */ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARB ======================================================== */ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ /* ======================================================= MMPUSARA ======================================================== */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ /* ======================================================= DMACCHSAR ======================================================= */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h index 0658d04c0..b9a6bdccc 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h @@ -468,24 +468,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -702,27 +719,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; - - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1669,7 +1672,7 @@ typedef struct } R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) */ typedef struct { @@ -3725,15 +3728,16 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - uint32_t : 1; + __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; + __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ @@ -3772,7 +3776,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ uint32_t : 1; __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; + __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ + uint32_t : 3; __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ uint32_t : 3; __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ @@ -3813,7 +3818,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - uint32_t : 3; + __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ + uint32_t : 2; } PSARD_b; }; @@ -3853,7 +3859,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ + uint32_t : 27; } MSSAR_b; }; @@ -4018,9 +4025,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -4028,16 +4048,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -5844,7 +5864,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -5860,7 +5896,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -6158,11 +6194,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -6174,7 +6221,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -6197,15 +6244,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -6220,7 +6286,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -7431,17 +7534,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -8841,47 +8948,43 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -8934,7 +9037,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -9097,7 +9201,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -9987,7 +10111,9 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ uint32_t : 3; __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; } BST_b; }; @@ -10008,7 +10134,9 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ uint32_t : 3; __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; } BSTE_b; }; @@ -10029,28 +10157,32 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ uint32_t : 3; __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; } BIE_b; }; union { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ struct { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 11; + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; } BSTFC_b; }; @@ -10333,7 +10465,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT0_b; @@ -10350,7 +10483,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT1_b; @@ -10367,7 +10501,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT2_b; @@ -10384,7 +10519,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT3_b; @@ -10402,7 +10538,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } SVDCT_b; @@ -10552,7 +10689,20 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28[2]; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; union { @@ -10678,9 +10828,7 @@ typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -11619,14 +11767,16 @@ typedef struct /*!< (@ 0x40083000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -14933,23 +15083,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -17078,20 +17243,7 @@ typedef struct /*!< (@ 0x40000E00) R_TZF Structure __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ } TZFPT_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[94]; - - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; -} R_TZF_Type; /*!< Size = 388 (0x184) */ +} R_TZF_Type; /*!< Size = 6 (0x6) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -17319,21 +17471,22 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure struct { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 3; - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ } ICUSARE_b; }; @@ -17347,7 +17500,8 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 4; + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ @@ -17358,7 +17512,21 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 17; } ICUSARF_b; }; - __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + uint32_t : 28; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; union { @@ -17412,7 +17580,30 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } BUSSARB_b; }; - __IM uint32_t RESERVED5[10]; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; union { @@ -17437,7 +17628,33 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } MMPUSARB_b; }; - __IM uint32_t RESERVED6[26]; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; union { @@ -17450,7 +17667,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 24; } DMACCHSAR_b; }; - __IM uint32_t RESERVED7[3]; + __IM uint32_t RESERVED9[3]; union { @@ -17462,7 +17679,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[147]; + __IM uint32_t RESERVED10[147]; union { @@ -17491,7 +17708,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 11; } SRAMSABAR1_b; }; - __IM uint32_t RESERVED9[126]; + __IM uint32_t RESERVED11[126]; union { @@ -19668,6 +19885,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -19732,9 +19952,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -21068,12 +21285,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ + #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ + #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ + #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ @@ -21121,6 +21344,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ + #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ @@ -21168,6 +21393,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ + #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ /* ========================================================= PSARE ========================================================= */ #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ @@ -21208,6 +21435,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ + #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ /* ======================================================= CFSAMONA ======================================================== */ #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ @@ -21246,6 +21475,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -22143,6 +22375,11 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -22258,30 +22495,49 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -22762,19 +23018,27 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -23480,10 +23744,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -23520,166 +23780,179 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -24130,6 +24403,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ /* ========================================================= BSTE ========================================================== */ #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ @@ -24145,6 +24420,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ /* ========================================================== BIE ========================================================== */ #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ @@ -24160,6 +24437,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ /* ========================================================= BSTFC ========================================================= */ #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ @@ -24175,6 +24454,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ /* ========================================================= NTST ========================================================== */ #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ @@ -24377,6 +24658,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT1 ========================================================= */ @@ -24388,6 +24673,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT2 ========================================================= */ @@ -24399,6 +24688,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT3 ========================================================= */ @@ -24410,6 +24703,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ @@ -24423,6 +24720,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================= SDCTPIDL ======================================================== */ @@ -24484,6 +24785,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ /* ======================================================== BITCNT ========================================================= */ #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ @@ -24732,20 +25040,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -26581,32 +26879,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ @@ -27330,9 +27606,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -27413,6 +27686,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ @@ -27436,6 +27711,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ @@ -27459,18 +27736,39 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== ICUSARI ======================================================== */ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARA ======================================================== */ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARB ======================================================== */ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ /* ======================================================= MMPUSARA ======================================================== */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ /* ======================================================= DMACCHSAR ======================================================= */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h index 5970775d6..3c210a047 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h @@ -465,24 +465,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -699,27 +716,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; - - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1116,8 +1119,8 @@ typedef struct struct { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 9; } A_b; }; @@ -1127,8 +1130,8 @@ typedef struct struct { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnB Output Rising Edge Delay Setting */ + uint16_t : 9; } B_b; }; } R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ @@ -3191,9 +3194,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3201,16 +3217,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -4134,7 +4150,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -4150,7 +4182,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -4448,11 +4480,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -4464,7 +4507,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -4487,15 +4530,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -4510,7 +4572,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -4993,17 +5092,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -6358,8 +6461,8 @@ typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ uint16_t : 6; - __IOM uint16_t FRANGE : 1; /*!< [8..8] GPT core clock Frequency Range */ - uint16_t : 7; + __IOM uint16_t FRANGE : 2; /*!< [9..8] GPT core clock Frequency Range */ + uint16_t : 6; } GTDLYCR1_b; }; @@ -6451,47 +6554,43 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -6544,7 +6643,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -6707,7 +6807,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -10283,23 +10403,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -11786,6 +11921,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -11850,9 +11988,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -11989,10 +12124,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================== A =========================================================== */ #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ - #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ /* =========================================================== B =========================================================== */ #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ - #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ /* =========================================================================================================================== */ /* ================ SAR ================ */ @@ -12825,6 +12960,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -13409,6 +13547,11 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -13524,30 +13667,49 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -13734,19 +13896,27 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -14407,7 +14577,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= GTDLYCR1 ======================================================== */ #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */ - #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x100UL) /*!< FRANGE (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x300UL) /*!< FRANGE (Bitfield-Mask: 0x03) */ #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ @@ -14471,10 +14641,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -14511,166 +14677,179 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -16470,32 +16649,10 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h index 1b017aed3..ac9db4c0f 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h @@ -468,24 +468,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -702,27 +719,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; - - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1357,7 +1360,7 @@ typedef struct struct { __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry enable */ __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ } ID_b; @@ -1414,7 +1417,7 @@ typedef struct struct { __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ } ID_b; @@ -1574,8 +1577,8 @@ typedef struct struct { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 9; } A_b; }; @@ -1585,8 +1588,8 @@ typedef struct struct { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnB Output Rising Edge Delay Setting */ + uint16_t : 9; } B_b; }; } R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ @@ -1744,7 +1747,7 @@ typedef struct } R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) */ typedef struct { @@ -3617,15 +3620,16 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - uint32_t : 1; + __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; + __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ @@ -3664,7 +3668,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ uint32_t : 1; __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; + __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ + uint32_t : 3; __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ uint32_t : 3; __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ @@ -3705,7 +3710,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - uint32_t : 3; + __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ + uint32_t : 2; } PSARD_b; }; @@ -3745,7 +3751,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ + uint32_t : 27; } MSSAR_b; }; @@ -3910,9 +3917,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3920,16 +3940,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -5011,7 +5031,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -5027,7 +5063,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -5274,11 +5310,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -5290,7 +5337,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -5313,15 +5360,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -5336,7 +5402,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -5817,17 +5920,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -7204,8 +7311,8 @@ typedef struct /*!< (@ 0x4016A000) R_GPT_ODC Structure __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ uint16_t : 6; - __IOM uint16_t FRANGE : 1; /*!< [8..8] GPT core clock Frequency Range */ - uint16_t : 7; + __IOM uint16_t FRANGE : 2; /*!< [9..8] GPT core clock Frequency Range */ + uint16_t : 6; } GTDLYCR1_b; }; @@ -7297,47 +7404,43 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -7390,7 +7493,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -7553,7 +7657,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -8645,7 +8769,9 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ uint32_t : 3; __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; } BST_b; }; @@ -8666,7 +8792,9 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ uint32_t : 3; __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; } BSTE_b; }; @@ -8687,28 +8815,32 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ uint32_t : 3; __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; } BIE_b; }; union { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ struct { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 11; + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; } BSTFC_b; }; @@ -8991,7 +9123,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT0_b; @@ -9008,7 +9141,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT1_b; @@ -9025,7 +9159,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT2_b; @@ -9042,7 +9177,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT3_b; @@ -9060,7 +9196,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } SVDCT_b; @@ -9210,7 +9347,20 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28[2]; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; union { @@ -9336,9 +9486,7 @@ typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -9999,7 +10147,18 @@ typedef struct /*!< (@ 0x4001F800) R_PFS Structure typedef struct /*!< (@ 0x4001FD00) R_PMISC Structure */ { - __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1[5]; @@ -12173,23 +12332,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -13249,20 +13423,7 @@ typedef struct /*!< (@ 0x40000E00) R_TZF Structure __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ } TZFPT_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[94]; - - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; -} R_TZF_Type; /*!< Size = 388 (0x184) */ +} R_TZF_Type; /*!< Size = 6 (0x6) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -13490,21 +13651,22 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure struct { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 3; - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ } ICUSARE_b; }; @@ -13518,7 +13680,8 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 4; + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ @@ -13529,7 +13692,21 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 17; } ICUSARF_b; }; - __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + uint32_t : 28; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; union { @@ -13583,7 +13760,30 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } BUSSARB_b; }; - __IM uint32_t RESERVED5[10]; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; union { @@ -13608,7 +13808,33 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } MMPUSARB_b; }; - __IM uint32_t RESERVED6[26]; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; union { @@ -13621,7 +13847,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 24; } DMACCHSAR_b; }; - __IM uint32_t RESERVED7[3]; + __IM uint32_t RESERVED9[3]; union { @@ -13633,7 +13859,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[147]; + __IM uint32_t RESERVED10[147]; union { @@ -13662,7 +13888,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 11; } SRAMSABAR1_b; }; - __IM uint32_t RESERVED9[126]; + __IM uint32_t RESERVED11[126]; union { @@ -19590,6 +19816,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTX8_BASE 0x400E8800UL #define R_AGTX9_BASE 0x400E8900UL #define R_FLAD_BASE 0x407FC000UL + #define R_SCI_B5_BASE 0x40118500UL + #define R_SCI_B6_BASE 0x40118600UL + #define R_SCI_B7_BASE 0x40118700UL + #define R_SCI_B8_BASE 0x40118800UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -19725,6 +19955,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTW8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGTW9 ((R_AGTX0_Type *) R_AGTX9_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_SCI_B5 ((R_SCI_B0_Type *) R_SCI_B5_BASE) + #define R_SCI_B6 ((R_SCI_B0_Type *) R_SCI_B6_BASE) + #define R_SCI_B7 ((R_SCI_B0_Type *) R_SCI_B7_BASE) + #define R_SCI_B8 ((R_SCI_B0_Type *) R_SCI_B8_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -19932,6 +20166,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -19996,9 +20233,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -20343,6 +20577,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ @@ -20374,6 +20610,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ @@ -20459,10 +20697,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================== A =========================================================== */ #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ - #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ /* =========================================================== B =========================================================== */ #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ - #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ /* =========================================================================================================================== */ /* ================ SAR ================ */ @@ -21294,12 +21532,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ + #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ + #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ + #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ @@ -21347,6 +21591,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ + #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ @@ -21394,6 +21640,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ + #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ /* ========================================================= PSARE ========================================================= */ #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ @@ -21434,6 +21682,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ + #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ /* ======================================================= CFSAMONA ======================================================== */ #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ @@ -21472,6 +21722,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -21953,6 +22206,11 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -22048,30 +22306,49 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -22271,19 +22548,27 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -22952,7 +23237,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= GTDLYCR1 ======================================================== */ #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */ - #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x100UL) /*!< FRANGE (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x300UL) /*!< FRANGE (Bitfield-Mask: 0x03) */ #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ @@ -23016,10 +23301,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -23056,166 +23337,179 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -23756,6 +24050,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ /* ========================================================= BSTE ========================================================== */ #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ @@ -23771,6 +24067,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ /* ========================================================== BIE ========================================================== */ #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ @@ -23786,6 +24084,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ /* ========================================================= BSTFC ========================================================= */ #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ @@ -23801,6 +24101,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ /* ========================================================= NTST ========================================================== */ #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ @@ -24003,6 +24305,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT1 ========================================================= */ @@ -24014,6 +24320,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT2 ========================================================= */ @@ -24025,6 +24335,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT3 ========================================================= */ @@ -24036,6 +24350,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ @@ -24049,6 +24367,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================= SDCTPIDL ======================================================== */ @@ -24110,6 +24432,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ /* ======================================================== BITCNT ========================================================= */ #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ @@ -24200,10 +24529,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== PCNTR1 ========================================================= */ - #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ - #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ /* ========================================================== PDR ========================================================== */ #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ @@ -24211,10 +24540,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ /* ======================================================== PCNTR2 ========================================================= */ - #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ - #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ /* ========================================================= PIDR ========================================================== */ #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ @@ -24222,10 +24551,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ /* ======================================================== PCNTR3 ========================================================= */ - #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ - #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ /* ========================================================= POSR ========================================================== */ #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ @@ -24233,10 +24562,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ /* ======================================================== PCNTR4 ========================================================= */ - #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ - #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ /* ========================================================= EOSR ========================================================== */ #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ @@ -24253,16 +24582,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ /* ========================================================= PWPR ========================================================== */ - #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ - #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ - #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ - #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ /* ========================================================= PWPRS ========================================================= */ - #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ - #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ - #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ - #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_SCI0 ================ */ @@ -25579,32 +25912,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ @@ -25775,9 +26086,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -25858,6 +26166,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ @@ -25881,6 +26191,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ @@ -25904,18 +26216,39 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== ICUSARI ======================================================== */ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARA ======================================================== */ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARB ======================================================== */ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ /* ======================================================= MMPUSARA ======================================================== */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ /* ======================================================= DMACCHSAR ======================================================= */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T3BB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T3BB.h index ca6e51015..a67ed1ffd 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T3BB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T3BB.h @@ -468,24 +468,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -702,27 +719,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; - - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1357,7 +1360,7 @@ typedef struct struct { __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry enable */ __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ } ID_b; @@ -1414,7 +1417,7 @@ typedef struct struct { __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ } ID_b; @@ -1639,7 +1642,7 @@ typedef struct } R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) */ typedef struct { @@ -3594,15 +3597,16 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - uint32_t : 1; + __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; + __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ @@ -3641,7 +3645,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ uint32_t : 1; __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; + __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ + uint32_t : 3; __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ uint32_t : 3; __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ @@ -3682,7 +3687,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - uint32_t : 3; + __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ + uint32_t : 2; } PSARD_b; }; @@ -3722,7 +3728,8 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ + uint32_t : 27; } MSSAR_b; }; @@ -3887,9 +3894,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -3897,16 +3917,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -4988,7 +5008,23 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -5004,7 +5040,7 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -5302,11 +5338,22 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -5318,7 +5365,7 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -5341,15 +5388,34 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -5364,7 +5430,44 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -5847,17 +5950,21 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ } FSAR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -7257,47 +7364,43 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -7350,7 +7453,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure struct { __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ uint8_t : 1; __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ @@ -7513,7 +7617,27 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure uint32_t : 29; } WUPEN1_b; }; - __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; union { @@ -8403,7 +8527,9 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ uint32_t : 3; __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; } BST_b; }; @@ -8424,7 +8550,9 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ uint32_t : 3; __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; } BSTE_b; }; @@ -8445,28 +8573,32 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ uint32_t : 3; __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; } BIE_b; }; union { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ struct { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 11; + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; } BSTFC_b; }; @@ -8749,7 +8881,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT0_b; @@ -8766,7 +8899,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT1_b; @@ -8783,7 +8917,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT2_b; @@ -8800,7 +8935,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT3_b; @@ -8818,7 +8954,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } SVDCT_b; @@ -8968,7 +9105,20 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28[2]; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; union { @@ -9094,9 +9244,7 @@ typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -11996,23 +12144,38 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ - uint32_t : 1; - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ - uint32_t : 1; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - uint32_t : 3; + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - uint32_t : 14; + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ } CGFSAR_b; }; __IM uint32_t RESERVED37; @@ -14193,20 +14356,7 @@ typedef struct /*!< (@ 0x40000E00) R_TZF Structure __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ } TZFPT_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[94]; - - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; -} R_TZF_Type; /*!< Size = 388 (0x184) */ +} R_TZF_Type; /*!< Size = 6 (0x6) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -14434,21 +14584,22 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure struct { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 3; - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ } ICUSARE_b; }; @@ -14462,7 +14613,8 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 4; + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ @@ -14473,7 +14625,21 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 17; } ICUSARF_b; }; - __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + uint32_t : 28; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; union { @@ -14527,7 +14693,30 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } BUSSARB_b; }; - __IM uint32_t RESERVED5[10]; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; union { @@ -14552,7 +14741,33 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } MMPUSARB_b; }; - __IM uint32_t RESERVED6[26]; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; union { @@ -14565,7 +14780,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 24; } DMACCHSAR_b; }; - __IM uint32_t RESERVED7[3]; + __IM uint32_t RESERVED9[3]; union { @@ -14577,7 +14792,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[147]; + __IM uint32_t RESERVED10[147]; union { @@ -14606,7 +14821,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 11; } SRAMSABAR1_b; }; - __IM uint32_t RESERVED9[126]; + __IM uint32_t RESERVED11[126]; union { @@ -15182,6 +15397,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -15246,9 +15464,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -15593,6 +15808,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ @@ -15624,6 +15841,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ @@ -16525,12 +16744,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ + #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ + #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ + #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ @@ -16578,6 +16803,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ + #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ @@ -16625,6 +16852,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ + #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ /* ========================================================= PSARE ========================================================= */ #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ @@ -16665,6 +16894,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ + #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ /* ======================================================= CFSAMONA ======================================================== */ #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ @@ -16703,6 +16934,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -17184,6 +17418,11 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -17299,30 +17538,49 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -17509,19 +17767,27 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ /* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -18227,10 +18493,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -18267,166 +18529,179 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ /* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ /* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ /* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ /* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ /* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ /* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -18877,6 +19152,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ /* ========================================================= BSTE ========================================================== */ #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ @@ -18892,6 +19169,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ /* ========================================================== BIE ========================================================== */ #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ @@ -18907,6 +19186,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ /* ========================================================= BSTFC ========================================================= */ #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ @@ -18922,6 +19203,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ /* ========================================================= NTST ========================================================== */ #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ @@ -19124,6 +19407,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT1 ========================================================= */ @@ -19135,6 +19422,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT2 ========================================================= */ @@ -19146,6 +19437,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT3 ========================================================= */ @@ -19157,6 +19452,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ @@ -19170,6 +19469,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================= SDCTPIDL ======================================================== */ @@ -19231,6 +19534,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ /* ======================================================== BITCNT ========================================================= */ #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ @@ -20719,32 +21029,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ @@ -21486,9 +21774,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CACHE ================ */ @@ -21569,6 +21854,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ @@ -21592,6 +21879,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ @@ -21615,18 +21904,39 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== ICUSARI ======================================================== */ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARA ======================================================== */ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARB ======================================================== */ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ /* ======================================================= MMPUSARA ======================================================== */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ /* ======================================================= DMACCHSAR ======================================================= */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h index 0857662f4..63341bb67 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h @@ -47,8 +47,8 @@ extern "C" { #define __ICACHE_PRESENT 1 /*!< Instruction Cache present */ #define __DCACHE_PRESENT 1 /*!< Data Cache present */ #define __SAUREGION_PRESENT 1 /*!< SAU region present */ - #define __PMU_PRESENT 0 /*!< PMU present */ - #define __PMU_NUM_EVENTCNT 0 /*!< PMU Event Counters */ + #define __PMU_PRESENT 1 /*!< PMU present */ + #define __PMU_NUM_EVENTCNT 8 /*!< PMU Event Counters */ /** @} */ /* End of group Configuration_of_CMSIS */ @@ -472,24 +472,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -706,27 +723,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1361,7 +1364,7 @@ typedef struct struct { __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry enable */ __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ } ID_b; @@ -1418,7 +1421,7 @@ typedef struct struct { __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ } ID_b; @@ -2469,7 +2472,7 @@ typedef struct } R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) */ typedef struct { @@ -4889,32 +4892,42 @@ typedef struct /*!< (@ 0x40204000) R_PSCU Structure union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ - - struct - { - uint32_t : 4; - __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C Bus Interface 2 Security Attribution */ - uint32_t : 3; - __IOM uint32_t PSARB8 : 1; /*!< [8..8] I2C Bus Interface 1 Security Attribution */ - __IOM uint32_t PSARB9 : 1; /*!< [9..9] I2C Bus Interface 0 Security Attribution */ - uint32_t : 1; - __IOM uint32_t PSARB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface 0 Security Attribution */ - __IOM uint32_t PSARB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface 0 Security Attribution */ - uint32_t : 2; - __IOM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0 Controller Security Attribution */ - __IOM uint32_t PSARB16 : 1; /*!< [16..16] Octa Memory Controller Security Attribution */ - uint32_t : 1; - __IOM uint32_t PSARB18 : 1; /*!< [18..18] Serial Peripheral Interface 1 Security Attribution */ - __IOM uint32_t PSARB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Security Attribution */ - uint32_t : 2; - __IOM uint32_t PSARB22 : 1; /*!< [22..22] Serial Communication Interface 9 Security Attribution */ - uint32_t : 4; - __IOM uint32_t PSARB27 : 1; /*!< [27..27] Serial Communication Interface 4 Security Attribution */ - __IOM uint32_t PSARB28 : 1; /*!< [28..28] Serial Communication Interface 3 Security Attribution */ - __IOM uint32_t PSARB29 : 1; /*!< [29..29] Serial Communication Interface 2 Security Attribution */ - __IOM uint32_t PSARB30 : 1; /*!< [30..30] Serial Communication Interface 1 Security Attribution */ - __IOM uint32_t PSARB31 : 1; /*!< [31..31] Serial Communication Interface 0 Security Attribution */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + __IOM uint32_t PSARB0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARB1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARB4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARB6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARB10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARB11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARB13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARB14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARB15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARB16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARB17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARB18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARB20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARB21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARB22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ } PSARB_b; }; @@ -4924,86 +4937,120 @@ typedef struct /*!< (@ 0x40204000) R_PSCU Structure struct { - __IOM uint32_t PSARC0 : 1; /*!< [0..0] Clock Frequency Accuracy Measurement Circuit Security - * Attribution */ - __IOM uint32_t PSARC1 : 1; /*!< [1..1] Cyclic Redundancy Check Calculator Security Attribution */ - uint32_t : 5; - __IOM uint32_t PSARC7 : 1; /*!< [7..7] Serial Sound Interface Enhanced (channel 1) Security - * Attribution */ - __IOM uint32_t PSARC8 : 1; /*!< [8..8] Serial Sound Interface Enhanced (channel 0) Security - * Attribution */ - uint32_t : 2; - __IOM uint32_t PSARC11 : 1; /*!< [11..11] Secure Digital Host IF 1 Security Attribution */ - __IOM uint32_t PSARC12 : 1; /*!< [12..12] Secure Digital Host IF 0 Security Attribution */ - __IOM uint32_t PSARC13 : 1; /*!< [13..13] Data Operation Circuit Security Attribution */ - uint32_t : 1; - __IOM uint32_t PSARC15 : 1; /*!< [15..15] Graph-ic(GLCDC,MIPI,DRW,JPEG) Security Attribution */ - __IOM uint32_t PSARC16 : 1; /*!< [16..16] CEU Security Attribution */ - uint32_t : 9; - __IOM uint32_t PSARC26 : 1; /*!< [26..26] Controller Area Network with Flexible Data-Rate 1 Security - * Attribution */ - __IOM uint32_t PSARC27 : 1; /*!< [27..27] Controller Area Network with Flexible Data-Rate 0 Security - * Attribution */ - uint32_t : 3; - __IOM uint32_t PSARC31 : 1; /*!< [31..31] SHIP Security Attribution */ + __IOM uint32_t PSARC0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARC2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARC3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARC4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARC5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARC6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARC7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARC8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARC9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARC10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARC11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARC12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARC14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARC15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARC16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARC17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARC18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARC19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARC20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARC21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARC22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARC23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARC24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARC25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARC26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARC27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARC28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARC29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARC30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARC31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ } PSARC_b; }; union { - __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ - - struct - { - uint32_t : 4; - __IOM uint32_t PSARD4 : 1; /*!< [4..4] Asynchronous General Purpose Timer 1 Security Attribution */ - __IOM uint32_t PSARD5 : 1; /*!< [5..5] Asynchronous General Purpose Timer 0 Security Attribution */ - uint32_t : 5; - __IOM uint32_t PSARD11 : 1; /*!< [11..11] Port Output Enable for GPT Group 3 Security Attribution */ - __IOM uint32_t PSARD12 : 1; /*!< [12..12] Port Output Enable for GPT Group 2 Security Attribution */ - __IOM uint32_t PSARD13 : 1; /*!< [13..13] Port Output Enable for GPT Group 1 Security Attribution */ - __IOM uint32_t PSARD14 : 1; /*!< [14..14] Port Output Enable for GPT Group 0 Security Attribution */ - __IOM uint32_t PSARD15 : 1; /*!< [15..15] 12-Bit A/D 1 Converter Security Attribution */ - __IOM uint32_t PSARD16 : 1; /*!< [16..16] 12-Bit A/D 0 Converter Security Attribution */ - uint32_t : 3; - __IOM uint32_t PSARD20 : 1; /*!< [20..20] 12-Bit D/A Converter Security Attribution */ - uint32_t : 1; - __IOM uint32_t PSARD22 : 1; /*!< [22..22] Temperature Sensor Security Attribution */ - uint32_t : 4; - __IOM uint32_t PSARD27 : 1; /*!< [27..27] High speed analog Comparator 1 Security Attribution */ - __IOM uint32_t PSARD28 : 1; /*!< [28..28] High speed analog Comparator 0 Security Attribution */ - uint32_t : 3; + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARD4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARD5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARD6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARD7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARD8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARD9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARD10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARD11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARD17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARD18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARD19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARD21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARD22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARD23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARD24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARD25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARD29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARD30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARD31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ } PSARD_b; }; union { - __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ - - struct - { - uint32_t : 1; - __IOM uint32_t PSARE1 : 1; /*!< [1..1] WDT0 Security Attribution */ - __IOM uint32_t PSARE2 : 1; /*!< [2..2] Independent Watchdog Timer Security Attribution */ - __IOM uint32_t PSARE3 : 1; /*!< [3..3] Real Time Clock Security Attribution */ - uint32_t : 4; - __IOM uint32_t PSARE8 : 1; /*!< [8..8] ULPT1 Security Attribution */ - __IOM uint32_t PSARE9 : 1; /*!< [9..9] ULPT0 Security Attribution */ - uint32_t : 8; - __IOM uint32_t PSARE18 : 1; /*!< [18..18] General PWM Timer channel13 Security Attribution */ - __IOM uint32_t PSARE19 : 1; /*!< [19..19] General PWM Timer channel12 Security Attribution */ - __IOM uint32_t PSARE20 : 1; /*!< [20..20] General PWM Timer channel11 Security Attribution */ - __IOM uint32_t PSARE21 : 1; /*!< [21..21] General PWM Timer channel10 Security Attribution */ - __IOM uint32_t PSARE22 : 1; /*!< [22..22] General PWM Timer channel9 Security Attribution */ - __IOM uint32_t PSARE23 : 1; /*!< [23..23] General PWM Timer channel8 Security Attribution */ - __IOM uint32_t PSARE24 : 1; /*!< [24..24] General PWM Timer channel7 Security Attribution */ - __IOM uint32_t PSARE25 : 1; /*!< [25..25] General PWM Timer channel6 Security Attribution */ - __IOM uint32_t PSARE26 : 1; /*!< [26..26] General PWM Timer channel5 Security Attribution */ - __IOM uint32_t PSARE27 : 1; /*!< [27..27] General PWM Timer channel4 Security Attribution */ - __IOM uint32_t PSARE28 : 1; /*!< [28..28] General PWM Timer channel3 Security Attribution */ - __IOM uint32_t PSARE29 : 1; /*!< [29..29] General PWM Timer channel2 Security Attribution */ - __IOM uint32_t PSARE30 : 1; /*!< [30..30] General PWM Timer channel1 Security Attribution */ - __IOM uint32_t PSARE31 : 1; /*!< [31..31] General PWM Timer channel0 Security Attribution */ + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARE3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARE4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARE5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARE6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARE7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARE8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARE9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARE10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARE11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARE12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARE13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARE14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARE16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARE17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARE18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARE19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARE20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARE21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARE22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ } PSARE_b; }; @@ -5013,50 +5060,80 @@ typedef struct /*!< (@ 0x40204000) R_PSCU Structure struct { - __IOM uint32_t MSSAR0 : 1; /*!< [0..0] SRAM0 Clock Stop Security Attribution */ - __IOM uint32_t MSSAR1 : 1; /*!< [1..1] SRAM1 Clock Stop Security Attribution */ - uint32_t : 9; - __IOM uint32_t MSSAR11 : 1; /*!< [11..11] CTCM0 Security Attribution */ - uint32_t : 1; - __IOM uint32_t MSSAR13 : 1; /*!< [13..13] STCM0 Security Attribution */ - uint32_t : 1; - __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Standby RAM Clock Stop Security Attribution */ - uint32_t : 6; - __IOM uint32_t MSSAR22 : 1; /*!< [22..22] DMAC0/DTC0 Clock Stop Security Attribution */ - uint32_t : 8; - __IOM uint32_t MSSAR31 : 1; /*!< [31..31] ELC clock stop Security Attribution */ + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] Module stop security attribution bit 0 */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] Module stop security attribution bit 1 */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] Module stop security attribution bit 2 */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] Module stop security attribution bit 3 */ + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] Module stop security attribution bit 4 */ + __IOM uint32_t MSSAR5 : 1; /*!< [5..5] Module stop security attribution bit 5 */ + __IOM uint32_t MSSAR6 : 1; /*!< [6..6] Module stop security attribution bit 6 */ + __IOM uint32_t MSSAR7 : 1; /*!< [7..7] Module stop security attribution bit 7 */ + __IOM uint32_t MSSAR8 : 1; /*!< [8..8] Module stop security attribution bit 8 */ + __IOM uint32_t MSSAR9 : 1; /*!< [9..9] Module stop security attribution bit 9 */ + __IOM uint32_t MSSAR10 : 1; /*!< [10..10] Module stop security attribution bit 10 */ + __IOM uint32_t MSSAR11 : 1; /*!< [11..11] Module stop security attribution bit 11 */ + __IOM uint32_t MSSAR12 : 1; /*!< [12..12] Module stop security attribution bit 12 */ + __IOM uint32_t MSSAR13 : 1; /*!< [13..13] Module stop security attribution bit 13 */ + __IOM uint32_t MSSAR14 : 1; /*!< [14..14] Module stop security attribution bit 14 */ + __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Module stop security attribution bit 15 */ + __IOM uint32_t MSSAR16 : 1; /*!< [16..16] Module stop security attribution bit 16 */ + __IOM uint32_t MSSAR17 : 1; /*!< [17..17] Module stop security attribution bit 17 */ + __IOM uint32_t MSSAR18 : 1; /*!< [18..18] Module stop security attribution bit 18 */ + __IOM uint32_t MSSAR19 : 1; /*!< [19..19] Module stop security attribution bit 19 */ + __IOM uint32_t MSSAR20 : 1; /*!< [20..20] Module stop security attribution bit 20 */ + __IOM uint32_t MSSAR21 : 1; /*!< [21..21] Module stop security attribution bit 21 */ + __IOM uint32_t MSSAR22 : 1; /*!< [22..22] Module stop security attribution bit 22 */ + __IOM uint32_t MSSAR23 : 1; /*!< [23..23] Module stop security attribution bit 23 */ + __IOM uint32_t MSSAR24 : 1; /*!< [24..24] Module stop security attribution bit 24 */ + __IOM uint32_t MSSAR25 : 1; /*!< [25..25] Module stop security attribution bit 25 */ + __IOM uint32_t MSSAR26 : 1; /*!< [26..26] Module stop security attribution bit 26 */ + __IOM uint32_t MSSAR27 : 1; /*!< [27..27] Module stop security attribution bit 27 */ + __IOM uint32_t MSSAR28 : 1; /*!< [28..28] Module stop security attribution bit 28 */ + __IOM uint32_t MSSAR29 : 1; /*!< [29..29] Module stop security attribution bit 29 */ + __IOM uint32_t MSSAR30 : 1; /*!< [30..30] Module stop security attribution bit 30 */ + __IOM uint32_t MSSAR31 : 1; /*!< [31..31] Module stop security attribution bit 31 */ } MSSAR_b; }; __IM uint32_t RESERVED1; union { - __IOM uint32_t PPARB; /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B */ - - struct - { - uint32_t : 4; - __IOM uint32_t PPARB4 : 1; /*!< [4..4] I3C Bus Interface 2 Privilege Attribution */ - uint32_t : 3; - __IOM uint32_t PPARB8 : 1; /*!< [8..8] I2C Bus Interface 1 Privilege Attribution */ - __IOM uint32_t PPARB9 : 1; /*!< [9..9] I2C Bus Interface 0 Privilege Attribution */ - uint32_t : 1; - __IOM uint32_t PPARB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface 0 Privilege Attribution */ - __IOM uint32_t PPARB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface 0 Privilege Attribution */ - uint32_t : 2; - __IOM uint32_t PPARB15 : 1; /*!< [15..15] ETHER0/EDMAC0 Controller Privilege Attribution */ - __IOM uint32_t PPARB16 : 1; /*!< [16..16] Octa Memory Controller Privilege Attribution */ - uint32_t : 1; - __IOM uint32_t PPARB18 : 1; /*!< [18..18] Serial Peripheral Interface 1 Privilege Attribution */ - __IOM uint32_t PPARB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Privilege Attribution */ - uint32_t : 2; - __IOM uint32_t PPARB22 : 1; /*!< [22..22] Serial Communication Interface 9 Privilege Attribution */ - uint32_t : 4; - __IOM uint32_t PPARB27 : 1; /*!< [27..27] Serial Communication Interface 4 Privilege Attribution */ - __IOM uint32_t PPARB28 : 1; /*!< [28..28] Serial Communication Interface 3 Privilege Attribution */ - __IOM uint32_t PPARB29 : 1; /*!< [29..29] Serial Communication Interface 2 Privilege Attribution */ - __IOM uint32_t PPARB30 : 1; /*!< [30..30] Serial Communication Interface 1 Privilege Attribution */ - __IOM uint32_t PPARB31 : 1; /*!< [31..31] Serial Communication Interface 0 Privilege Attribution */ + __IOM uint32_t PPARB; /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B */ + + struct + { + __IOM uint32_t PPARB0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARB1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARB2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARB3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARB4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARB5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARB6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARB7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARB8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARB9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARB10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARB11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARB12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARB13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARB14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARB15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARB16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARB17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARB18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARB19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARB20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARB21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARB22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARB23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARB24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARB25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARB26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARB27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARB28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARB29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARB30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARB31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ } PPARB_b; }; @@ -5066,104 +5143,167 @@ typedef struct /*!< (@ 0x40204000) R_PSCU Structure struct { - __IOM uint32_t PPARC0 : 1; /*!< [0..0] Clock Frequency Accuracy Measurement Circuit Privilege - * Attribution */ - __IOM uint32_t PPARC1 : 1; /*!< [1..1] Cyclic Redundancy Check Calculator Privilege Attribution */ - uint32_t : 5; - __IOM uint32_t PPARC7 : 1; /*!< [7..7] Serial Sound Interface Enhanced (channel 1) Privilege - * Attribution */ - __IOM uint32_t PPARC8 : 1; /*!< [8..8] Serial Sound Interface Enhanced (channel 0) Privilege - * Attribution */ - uint32_t : 2; - __IOM uint32_t PPARC11 : 1; /*!< [11..11] Privilege Digital Host IF 1 Privilege Attribution */ - __IOM uint32_t PPARC12 : 1; /*!< [12..12] Privilege Digital Host IF 0 Privilege Attribution */ - __IOM uint32_t PPARC13 : 1; /*!< [13..13] Data Operation Circuit Privilege Attribution */ - uint32_t : 1; - __IOM uint32_t PPARC15 : 1; /*!< [15..15] Graph-ic(GLCDC,MIPI,DRW,JPEG) Privilege Attribution */ - __IOM uint32_t PPARC16 : 1; /*!< [16..16] CEU Privilege Attribution */ - uint32_t : 9; - __IOM uint32_t PPARC26 : 1; /*!< [26..26] Controller Area Network with Flexible Data-Rate 1 Privilege - * Attribution */ - __IOM uint32_t PPARC27 : 1; /*!< [27..27] Controller Area Network with Flexible Data-Rate 0 Privilege - * Attribution */ - uint32_t : 3; - __IOM uint32_t PPARC31 : 1; /*!< [31..31] SHIP Privilege Attribution */ + __IOM uint32_t PPARC0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARC1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARC2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARC3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARC4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARC5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARC6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARC7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARC8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARC9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARC10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARC11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARC12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARC13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARC14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARC15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARC16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARC17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARC18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARC19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARC20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARC21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARC22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARC23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARC24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARC25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARC26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARC27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARC28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARC29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARC30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARC31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ } PPARC_b; }; union { - __IOM uint32_t PPARD; /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D */ - - struct - { - uint32_t : 4; - __IOM uint32_t PPARD4 : 1; /*!< [4..4] Asynchronous General Purpose Timer 1 Privilege Attribution */ - __IOM uint32_t PPARD5 : 1; /*!< [5..5] Asynchronous General Purpose Timer 0 Privilege Attribution */ - uint32_t : 5; - __IOM uint32_t PPARD11 : 1; /*!< [11..11] Port Output Enable for GPT Group 3 Privilege Attribution */ - __IOM uint32_t PPARD12 : 1; /*!< [12..12] Port Output Enable for GPT Group 2 Privilege Attribution */ - __IOM uint32_t PPARD13 : 1; /*!< [13..13] Port Output Enable for GPT Group 1 Privilege Attribution */ - __IOM uint32_t PPARD14 : 1; /*!< [14..14] Port Output Enable for GPT Group 0 Privilege Attribution */ - __IOM uint32_t PPARD15 : 1; /*!< [15..15] 12-Bit A/D 1 Converter Privilege Attribution */ - __IOM uint32_t PPARD16 : 1; /*!< [16..16] 12-Bit A/D 0 Converter Privilege Attribution */ - uint32_t : 3; - __IOM uint32_t PPARD20 : 1; /*!< [20..20] 12-Bit D/A Converter Privilege Attribution */ - uint32_t : 1; - __IOM uint32_t PPARD22 : 1; /*!< [22..22] Temperature Sensor Privilege Attribution */ - uint32_t : 4; - __IOM uint32_t PPARD27 : 1; /*!< [27..27] High speed analog Comparator 1 Privilege Attribution */ - __IOM uint32_t PPARD28 : 1; /*!< [28..28] High speed analog Comparator 0 Privilege Attribution */ - uint32_t : 3; + __IOM uint32_t PPARD; /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D */ + + struct + { + __IOM uint32_t PPARD0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARD1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARD2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARD3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARD4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARD5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARD6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARD7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARD8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARD9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARD10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARD11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARD12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARD13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARD14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARD15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARD16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARD17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARD18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARD19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARD20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARD21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARD22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARD23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARD24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARD25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARD26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARD27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARD28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARD29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARD30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARD31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ } PPARD_b; }; union { - __IOM uint32_t PPARE; /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E */ - - struct - { - uint32_t : 1; - __IOM uint32_t PPARE1 : 1; /*!< [1..1] Watchdog Timer0 Privilege Attribution */ - __IOM uint32_t PPARE2 : 1; /*!< [2..2] Independent Watchdog Timer Privilege Attribution */ - __IOM uint32_t PPARE3 : 1; /*!< [3..3] Real Time Clock Privilege Attribution */ - uint32_t : 4; - __IOM uint32_t PPARE8 : 1; /*!< [8..8] ULPT1 Privilege Attribution */ - __IOM uint32_t PPARE9 : 1; /*!< [9..9] ULPT0 Privilege Attribution */ - uint32_t : 8; - __IOM uint32_t PPARE18 : 1; /*!< [18..18] General PWM Timer channel13 Privilege Attribution */ - __IOM uint32_t PPARE19 : 1; /*!< [19..19] General PWM Timer channel12 Privilege Attribution */ - __IOM uint32_t PPARE20 : 1; /*!< [20..20] General PWM Timer channel11 Privilege Attribution */ - __IOM uint32_t PPARE21 : 1; /*!< [21..21] General PWM Timer channel10 Privilege Attribution */ - __IOM uint32_t PPARE22 : 1; /*!< [22..22] General PWM Timer channel9 Privilege Attribution */ - __IOM uint32_t PPARE23 : 1; /*!< [23..23] General PWM Timer channel8 Privilege Attribution */ - __IOM uint32_t PPARE24 : 1; /*!< [24..24] General PWM Timer channel7 Privilege Attribution */ - __IOM uint32_t PPARE25 : 1; /*!< [25..25] General PWM Timer channel6 Privilege Attribution */ - __IOM uint32_t PPARE26 : 1; /*!< [26..26] General PWM Timer channel5 Privilege Attribution */ - __IOM uint32_t PPARE27 : 1; /*!< [27..27] General PWM Timer channel4 Privilege Attribution */ - __IOM uint32_t PPARE28 : 1; /*!< [28..28] General PWM Timer channel3 Privilege Attribution */ - __IOM uint32_t PPARE29 : 1; /*!< [29..29] General PWM Timer channel2 Privilege Attribution */ - __IOM uint32_t PPARE30 : 1; /*!< [30..30] General PWM Timer channel1 Privilege Attribution */ - __IOM uint32_t PPARE31 : 1; /*!< [31..31] General PWM Timer channel0 Privilege Attribution */ + __IOM uint32_t PPARE; /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E */ + + struct + { + __IOM uint32_t PPARE0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARE1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARE2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARE3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARE4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARE5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARE6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARE7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARE8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARE9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARE10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARE11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARE12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARE13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARE14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARE15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARE16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARE17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARE18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARE19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARE20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARE21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARE22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARE23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARE24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARE25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARE26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARE27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARE28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARE29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARE30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARE31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ } PPARE_b; }; union { - __IOM uint32_t MSPAR; /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register */ - - struct - { - uint32_t : 31; - __IOM uint32_t MSPAR31 : 1; /*!< [31..31] ELC clock stop Privilege Attribution */ + __IOM uint32_t MSPAR; /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register */ + + struct + { + __IOM uint32_t MSPAR0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t MSPAR1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t MSPAR2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t MSPAR3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t MSPAR4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t MSPAR5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t MSPAR6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t MSPAR7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t MSPAR8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t MSPAR9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t MSPAR10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t MSPAR11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t MSPAR12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t MSPAR13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t MSPAR14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t MSPAR15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t MSPAR16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t MSPAR17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t MSPAR18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t MSPAR19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t MSPAR20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t MSPAR21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t MSPAR22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t MSPAR23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t MSPAR24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t MSPAR25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t MSPAR26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t MSPAR27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t MSPAR28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t MSPAR29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t MSPAR30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t MSPAR31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ } MSPAR_b; }; union { - __IM uint32_t CFSAMONA; /*!< (@ 0x00000030) Code Flash Security Attribution Monitor Register - * A */ + __IM uint32_t CFSAMONA; /*!< (@ 0x00000030) Code Flash Security Attribution Monitor Register */ struct { @@ -5284,9 +5424,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -5294,16 +5447,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -6385,7 +6538,23 @@ typedef struct /*!< (@ 0x4000A800) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -6401,7 +6570,7 @@ typedef struct /*!< (@ 0x4000A800) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -7354,7 +7523,20 @@ typedef struct /*!< (@ 0x40344000) R_DRW Structure uint32_t : 8; } COLKEY_b; }; -} R_DRW_Type; /*!< Size = 236 (0xec) */ + __IM uint32_t RESERVED6[5]; + + union + { + __IOM uint32_t DBWER; /*!< (@ 0x00000100) DRW Bufferable Write Enable Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t BWE : 1; /*!< [2..2] Bufferable Write Enable */ + uint32_t : 29; + } DBWER_b; + }; +} R_DRW_Type; /*!< Size = 260 (0x104) */ /* =========================================================================================================================== */ /* ================ R_DTC ================ */ @@ -7386,11 +7568,22 @@ typedef struct /*!< (@ 0x4000AC00) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -7402,7 +7595,7 @@ typedef struct /*!< (@ 0x4000AC00) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -7425,15 +7618,34 @@ typedef struct /*!< (@ 0x4000AC00) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -7448,7 +7660,44 @@ typedef struct /*!< (@ 0x4000AC00) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -10185,47 +10434,43 @@ typedef struct /*!< (@ 0x40323F00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40212000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40212000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -11356,7 +11601,9 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ uint32_t : 3; __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; } BST_b; }; @@ -11377,7 +11624,9 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ uint32_t : 3; __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; } BSTE_b; }; @@ -11398,28 +11647,32 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ uint32_t : 3; __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; } BIE_b; }; union { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ struct { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 11; + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; } BSTFC_b; }; @@ -11702,7 +11955,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT0_b; @@ -11719,7 +11973,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT1_b; @@ -11736,7 +11991,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT2_b; @@ -11753,7 +12009,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT3_b; @@ -11771,7 +12028,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } SVDCT_b; @@ -11921,7 +12179,20 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28[2]; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; union { @@ -12047,9 +12318,7 @@ typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -12718,7 +12987,8 @@ typedef struct /*!< (@ 0x40400D00) R_PMISC Structure { uint8_t : 4; __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ - uint8_t : 3; + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; } PFENET_b; }; __IM uint8_t RESERVED; @@ -12770,14 +13040,16 @@ typedef struct /*!< (@ 0x40202000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -15940,10 +16212,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint32_t WDT1RF : 1; /*!< [17..17] Watchdog Timer1 Reset Detect Flag. NOTE: Writable only * to clear the flag. Confirm the value is 1 and then write * 0. */ - uint32_t : 2; - __IOM uint32_t CLU1RF : 1; /*!< [20..20] CPU1 Lockup Reset Detect Flag. NOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ + uint32_t : 3; __IOM uint32_t LM1RF : 1; /*!< [21..21] Local memory 1 error Reset Detect Flag. NOTE: Writable * only to clear the flag. Confirm the value is 1 and then * write 0. */ @@ -16876,13 +17145,10 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - uint8_t : 1; - __IOM uint8_t WDT1MASK : 1; /*!< [1..1] CPU1 Watchdog timer Reset Mask */ - uint8_t : 2; - __IOM uint8_t CLUP1MASK : 1; /*!< [4..4] CPU1 Lockup Reset Mask */ - __IOM uint8_t LM1MASK : 1; /*!< [5..5] Local memory 1 error Reset Mask */ - uint8_t : 1; - __IOM uint8_t NWMASK : 1; /*!< [7..7] Network Reset Mask */ + uint8_t : 5; + __IOM uint8_t LM1MASK : 1; /*!< [5..5] Local memory 1 error Reset Mask */ + uint8_t : 1; + __IOM uint8_t NWMASK : 1; /*!< [7..7] Network Reset Mask */ } SYRSTMSK1_b; }; __IM uint8_t RESERVED129; @@ -19767,21 +20033,22 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure struct { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 3; - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ } ICUSARE_b; }; @@ -19795,7 +20062,8 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 4; + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ @@ -19806,7 +20074,21 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 17; } ICUSARF_b; }; - __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + uint32_t : 28; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; union { @@ -19860,7 +20142,30 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } BUSSARB_b; }; - __IM uint32_t RESERVED5[10]; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; union { @@ -19885,7 +20190,33 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } MMPUSARB_b; }; - __IM uint32_t RESERVED6[26]; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; union { @@ -19898,7 +20229,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 24; } DMACCHSAR_b; }; - __IM uint32_t RESERVED7[3]; + __IM uint32_t RESERVED9[3]; union { @@ -19910,7 +20241,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[147]; + __IM uint32_t RESERVED10[147]; union { @@ -19939,7 +20270,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 11; } SRAMSABAR1_b; }; - __IM uint32_t RESERVED9[126]; + __IM uint32_t RESERVED11[126]; union { @@ -30013,6 +30344,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_DSILINK_BASE (0x40346000UL + BASE_NS_OFFSET) #define R_FLAD_BASE (0x4011C000UL + BASE_NS_OFFSET) #define R_OFS_DATAFLASH_BASE (0x27030000UL + BASE_NS_OFFSET) + #define R_SCI_B5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI_B6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI_B7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI_B8_BASE (0x40358800UL + BASE_NS_OFFSET) /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -30162,6 +30497,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_DSILINK ((R_DSILINK_Type *) R_DSILINK_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) #define R_OFS_DATAFLASH ((R_OFS_DATAFLASH_Type *) R_OFS_DATAFLASH_BASE) + #define R_SCI_B5 ((R_SCI_B0_Type *) R_SCI_B5_BASE) + #define R_SCI_B6 ((R_SCI_B0_Type *) R_SCI_B6_BASE) + #define R_SCI_B7 ((R_SCI_B0_Type *) R_SCI_B7_BASE) + #define R_SCI_B8 ((R_SCI_B0_Type *) R_SCI_B8_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -30369,6 +30708,9 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -30433,9 +30775,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -30780,6 +31119,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ @@ -30811,6 +31152,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ @@ -32208,272 +32551,44 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* =========================================================================================================================== */ /* ========================================================= PSARB ========================================================= */ - #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ - #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ - #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ - #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ - #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ - #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ - #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ - #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ - #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ - #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ - #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ - #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ - #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ - #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ - #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ - #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB_Pos (0UL) /*!< PSARB (Bit 0) */ + #define R_PSCU_PSARB_PSARB_Msk (0x1UL) /*!< PSARB (Bitfield-Mask: 0x01) */ /* ========================================================= PSARC ========================================================= */ - #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ - #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ - #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC7_Pos (7UL) /*!< PSARC7 (Bit 7) */ - #define R_PSCU_PSARC_PSARC7_Msk (0x80UL) /*!< PSARC7 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ - #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC11_Pos (11UL) /*!< PSARC11 (Bit 11) */ - #define R_PSCU_PSARC_PSARC11_Msk (0x800UL) /*!< PSARC11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ - #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ - #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC15_Pos (15UL) /*!< PSARC15 (Bit 15) */ - #define R_PSCU_PSARC_PSARC15_Msk (0x8000UL) /*!< PSARC15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC16_Pos (16UL) /*!< PSARC16 (Bit 16) */ - #define R_PSCU_PSARC_PSARC16_Msk (0x10000UL) /*!< PSARC16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC26_Pos (26UL) /*!< PSARC26 (Bit 26) */ - #define R_PSCU_PSARC_PSARC26_Msk (0x4000000UL) /*!< PSARC26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ - #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ - #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC_Pos (0UL) /*!< PSARC (Bit 0) */ + #define R_PSCU_PSARC_PSARC_Msk (0x1UL) /*!< PSARC (Bitfield-Mask: 0x01) */ /* ========================================================= PSARD ========================================================= */ - #define R_PSCU_PSARD_PSARD4_Pos (4UL) /*!< PSARD4 (Bit 4) */ - #define R_PSCU_PSARD_PSARD4_Msk (0x10UL) /*!< PSARD4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD5_Pos (5UL) /*!< PSARD5 (Bit 5) */ - #define R_PSCU_PSARD_PSARD5_Msk (0x20UL) /*!< PSARD5 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ - #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ - #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ - #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ - #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ - #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ - #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ - #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ - #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ - #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ - #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD_Pos (0UL) /*!< PSARD (Bit 0) */ + #define R_PSCU_PSARD_PSARD_Msk (0x1UL) /*!< PSARD (Bitfield-Mask: 0x01) */ /* ========================================================= PSARE ========================================================= */ - #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ - #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ - #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE3_Pos (3UL) /*!< PSARE3 (Bit 3) */ - #define R_PSCU_PSARE_PSARE3_Msk (0x8UL) /*!< PSARE3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE8_Pos (8UL) /*!< PSARE8 (Bit 8) */ - #define R_PSCU_PSARE_PSARE8_Msk (0x100UL) /*!< PSARE8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE9_Pos (9UL) /*!< PSARE9 (Bit 9) */ - #define R_PSCU_PSARE_PSARE9_Msk (0x200UL) /*!< PSARE9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE18_Pos (18UL) /*!< PSARE18 (Bit 18) */ - #define R_PSCU_PSARE_PSARE18_Msk (0x40000UL) /*!< PSARE18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE19_Pos (19UL) /*!< PSARE19 (Bit 19) */ - #define R_PSCU_PSARE_PSARE19_Msk (0x80000UL) /*!< PSARE19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE20_Pos (20UL) /*!< PSARE20 (Bit 20) */ - #define R_PSCU_PSARE_PSARE20_Msk (0x100000UL) /*!< PSARE20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE21_Pos (21UL) /*!< PSARE21 (Bit 21) */ - #define R_PSCU_PSARE_PSARE21_Msk (0x200000UL) /*!< PSARE21 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ - #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ - #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ - #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ - #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ - #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ - #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ - #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ - #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ - #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ - #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE_Pos (0UL) /*!< PSARE (Bit 0) */ + #define R_PSCU_PSARE_PSARE_Msk (0x1UL) /*!< PSARE (Bitfield-Mask: 0x01) */ /* ========================================================= MSSAR ========================================================= */ - #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ - #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ - #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR11_Pos (11UL) /*!< MSSAR11 (Bit 11) */ - #define R_PSCU_MSSAR_MSSAR11_Msk (0x800UL) /*!< MSSAR11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR13_Pos (13UL) /*!< MSSAR13 (Bit 13) */ - #define R_PSCU_MSSAR_MSSAR13_Msk (0x2000UL) /*!< MSSAR13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR15_Pos (15UL) /*!< MSSAR15 (Bit 15) */ - #define R_PSCU_MSSAR_MSSAR15_Msk (0x8000UL) /*!< MSSAR15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR22_Pos (22UL) /*!< MSSAR22 (Bit 22) */ - #define R_PSCU_MSSAR_MSSAR22_Msk (0x400000UL) /*!< MSSAR22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR31_Pos (31UL) /*!< MSSAR31 (Bit 31) */ - #define R_PSCU_MSSAR_MSSAR31_Msk (0x80000000UL) /*!< MSSAR31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR_Pos (0UL) /*!< MSSAR (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR_Msk (0x1UL) /*!< MSSAR (Bitfield-Mask: 0x01) */ /* ========================================================= PPARB ========================================================= */ - #define R_PSCU_PPARB_PPARB4_Pos (4UL) /*!< PPARB4 (Bit 4) */ - #define R_PSCU_PPARB_PPARB4_Msk (0x10UL) /*!< PPARB4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB8_Pos (8UL) /*!< PPARB8 (Bit 8) */ - #define R_PSCU_PPARB_PPARB8_Msk (0x100UL) /*!< PPARB8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB9_Pos (9UL) /*!< PPARB9 (Bit 9) */ - #define R_PSCU_PPARB_PPARB9_Msk (0x200UL) /*!< PPARB9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB11_Pos (11UL) /*!< PPARB11 (Bit 11) */ - #define R_PSCU_PPARB_PPARB11_Msk (0x800UL) /*!< PPARB11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB12_Pos (12UL) /*!< PPARB12 (Bit 12) */ - #define R_PSCU_PPARB_PPARB12_Msk (0x1000UL) /*!< PPARB12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB15_Pos (15UL) /*!< PPARB15 (Bit 15) */ - #define R_PSCU_PPARB_PPARB15_Msk (0x8000UL) /*!< PPARB15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB16_Pos (16UL) /*!< PPARB16 (Bit 16) */ - #define R_PSCU_PPARB_PPARB16_Msk (0x10000UL) /*!< PPARB16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB18_Pos (18UL) /*!< PPARB18 (Bit 18) */ - #define R_PSCU_PPARB_PPARB18_Msk (0x40000UL) /*!< PPARB18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB19_Pos (19UL) /*!< PPARB19 (Bit 19) */ - #define R_PSCU_PPARB_PPARB19_Msk (0x80000UL) /*!< PPARB19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB22_Pos (22UL) /*!< PPARB22 (Bit 22) */ - #define R_PSCU_PPARB_PPARB22_Msk (0x400000UL) /*!< PPARB22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB27_Pos (27UL) /*!< PPARB27 (Bit 27) */ - #define R_PSCU_PPARB_PPARB27_Msk (0x8000000UL) /*!< PPARB27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB28_Pos (28UL) /*!< PPARB28 (Bit 28) */ - #define R_PSCU_PPARB_PPARB28_Msk (0x10000000UL) /*!< PPARB28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB29_Pos (29UL) /*!< PPARB29 (Bit 29) */ - #define R_PSCU_PPARB_PPARB29_Msk (0x20000000UL) /*!< PPARB29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB30_Pos (30UL) /*!< PPARB30 (Bit 30) */ - #define R_PSCU_PPARB_PPARB30_Msk (0x40000000UL) /*!< PPARB30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB31_Pos (31UL) /*!< PPARB31 (Bit 31) */ - #define R_PSCU_PPARB_PPARB31_Msk (0x80000000UL) /*!< PPARB31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB_Pos (0UL) /*!< PPARB (Bit 0) */ + #define R_PSCU_PPARB_PPARB_Msk (0x1UL) /*!< PPARB (Bitfield-Mask: 0x01) */ /* ========================================================= PPARC ========================================================= */ - #define R_PSCU_PPARC_PPARC0_Pos (0UL) /*!< PPARC0 (Bit 0) */ - #define R_PSCU_PPARC_PPARC0_Msk (0x1UL) /*!< PPARC0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC1_Pos (1UL) /*!< PPARC1 (Bit 1) */ - #define R_PSCU_PPARC_PPARC1_Msk (0x2UL) /*!< PPARC1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC7_Pos (7UL) /*!< PPARC7 (Bit 7) */ - #define R_PSCU_PPARC_PPARC7_Msk (0x80UL) /*!< PPARC7 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC8_Pos (8UL) /*!< PPARC8 (Bit 8) */ - #define R_PSCU_PPARC_PPARC8_Msk (0x100UL) /*!< PPARC8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC11_Pos (11UL) /*!< PPARC11 (Bit 11) */ - #define R_PSCU_PPARC_PPARC11_Msk (0x800UL) /*!< PPARC11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC12_Pos (12UL) /*!< PPARC12 (Bit 12) */ - #define R_PSCU_PPARC_PPARC12_Msk (0x1000UL) /*!< PPARC12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC13_Pos (13UL) /*!< PPARC13 (Bit 13) */ - #define R_PSCU_PPARC_PPARC13_Msk (0x2000UL) /*!< PPARC13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC15_Pos (15UL) /*!< PPARC15 (Bit 15) */ - #define R_PSCU_PPARC_PPARC15_Msk (0x8000UL) /*!< PPARC15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC16_Pos (16UL) /*!< PPARC16 (Bit 16) */ - #define R_PSCU_PPARC_PPARC16_Msk (0x10000UL) /*!< PPARC16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC26_Pos (26UL) /*!< PPARC26 (Bit 26) */ - #define R_PSCU_PPARC_PPARC26_Msk (0x4000000UL) /*!< PPARC26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC27_Pos (27UL) /*!< PPARC27 (Bit 27) */ - #define R_PSCU_PPARC_PPARC27_Msk (0x8000000UL) /*!< PPARC27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC31_Pos (31UL) /*!< PPARC31 (Bit 31) */ - #define R_PSCU_PPARC_PPARC31_Msk (0x80000000UL) /*!< PPARC31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARC_PPARC_Pos (0UL) /*!< PPARC (Bit 0) */ + #define R_PSCU_PPARC_PPARC_Msk (0x1UL) /*!< PPARC (Bitfield-Mask: 0x01) */ /* ========================================================= PPARD ========================================================= */ - #define R_PSCU_PPARD_PPARD4_Pos (4UL) /*!< PPARD4 (Bit 4) */ - #define R_PSCU_PPARD_PPARD4_Msk (0x10UL) /*!< PPARD4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD5_Pos (5UL) /*!< PPARD5 (Bit 5) */ - #define R_PSCU_PPARD_PPARD5_Msk (0x20UL) /*!< PPARD5 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD11_Pos (11UL) /*!< PPARD11 (Bit 11) */ - #define R_PSCU_PPARD_PPARD11_Msk (0x800UL) /*!< PPARD11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD12_Pos (12UL) /*!< PPARD12 (Bit 12) */ - #define R_PSCU_PPARD_PPARD12_Msk (0x1000UL) /*!< PPARD12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD13_Pos (13UL) /*!< PPARD13 (Bit 13) */ - #define R_PSCU_PPARD_PPARD13_Msk (0x2000UL) /*!< PPARD13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD14_Pos (14UL) /*!< PPARD14 (Bit 14) */ - #define R_PSCU_PPARD_PPARD14_Msk (0x4000UL) /*!< PPARD14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD15_Pos (15UL) /*!< PPARD15 (Bit 15) */ - #define R_PSCU_PPARD_PPARD15_Msk (0x8000UL) /*!< PPARD15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD16_Pos (16UL) /*!< PPARD16 (Bit 16) */ - #define R_PSCU_PPARD_PPARD16_Msk (0x10000UL) /*!< PPARD16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD20_Pos (20UL) /*!< PPARD20 (Bit 20) */ - #define R_PSCU_PPARD_PPARD20_Msk (0x100000UL) /*!< PPARD20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD22_Pos (22UL) /*!< PPARD22 (Bit 22) */ - #define R_PSCU_PPARD_PPARD22_Msk (0x400000UL) /*!< PPARD22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD27_Pos (27UL) /*!< PPARD27 (Bit 27) */ - #define R_PSCU_PPARD_PPARD27_Msk (0x8000000UL) /*!< PPARD27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD28_Pos (28UL) /*!< PPARD28 (Bit 28) */ - #define R_PSCU_PPARD_PPARD28_Msk (0x10000000UL) /*!< PPARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARD_PPARD_Pos (0UL) /*!< PPARD (Bit 0) */ + #define R_PSCU_PPARD_PPARD_Msk (0x1UL) /*!< PPARD (Bitfield-Mask: 0x01) */ /* ========================================================= PPARE ========================================================= */ - #define R_PSCU_PPARE_PPARE1_Pos (1UL) /*!< PPARE1 (Bit 1) */ - #define R_PSCU_PPARE_PPARE1_Msk (0x2UL) /*!< PPARE1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE2_Pos (2UL) /*!< PPARE2 (Bit 2) */ - #define R_PSCU_PPARE_PPARE2_Msk (0x4UL) /*!< PPARE2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE3_Pos (3UL) /*!< PPARE3 (Bit 3) */ - #define R_PSCU_PPARE_PPARE3_Msk (0x8UL) /*!< PPARE3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE8_Pos (8UL) /*!< PPARE8 (Bit 8) */ - #define R_PSCU_PPARE_PPARE8_Msk (0x100UL) /*!< PPARE8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE9_Pos (9UL) /*!< PPARE9 (Bit 9) */ - #define R_PSCU_PPARE_PPARE9_Msk (0x200UL) /*!< PPARE9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE18_Pos (18UL) /*!< PPARE18 (Bit 18) */ - #define R_PSCU_PPARE_PPARE18_Msk (0x40000UL) /*!< PPARE18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE19_Pos (19UL) /*!< PPARE19 (Bit 19) */ - #define R_PSCU_PPARE_PPARE19_Msk (0x80000UL) /*!< PPARE19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE20_Pos (20UL) /*!< PPARE20 (Bit 20) */ - #define R_PSCU_PPARE_PPARE20_Msk (0x100000UL) /*!< PPARE20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE21_Pos (21UL) /*!< PPARE21 (Bit 21) */ - #define R_PSCU_PPARE_PPARE21_Msk (0x200000UL) /*!< PPARE21 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE22_Pos (22UL) /*!< PPARE22 (Bit 22) */ - #define R_PSCU_PPARE_PPARE22_Msk (0x400000UL) /*!< PPARE22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE23_Pos (23UL) /*!< PPARE23 (Bit 23) */ - #define R_PSCU_PPARE_PPARE23_Msk (0x800000UL) /*!< PPARE23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE24_Pos (24UL) /*!< PPARE24 (Bit 24) */ - #define R_PSCU_PPARE_PPARE24_Msk (0x1000000UL) /*!< PPARE24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE25_Pos (25UL) /*!< PPARE25 (Bit 25) */ - #define R_PSCU_PPARE_PPARE25_Msk (0x2000000UL) /*!< PPARE25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE26_Pos (26UL) /*!< PPARE26 (Bit 26) */ - #define R_PSCU_PPARE_PPARE26_Msk (0x4000000UL) /*!< PPARE26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE27_Pos (27UL) /*!< PPARE27 (Bit 27) */ - #define R_PSCU_PPARE_PPARE27_Msk (0x8000000UL) /*!< PPARE27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE28_Pos (28UL) /*!< PPARE28 (Bit 28) */ - #define R_PSCU_PPARE_PPARE28_Msk (0x10000000UL) /*!< PPARE28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE29_Pos (29UL) /*!< PPARE29 (Bit 29) */ - #define R_PSCU_PPARE_PPARE29_Msk (0x20000000UL) /*!< PPARE29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE30_Pos (30UL) /*!< PPARE30 (Bit 30) */ - #define R_PSCU_PPARE_PPARE30_Msk (0x40000000UL) /*!< PPARE30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE31_Pos (31UL) /*!< PPARE31 (Bit 31) */ - #define R_PSCU_PPARE_PPARE31_Msk (0x80000000UL) /*!< PPARE31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE_Pos (0UL) /*!< PPARE (Bit 0) */ + #define R_PSCU_PPARE_PPARE_Msk (0x1UL) /*!< PPARE (Bitfield-Mask: 0x01) */ /* ========================================================= MSPAR ========================================================= */ - #define R_PSCU_MSPAR_MSPAR31_Pos (31UL) /*!< MSPAR31 (Bit 31) */ - #define R_PSCU_MSPAR_MSPAR31_Msk (0x80000000UL) /*!< MSPAR31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSPAR_MSPAR_Pos (0UL) /*!< MSPAR (Bit 0) */ + #define R_PSCU_MSPAR_MSPAR_Msk (0x1UL) /*!< MSPAR (Bitfield-Mask: 0x01) */ /* ======================================================= CFSAMONA ======================================================== */ - #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ - #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ /* ======================================================== DFSAMON ======================================================== */ - #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ - #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ /* ======================================================== DLMMON ========================================================= */ - #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ - #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ /* =========================================================================================================================== */ /* ================ R_BUS ================ */ @@ -32494,6 +32609,9 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -32975,6 +33093,11 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -33418,36 +33541,58 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ====================================================== PERFCOUNT2 ======================================================= */ #define R_DRW_PERFCOUNT2_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ #define R_DRW_PERFCOUNT2_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DBWER ========================================================= */ + #define R_DRW_DBWER_BWE_Pos (2UL) /*!< BWE (Bit 2) */ + #define R_DRW_DBWER_BWE_Msk (0x4UL) /*!< BWE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DTC ================ */ /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -34672,10 +34817,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -35326,6 +35467,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ /* ========================================================= BSTE ========================================================== */ #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ @@ -35341,6 +35484,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ /* ========================================================== BIE ========================================================== */ #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ @@ -35356,6 +35501,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ /* ========================================================= BSTFC ========================================================= */ #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ @@ -35371,6 +35518,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ /* ========================================================= NTST ========================================================== */ #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ @@ -35573,6 +35722,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT1 ========================================================= */ @@ -35584,6 +35737,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT2 ========================================================= */ @@ -35595,6 +35752,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT3 ========================================================= */ @@ -35606,6 +35767,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ @@ -35619,6 +35784,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================= SDCTPIDL ======================================================== */ @@ -35680,6 +35849,13 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ /* ======================================================== BITCNT ========================================================= */ #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ @@ -35770,10 +35946,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* =========================================================================================================================== */ /* ======================================================== PCNTR1 ========================================================= */ - #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ - #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ /* ========================================================== PDR ========================================================== */ #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ @@ -35781,10 +35957,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ /* ======================================================== PCNTR2 ========================================================= */ - #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ - #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ /* ========================================================= PIDR ========================================================== */ #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ @@ -35792,10 +35968,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ /* ======================================================== PCNTR3 ========================================================= */ - #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ - #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ /* ========================================================= POSR ========================================================== */ #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ @@ -35803,10 +35979,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ /* ======================================================== PCNTR4 ========================================================= */ - #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ - #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ /* ========================================================= EOSR ========================================================== */ #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ @@ -35825,6 +36001,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================== PFENET ========================================================= */ #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ /* ========================================================= PWPR ========================================================== */ #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ @@ -35841,20 +36019,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -37316,8 +37484,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_SYSTEM_RSTSR1_CMRF_Msk (0x4000UL) /*!< CMRF (Bitfield-Mask: 0x01) */ #define R_SYSTEM_RSTSR1_WDT1RF_Pos (17UL) /*!< WDT1RF (Bit 17) */ #define R_SYSTEM_RSTSR1_WDT1RF_Msk (0x20000UL) /*!< WDT1RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_CLU1RF_Pos (20UL) /*!< CLU1RF (Bit 20) */ - #define R_SYSTEM_RSTSR1_CLU1RF_Msk (0x100000UL) /*!< CLU1RF (Bitfield-Mask: 0x01) */ #define R_SYSTEM_RSTSR1_LM1RF_Pos (21UL) /*!< LM1RF (Bit 21) */ #define R_SYSTEM_RSTSR1_LM1RF_Msk (0x200000UL) /*!< LM1RF (Bitfield-Mask: 0x01) */ #define R_SYSTEM_RSTSR1_NWRF_Pos (22UL) /*!< NWRF (Bit 22) */ @@ -37832,10 +37998,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_SYSTEM_SYRSTMSK0_BUSMASK_Pos (7UL) /*!< BUSMASK (Bit 7) */ #define R_SYSTEM_SYRSTMSK0_BUSMASK_Msk (0x80UL) /*!< BUSMASK (Bitfield-Mask: 0x01) */ /* ======================================================= SYRSTMSK1 ======================================================= */ - #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Pos (1UL) /*!< WDT1MASK (Bit 1) */ - #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Msk (0x2UL) /*!< WDT1MASK (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SYRSTMSK1_CLUP1MASK_Pos (4UL) /*!< CLUP1MASK (Bit 4) */ - #define R_SYSTEM_SYRSTMSK1_CLUP1MASK_Msk (0x10UL) /*!< CLUP1MASK (Bitfield-Mask: 0x01) */ #define R_SYSTEM_SYRSTMSK1_LM1MASK_Pos (5UL) /*!< LM1MASK (Bit 5) */ #define R_SYSTEM_SYRSTMSK1_LM1MASK_Msk (0x20UL) /*!< LM1MASK (Bitfield-Mask: 0x01) */ #define R_SYSTEM_SYRSTMSK1_NWMASK_Pos (7UL) /*!< NWMASK (Bit 7) */ @@ -38998,6 +39160,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ @@ -39021,6 +39185,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ @@ -39044,18 +39210,39 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================== ICUSARI ======================================================== */ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARA ======================================================== */ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARB ======================================================== */ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ /* ======================================================= MMPUSARA ======================================================== */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ /* ======================================================= DMACCHSAR ======================================================= */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8M1AH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8M1AH.h index 5b839e874..b03b96cd8 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8M1AH.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8M1AH.h @@ -47,8 +47,8 @@ extern "C" { #define __ICACHE_PRESENT 1 /*!< Instruction Cache present */ #define __DCACHE_PRESENT 1 /*!< Data Cache present */ #define __SAUREGION_PRESENT 1 /*!< SAU region present */ - #define __PMU_PRESENT 0 /*!< PMU present */ - #define __PMU_NUM_EVENTCNT 0 /*!< PMU Event Counters */ + #define __PMU_PRESENT 1 /*!< PMU present */ + #define __PMU_NUM_EVENTCNT 8 /*!< PMU Event Counters */ /** @} */ /* End of group Configuration_of_CMSIS */ @@ -472,24 +472,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -706,27 +723,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1361,7 +1364,7 @@ typedef struct struct { __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry enable */ __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ } ID_b; @@ -1418,7 +1421,7 @@ typedef struct struct { __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ } ID_b; @@ -1643,7 +1646,7 @@ typedef struct } R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) */ typedef struct { @@ -4063,32 +4066,42 @@ typedef struct /*!< (@ 0x40204000) R_PSCU Structure union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ - - struct - { - uint32_t : 4; - __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C Bus Interface 2 Security Attribution */ - uint32_t : 3; - __IOM uint32_t PSARB8 : 1; /*!< [8..8] I2C Bus Interface 1 Security Attribution */ - __IOM uint32_t PSARB9 : 1; /*!< [9..9] I2C Bus Interface 0 Security Attribution */ - uint32_t : 1; - __IOM uint32_t PSARB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface 0 Security Attribution */ - __IOM uint32_t PSARB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface 0 Security Attribution */ - uint32_t : 2; - __IOM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0 Controller Security Attribution */ - __IOM uint32_t PSARB16 : 1; /*!< [16..16] Octa Memory Controller Security Attribution */ - uint32_t : 1; - __IOM uint32_t PSARB18 : 1; /*!< [18..18] Serial Peripheral Interface 1 Security Attribution */ - __IOM uint32_t PSARB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Security Attribution */ - uint32_t : 2; - __IOM uint32_t PSARB22 : 1; /*!< [22..22] Serial Communication Interface 9 Security Attribution */ - uint32_t : 4; - __IOM uint32_t PSARB27 : 1; /*!< [27..27] Serial Communication Interface 4 Security Attribution */ - __IOM uint32_t PSARB28 : 1; /*!< [28..28] Serial Communication Interface 3 Security Attribution */ - __IOM uint32_t PSARB29 : 1; /*!< [29..29] Serial Communication Interface 2 Security Attribution */ - __IOM uint32_t PSARB30 : 1; /*!< [30..30] Serial Communication Interface 1 Security Attribution */ - __IOM uint32_t PSARB31 : 1; /*!< [31..31] Serial Communication Interface 0 Security Attribution */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + __IOM uint32_t PSARB0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARB1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARB4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARB6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARB10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARB11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARB13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARB14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARB15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARB16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARB17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARB18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARB20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARB21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARB22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ } PSARB_b; }; @@ -4098,86 +4111,120 @@ typedef struct /*!< (@ 0x40204000) R_PSCU Structure struct { - __IOM uint32_t PSARC0 : 1; /*!< [0..0] Clock Frequency Accuracy Measurement Circuit Security - * Attribution */ - __IOM uint32_t PSARC1 : 1; /*!< [1..1] Cyclic Redundancy Check Calculator Security Attribution */ - uint32_t : 5; - __IOM uint32_t PSARC7 : 1; /*!< [7..7] Serial Sound Interface Enhanced (channel 1) Security - * Attribution */ - __IOM uint32_t PSARC8 : 1; /*!< [8..8] Serial Sound Interface Enhanced (channel 0) Security - * Attribution */ - uint32_t : 2; - __IOM uint32_t PSARC11 : 1; /*!< [11..11] Secure Digital Host IF 1 Security Attribution */ - __IOM uint32_t PSARC12 : 1; /*!< [12..12] Secure Digital Host IF 0 Security Attribution */ - __IOM uint32_t PSARC13 : 1; /*!< [13..13] Data Operation Circuit Security Attribution */ - uint32_t : 1; - __IOM uint32_t PSARC15 : 1; /*!< [15..15] Graph-ic(GLCDC,MIPI,DRW,JPEG) Security Attribution */ - __IOM uint32_t PSARC16 : 1; /*!< [16..16] CEU Security Attribution */ - uint32_t : 9; - __IOM uint32_t PSARC26 : 1; /*!< [26..26] Controller Area Network with Flexible Data-Rate 1 Security - * Attribution */ - __IOM uint32_t PSARC27 : 1; /*!< [27..27] Controller Area Network with Flexible Data-Rate 0 Security - * Attribution */ - uint32_t : 3; - __IOM uint32_t PSARC31 : 1; /*!< [31..31] SHIP Security Attribution */ + __IOM uint32_t PSARC0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARC2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARC3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARC4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARC5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARC6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARC7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARC8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARC9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARC10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARC11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARC12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARC14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARC15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARC16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARC17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARC18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARC19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARC20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARC21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARC22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARC23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARC24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARC25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARC26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARC27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARC28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARC29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARC30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARC31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ } PSARC_b; }; union { - __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ - - struct - { - uint32_t : 4; - __IOM uint32_t PSARD4 : 1; /*!< [4..4] Asynchronous General Purpose Timer 1 Security Attribution */ - __IOM uint32_t PSARD5 : 1; /*!< [5..5] Asynchronous General Purpose Timer 0 Security Attribution */ - uint32_t : 5; - __IOM uint32_t PSARD11 : 1; /*!< [11..11] Port Output Enable for GPT Group 3 Security Attribution */ - __IOM uint32_t PSARD12 : 1; /*!< [12..12] Port Output Enable for GPT Group 2 Security Attribution */ - __IOM uint32_t PSARD13 : 1; /*!< [13..13] Port Output Enable for GPT Group 1 Security Attribution */ - __IOM uint32_t PSARD14 : 1; /*!< [14..14] Port Output Enable for GPT Group 0 Security Attribution */ - __IOM uint32_t PSARD15 : 1; /*!< [15..15] 12-Bit A/D 1 Converter Security Attribution */ - __IOM uint32_t PSARD16 : 1; /*!< [16..16] 12-Bit A/D 0 Converter Security Attribution */ - uint32_t : 3; - __IOM uint32_t PSARD20 : 1; /*!< [20..20] 12-Bit D/A Converter Security Attribution */ - uint32_t : 1; - __IOM uint32_t PSARD22 : 1; /*!< [22..22] Temperature Sensor Security Attribution */ - uint32_t : 4; - __IOM uint32_t PSARD27 : 1; /*!< [27..27] High speed analog Comparator 1 Security Attribution */ - __IOM uint32_t PSARD28 : 1; /*!< [28..28] High speed analog Comparator 0 Security Attribution */ - uint32_t : 3; + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARD4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARD5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARD6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARD7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARD8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARD9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARD10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARD11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARD17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARD18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARD19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARD21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARD22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARD23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARD24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARD25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARD29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARD30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARD31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ } PSARD_b; }; union { - __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ - - struct - { - uint32_t : 1; - __IOM uint32_t PSARE1 : 1; /*!< [1..1] WDT0 Security Attribution */ - __IOM uint32_t PSARE2 : 1; /*!< [2..2] Independent Watchdog Timer Security Attribution */ - __IOM uint32_t PSARE3 : 1; /*!< [3..3] Real Time Clock Security Attribution */ - uint32_t : 4; - __IOM uint32_t PSARE8 : 1; /*!< [8..8] ULPT1 Security Attribution */ - __IOM uint32_t PSARE9 : 1; /*!< [9..9] ULPT0 Security Attribution */ - uint32_t : 8; - __IOM uint32_t PSARE18 : 1; /*!< [18..18] General PWM Timer channel13 Security Attribution */ - __IOM uint32_t PSARE19 : 1; /*!< [19..19] General PWM Timer channel12 Security Attribution */ - __IOM uint32_t PSARE20 : 1; /*!< [20..20] General PWM Timer channel11 Security Attribution */ - __IOM uint32_t PSARE21 : 1; /*!< [21..21] General PWM Timer channel10 Security Attribution */ - __IOM uint32_t PSARE22 : 1; /*!< [22..22] General PWM Timer channel9 Security Attribution */ - __IOM uint32_t PSARE23 : 1; /*!< [23..23] General PWM Timer channel8 Security Attribution */ - __IOM uint32_t PSARE24 : 1; /*!< [24..24] General PWM Timer channel7 Security Attribution */ - __IOM uint32_t PSARE25 : 1; /*!< [25..25] General PWM Timer channel6 Security Attribution */ - __IOM uint32_t PSARE26 : 1; /*!< [26..26] General PWM Timer channel5 Security Attribution */ - __IOM uint32_t PSARE27 : 1; /*!< [27..27] General PWM Timer channel4 Security Attribution */ - __IOM uint32_t PSARE28 : 1; /*!< [28..28] General PWM Timer channel3 Security Attribution */ - __IOM uint32_t PSARE29 : 1; /*!< [29..29] General PWM Timer channel2 Security Attribution */ - __IOM uint32_t PSARE30 : 1; /*!< [30..30] General PWM Timer channel1 Security Attribution */ - __IOM uint32_t PSARE31 : 1; /*!< [31..31] General PWM Timer channel0 Security Attribution */ + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARE3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARE4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARE5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARE6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARE7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARE8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARE9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARE10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARE11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARE12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARE13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARE14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARE16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARE17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARE18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARE19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARE20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARE21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARE22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ } PSARE_b; }; @@ -4187,50 +4234,80 @@ typedef struct /*!< (@ 0x40204000) R_PSCU Structure struct { - __IOM uint32_t MSSAR0 : 1; /*!< [0..0] SRAM0 Clock Stop Security Attribution */ - __IOM uint32_t MSSAR1 : 1; /*!< [1..1] SRAM1 Clock Stop Security Attribution */ - uint32_t : 9; - __IOM uint32_t MSSAR11 : 1; /*!< [11..11] CTCM0 Security Attribution */ - uint32_t : 1; - __IOM uint32_t MSSAR13 : 1; /*!< [13..13] STCM0 Security Attribution */ - uint32_t : 1; - __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Standby RAM Clock Stop Security Attribution */ - uint32_t : 6; - __IOM uint32_t MSSAR22 : 1; /*!< [22..22] DMAC0/DTC0 Clock Stop Security Attribution */ - uint32_t : 8; - __IOM uint32_t MSSAR31 : 1; /*!< [31..31] ELC clock stop Security Attribution */ + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] Module stop security attribution bit 0 */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] Module stop security attribution bit 1 */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] Module stop security attribution bit 2 */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] Module stop security attribution bit 3 */ + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] Module stop security attribution bit 4 */ + __IOM uint32_t MSSAR5 : 1; /*!< [5..5] Module stop security attribution bit 5 */ + __IOM uint32_t MSSAR6 : 1; /*!< [6..6] Module stop security attribution bit 6 */ + __IOM uint32_t MSSAR7 : 1; /*!< [7..7] Module stop security attribution bit 7 */ + __IOM uint32_t MSSAR8 : 1; /*!< [8..8] Module stop security attribution bit 8 */ + __IOM uint32_t MSSAR9 : 1; /*!< [9..9] Module stop security attribution bit 9 */ + __IOM uint32_t MSSAR10 : 1; /*!< [10..10] Module stop security attribution bit 10 */ + __IOM uint32_t MSSAR11 : 1; /*!< [11..11] Module stop security attribution bit 11 */ + __IOM uint32_t MSSAR12 : 1; /*!< [12..12] Module stop security attribution bit 12 */ + __IOM uint32_t MSSAR13 : 1; /*!< [13..13] Module stop security attribution bit 13 */ + __IOM uint32_t MSSAR14 : 1; /*!< [14..14] Module stop security attribution bit 14 */ + __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Module stop security attribution bit 15 */ + __IOM uint32_t MSSAR16 : 1; /*!< [16..16] Module stop security attribution bit 16 */ + __IOM uint32_t MSSAR17 : 1; /*!< [17..17] Module stop security attribution bit 17 */ + __IOM uint32_t MSSAR18 : 1; /*!< [18..18] Module stop security attribution bit 18 */ + __IOM uint32_t MSSAR19 : 1; /*!< [19..19] Module stop security attribution bit 19 */ + __IOM uint32_t MSSAR20 : 1; /*!< [20..20] Module stop security attribution bit 20 */ + __IOM uint32_t MSSAR21 : 1; /*!< [21..21] Module stop security attribution bit 21 */ + __IOM uint32_t MSSAR22 : 1; /*!< [22..22] Module stop security attribution bit 22 */ + __IOM uint32_t MSSAR23 : 1; /*!< [23..23] Module stop security attribution bit 23 */ + __IOM uint32_t MSSAR24 : 1; /*!< [24..24] Module stop security attribution bit 24 */ + __IOM uint32_t MSSAR25 : 1; /*!< [25..25] Module stop security attribution bit 25 */ + __IOM uint32_t MSSAR26 : 1; /*!< [26..26] Module stop security attribution bit 26 */ + __IOM uint32_t MSSAR27 : 1; /*!< [27..27] Module stop security attribution bit 27 */ + __IOM uint32_t MSSAR28 : 1; /*!< [28..28] Module stop security attribution bit 28 */ + __IOM uint32_t MSSAR29 : 1; /*!< [29..29] Module stop security attribution bit 29 */ + __IOM uint32_t MSSAR30 : 1; /*!< [30..30] Module stop security attribution bit 30 */ + __IOM uint32_t MSSAR31 : 1; /*!< [31..31] Module stop security attribution bit 31 */ } MSSAR_b; }; __IM uint32_t RESERVED1; union { - __IOM uint32_t PPARB; /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B */ - - struct - { - uint32_t : 4; - __IOM uint32_t PPARB4 : 1; /*!< [4..4] I3C Bus Interface 2 Privilege Attribution */ - uint32_t : 3; - __IOM uint32_t PPARB8 : 1; /*!< [8..8] I2C Bus Interface 1 Privilege Attribution */ - __IOM uint32_t PPARB9 : 1; /*!< [9..9] I2C Bus Interface 0 Privilege Attribution */ - uint32_t : 1; - __IOM uint32_t PPARB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface 0 Privilege Attribution */ - __IOM uint32_t PPARB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface 0 Privilege Attribution */ - uint32_t : 2; - __IOM uint32_t PPARB15 : 1; /*!< [15..15] ETHER0/EDMAC0 Controller Privilege Attribution */ - __IOM uint32_t PPARB16 : 1; /*!< [16..16] Octa Memory Controller Privilege Attribution */ - uint32_t : 1; - __IOM uint32_t PPARB18 : 1; /*!< [18..18] Serial Peripheral Interface 1 Privilege Attribution */ - __IOM uint32_t PPARB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Privilege Attribution */ - uint32_t : 2; - __IOM uint32_t PPARB22 : 1; /*!< [22..22] Serial Communication Interface 9 Privilege Attribution */ - uint32_t : 4; - __IOM uint32_t PPARB27 : 1; /*!< [27..27] Serial Communication Interface 4 Privilege Attribution */ - __IOM uint32_t PPARB28 : 1; /*!< [28..28] Serial Communication Interface 3 Privilege Attribution */ - __IOM uint32_t PPARB29 : 1; /*!< [29..29] Serial Communication Interface 2 Privilege Attribution */ - __IOM uint32_t PPARB30 : 1; /*!< [30..30] Serial Communication Interface 1 Privilege Attribution */ - __IOM uint32_t PPARB31 : 1; /*!< [31..31] Serial Communication Interface 0 Privilege Attribution */ + __IOM uint32_t PPARB; /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B */ + + struct + { + __IOM uint32_t PPARB0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARB1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARB2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARB3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARB4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARB5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARB6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARB7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARB8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARB9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARB10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARB11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARB12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARB13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARB14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARB15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARB16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARB17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARB18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARB19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARB20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARB21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARB22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARB23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARB24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARB25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARB26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARB27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARB28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARB29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARB30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARB31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ } PPARB_b; }; @@ -4240,104 +4317,167 @@ typedef struct /*!< (@ 0x40204000) R_PSCU Structure struct { - __IOM uint32_t PPARC0 : 1; /*!< [0..0] Clock Frequency Accuracy Measurement Circuit Privilege - * Attribution */ - __IOM uint32_t PPARC1 : 1; /*!< [1..1] Cyclic Redundancy Check Calculator Privilege Attribution */ - uint32_t : 5; - __IOM uint32_t PPARC7 : 1; /*!< [7..7] Serial Sound Interface Enhanced (channel 1) Privilege - * Attribution */ - __IOM uint32_t PPARC8 : 1; /*!< [8..8] Serial Sound Interface Enhanced (channel 0) Privilege - * Attribution */ - uint32_t : 2; - __IOM uint32_t PPARC11 : 1; /*!< [11..11] Privilege Digital Host IF 1 Privilege Attribution */ - __IOM uint32_t PPARC12 : 1; /*!< [12..12] Privilege Digital Host IF 0 Privilege Attribution */ - __IOM uint32_t PPARC13 : 1; /*!< [13..13] Data Operation Circuit Privilege Attribution */ - uint32_t : 1; - __IOM uint32_t PPARC15 : 1; /*!< [15..15] Graph-ic(GLCDC,MIPI,DRW,JPEG) Privilege Attribution */ - __IOM uint32_t PPARC16 : 1; /*!< [16..16] CEU Privilege Attribution */ - uint32_t : 9; - __IOM uint32_t PPARC26 : 1; /*!< [26..26] Controller Area Network with Flexible Data-Rate 1 Privilege - * Attribution */ - __IOM uint32_t PPARC27 : 1; /*!< [27..27] Controller Area Network with Flexible Data-Rate 0 Privilege - * Attribution */ - uint32_t : 3; - __IOM uint32_t PPARC31 : 1; /*!< [31..31] SHIP Privilege Attribution */ + __IOM uint32_t PPARC0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARC1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARC2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARC3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARC4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARC5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARC6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARC7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARC8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARC9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARC10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARC11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARC12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARC13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARC14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARC15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARC16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARC17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARC18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARC19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARC20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARC21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARC22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARC23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARC24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARC25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARC26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARC27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARC28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARC29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARC30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARC31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ } PPARC_b; }; union { - __IOM uint32_t PPARD; /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D */ - - struct - { - uint32_t : 4; - __IOM uint32_t PPARD4 : 1; /*!< [4..4] Asynchronous General Purpose Timer 1 Privilege Attribution */ - __IOM uint32_t PPARD5 : 1; /*!< [5..5] Asynchronous General Purpose Timer 0 Privilege Attribution */ - uint32_t : 5; - __IOM uint32_t PPARD11 : 1; /*!< [11..11] Port Output Enable for GPT Group 3 Privilege Attribution */ - __IOM uint32_t PPARD12 : 1; /*!< [12..12] Port Output Enable for GPT Group 2 Privilege Attribution */ - __IOM uint32_t PPARD13 : 1; /*!< [13..13] Port Output Enable for GPT Group 1 Privilege Attribution */ - __IOM uint32_t PPARD14 : 1; /*!< [14..14] Port Output Enable for GPT Group 0 Privilege Attribution */ - __IOM uint32_t PPARD15 : 1; /*!< [15..15] 12-Bit A/D 1 Converter Privilege Attribution */ - __IOM uint32_t PPARD16 : 1; /*!< [16..16] 12-Bit A/D 0 Converter Privilege Attribution */ - uint32_t : 3; - __IOM uint32_t PPARD20 : 1; /*!< [20..20] 12-Bit D/A Converter Privilege Attribution */ - uint32_t : 1; - __IOM uint32_t PPARD22 : 1; /*!< [22..22] Temperature Sensor Privilege Attribution */ - uint32_t : 4; - __IOM uint32_t PPARD27 : 1; /*!< [27..27] High speed analog Comparator 1 Privilege Attribution */ - __IOM uint32_t PPARD28 : 1; /*!< [28..28] High speed analog Comparator 0 Privilege Attribution */ - uint32_t : 3; + __IOM uint32_t PPARD; /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D */ + + struct + { + __IOM uint32_t PPARD0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARD1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARD2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARD3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARD4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARD5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARD6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARD7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARD8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARD9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARD10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARD11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARD12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARD13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARD14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARD15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARD16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARD17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARD18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARD19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARD20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARD21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARD22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARD23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARD24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARD25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARD26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARD27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARD28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARD29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARD30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARD31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ } PPARD_b; }; union { - __IOM uint32_t PPARE; /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E */ - - struct - { - uint32_t : 1; - __IOM uint32_t PPARE1 : 1; /*!< [1..1] Watchdog Timer0 Privilege Attribution */ - __IOM uint32_t PPARE2 : 1; /*!< [2..2] Independent Watchdog Timer Privilege Attribution */ - __IOM uint32_t PPARE3 : 1; /*!< [3..3] Real Time Clock Privilege Attribution */ - uint32_t : 4; - __IOM uint32_t PPARE8 : 1; /*!< [8..8] ULPT1 Privilege Attribution */ - __IOM uint32_t PPARE9 : 1; /*!< [9..9] ULPT0 Privilege Attribution */ - uint32_t : 8; - __IOM uint32_t PPARE18 : 1; /*!< [18..18] General PWM Timer channel13 Privilege Attribution */ - __IOM uint32_t PPARE19 : 1; /*!< [19..19] General PWM Timer channel12 Privilege Attribution */ - __IOM uint32_t PPARE20 : 1; /*!< [20..20] General PWM Timer channel11 Privilege Attribution */ - __IOM uint32_t PPARE21 : 1; /*!< [21..21] General PWM Timer channel10 Privilege Attribution */ - __IOM uint32_t PPARE22 : 1; /*!< [22..22] General PWM Timer channel9 Privilege Attribution */ - __IOM uint32_t PPARE23 : 1; /*!< [23..23] General PWM Timer channel8 Privilege Attribution */ - __IOM uint32_t PPARE24 : 1; /*!< [24..24] General PWM Timer channel7 Privilege Attribution */ - __IOM uint32_t PPARE25 : 1; /*!< [25..25] General PWM Timer channel6 Privilege Attribution */ - __IOM uint32_t PPARE26 : 1; /*!< [26..26] General PWM Timer channel5 Privilege Attribution */ - __IOM uint32_t PPARE27 : 1; /*!< [27..27] General PWM Timer channel4 Privilege Attribution */ - __IOM uint32_t PPARE28 : 1; /*!< [28..28] General PWM Timer channel3 Privilege Attribution */ - __IOM uint32_t PPARE29 : 1; /*!< [29..29] General PWM Timer channel2 Privilege Attribution */ - __IOM uint32_t PPARE30 : 1; /*!< [30..30] General PWM Timer channel1 Privilege Attribution */ - __IOM uint32_t PPARE31 : 1; /*!< [31..31] General PWM Timer channel0 Privilege Attribution */ + __IOM uint32_t PPARE; /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E */ + + struct + { + __IOM uint32_t PPARE0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARE1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARE2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARE3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARE4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARE5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARE6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARE7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARE8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARE9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARE10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARE11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARE12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARE13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARE14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARE15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARE16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARE17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARE18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARE19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARE20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARE21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARE22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARE23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARE24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARE25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARE26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARE27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARE28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARE29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARE30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARE31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ } PPARE_b; }; union { - __IOM uint32_t MSPAR; /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register */ - - struct - { - uint32_t : 31; - __IOM uint32_t MSPAR31 : 1; /*!< [31..31] ELC clock stop Privilege Attribution */ + __IOM uint32_t MSPAR; /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register */ + + struct + { + __IOM uint32_t MSPAR0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t MSPAR1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t MSPAR2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t MSPAR3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t MSPAR4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t MSPAR5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t MSPAR6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t MSPAR7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t MSPAR8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t MSPAR9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t MSPAR10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t MSPAR11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t MSPAR12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t MSPAR13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t MSPAR14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t MSPAR15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t MSPAR16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t MSPAR17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t MSPAR18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t MSPAR19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t MSPAR20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t MSPAR21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t MSPAR22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t MSPAR23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t MSPAR24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t MSPAR25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t MSPAR26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t MSPAR27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t MSPAR28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t MSPAR29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t MSPAR30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t MSPAR31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ } MSPAR_b; }; union { - __IM uint32_t CFSAMONA; /*!< (@ 0x00000030) Code Flash Security Attribution Monitor Register - * A */ + __IM uint32_t CFSAMONA; /*!< (@ 0x00000030) Code Flash Security Attribution Monitor Register */ struct { @@ -4458,9 +4598,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -4468,16 +4621,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -5559,7 +5712,23 @@ typedef struct /*!< (@ 0x4000A800) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -5575,7 +5744,7 @@ typedef struct /*!< (@ 0x4000A800) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -5873,11 +6042,22 @@ typedef struct /*!< (@ 0x4000AC00) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -5889,7 +6069,7 @@ typedef struct /*!< (@ 0x4000AC00) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -5912,15 +6092,34 @@ typedef struct /*!< (@ 0x4000AC00) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -5935,7 +6134,44 @@ typedef struct /*!< (@ 0x4000AC00) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -8596,47 +8832,43 @@ typedef struct /*!< (@ 0x40323F00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40212000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40212000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -9767,7 +9999,9 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ uint32_t : 3; __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; } BST_b; }; @@ -9788,7 +10022,9 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ uint32_t : 3; __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; } BSTE_b; }; @@ -9809,28 +10045,32 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ uint32_t : 3; __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; } BIE_b; }; union { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ struct { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 11; + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; } BSTFC_b; }; @@ -10113,7 +10353,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT0_b; @@ -10130,7 +10371,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT1_b; @@ -10147,7 +10389,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT2_b; @@ -10164,7 +10407,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT3_b; @@ -10182,7 +10426,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } SVDCT_b; @@ -10332,7 +10577,20 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28[2]; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; union { @@ -10458,9 +10716,7 @@ typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -11129,7 +11385,8 @@ typedef struct /*!< (@ 0x40400D00) R_PMISC Structure { uint8_t : 4; __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ - uint8_t : 3; + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; } PFENET_b; }; __IM uint8_t RESERVED; @@ -11181,14 +11438,16 @@ typedef struct /*!< (@ 0x40202000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -14351,10 +14610,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint32_t WDT1RF : 1; /*!< [17..17] Watchdog Timer1 Reset Detect Flag. NOTE: Writable only * to clear the flag. Confirm the value is 1 and then write * 0. */ - uint32_t : 2; - __IOM uint32_t CLU1RF : 1; /*!< [20..20] CPU1 Lockup Reset Detect Flag. NOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ + uint32_t : 3; __IOM uint32_t LM1RF : 1; /*!< [21..21] Local memory 1 error Reset Detect Flag. NOTE: Writable * only to clear the flag. Confirm the value is 1 and then * write 0. */ @@ -15287,13 +15543,10 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - uint8_t : 1; - __IOM uint8_t WDT1MASK : 1; /*!< [1..1] CPU1 Watchdog timer Reset Mask */ - uint8_t : 2; - __IOM uint8_t CLUP1MASK : 1; /*!< [4..4] CPU1 Lockup Reset Mask */ - __IOM uint8_t LM1MASK : 1; /*!< [5..5] Local memory 1 error Reset Mask */ - uint8_t : 1; - __IOM uint8_t NWMASK : 1; /*!< [7..7] Network Reset Mask */ + uint8_t : 5; + __IOM uint8_t LM1MASK : 1; /*!< [5..5] Local memory 1 error Reset Mask */ + uint8_t : 1; + __IOM uint8_t NWMASK : 1; /*!< [7..7] Network Reset Mask */ } SYRSTMSK1_b; }; __IM uint8_t RESERVED129; @@ -18178,21 +18431,22 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure struct { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 3; - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ } ICUSARE_b; }; @@ -18206,7 +18460,8 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 4; + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ @@ -18217,7 +18472,21 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 17; } ICUSARF_b; }; - __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + uint32_t : 28; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; union { @@ -18271,7 +18540,30 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } BUSSARB_b; }; - __IM uint32_t RESERVED5[10]; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; union { @@ -18296,7 +18588,33 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } MMPUSARB_b; }; - __IM uint32_t RESERVED6[26]; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; union { @@ -18309,7 +18627,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 24; } DMACCHSAR_b; }; - __IM uint32_t RESERVED7[3]; + __IM uint32_t RESERVED9[3]; union { @@ -18321,7 +18639,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[147]; + __IM uint32_t RESERVED10[147]; union { @@ -18350,7 +18668,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 11; } SRAMSABAR1_b; }; - __IM uint32_t RESERVED9[126]; + __IM uint32_t RESERVED11[126]; union { @@ -22164,6 +22482,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_AGTX9_BASE (0x40221900UL + BASE_NS_OFFSET) #define R_FLAD_BASE (0x4011C000UL + BASE_NS_OFFSET) #define R_OFS_DATAFLASH_BASE (0x27030000UL + BASE_NS_OFFSET) + #define R_SCI_B5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI_B6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI_B7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI_B8_BASE (0x40358800UL + BASE_NS_OFFSET) /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -22309,6 +22631,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) #define R_OFS_DATAFLASH ((R_OFS_DATAFLASH_Type *) R_OFS_DATAFLASH_BASE) + #define R_SCI_B5 ((R_SCI_B0_Type *) R_SCI_B5_BASE) + #define R_SCI_B6 ((R_SCI_B0_Type *) R_SCI_B6_BASE) + #define R_SCI_B7 ((R_SCI_B0_Type *) R_SCI_B7_BASE) + #define R_SCI_B8 ((R_SCI_B0_Type *) R_SCI_B8_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -22516,6 +22842,9 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -22580,9 +22909,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -22927,6 +23253,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ @@ -22958,6 +23286,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ @@ -24029,272 +24359,44 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* =========================================================================================================================== */ /* ========================================================= PSARB ========================================================= */ - #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ - #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ - #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ - #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ - #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ - #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ - #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ - #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ - #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ - #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ - #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ - #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ - #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ - #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ - #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ - #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB_Pos (0UL) /*!< PSARB (Bit 0) */ + #define R_PSCU_PSARB_PSARB_Msk (0x1UL) /*!< PSARB (Bitfield-Mask: 0x01) */ /* ========================================================= PSARC ========================================================= */ - #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ - #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ - #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC7_Pos (7UL) /*!< PSARC7 (Bit 7) */ - #define R_PSCU_PSARC_PSARC7_Msk (0x80UL) /*!< PSARC7 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ - #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC11_Pos (11UL) /*!< PSARC11 (Bit 11) */ - #define R_PSCU_PSARC_PSARC11_Msk (0x800UL) /*!< PSARC11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ - #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ - #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC15_Pos (15UL) /*!< PSARC15 (Bit 15) */ - #define R_PSCU_PSARC_PSARC15_Msk (0x8000UL) /*!< PSARC15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC16_Pos (16UL) /*!< PSARC16 (Bit 16) */ - #define R_PSCU_PSARC_PSARC16_Msk (0x10000UL) /*!< PSARC16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC26_Pos (26UL) /*!< PSARC26 (Bit 26) */ - #define R_PSCU_PSARC_PSARC26_Msk (0x4000000UL) /*!< PSARC26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ - #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ - #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC_Pos (0UL) /*!< PSARC (Bit 0) */ + #define R_PSCU_PSARC_PSARC_Msk (0x1UL) /*!< PSARC (Bitfield-Mask: 0x01) */ /* ========================================================= PSARD ========================================================= */ - #define R_PSCU_PSARD_PSARD4_Pos (4UL) /*!< PSARD4 (Bit 4) */ - #define R_PSCU_PSARD_PSARD4_Msk (0x10UL) /*!< PSARD4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD5_Pos (5UL) /*!< PSARD5 (Bit 5) */ - #define R_PSCU_PSARD_PSARD5_Msk (0x20UL) /*!< PSARD5 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ - #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ - #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ - #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ - #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ - #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ - #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ - #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ - #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ - #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ - #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD_Pos (0UL) /*!< PSARD (Bit 0) */ + #define R_PSCU_PSARD_PSARD_Msk (0x1UL) /*!< PSARD (Bitfield-Mask: 0x01) */ /* ========================================================= PSARE ========================================================= */ - #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ - #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ - #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE3_Pos (3UL) /*!< PSARE3 (Bit 3) */ - #define R_PSCU_PSARE_PSARE3_Msk (0x8UL) /*!< PSARE3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE8_Pos (8UL) /*!< PSARE8 (Bit 8) */ - #define R_PSCU_PSARE_PSARE8_Msk (0x100UL) /*!< PSARE8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE9_Pos (9UL) /*!< PSARE9 (Bit 9) */ - #define R_PSCU_PSARE_PSARE9_Msk (0x200UL) /*!< PSARE9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE18_Pos (18UL) /*!< PSARE18 (Bit 18) */ - #define R_PSCU_PSARE_PSARE18_Msk (0x40000UL) /*!< PSARE18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE19_Pos (19UL) /*!< PSARE19 (Bit 19) */ - #define R_PSCU_PSARE_PSARE19_Msk (0x80000UL) /*!< PSARE19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE20_Pos (20UL) /*!< PSARE20 (Bit 20) */ - #define R_PSCU_PSARE_PSARE20_Msk (0x100000UL) /*!< PSARE20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE21_Pos (21UL) /*!< PSARE21 (Bit 21) */ - #define R_PSCU_PSARE_PSARE21_Msk (0x200000UL) /*!< PSARE21 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ - #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ - #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ - #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ - #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ - #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ - #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ - #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ - #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ - #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ - #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE_Pos (0UL) /*!< PSARE (Bit 0) */ + #define R_PSCU_PSARE_PSARE_Msk (0x1UL) /*!< PSARE (Bitfield-Mask: 0x01) */ /* ========================================================= MSSAR ========================================================= */ - #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ - #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ - #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR11_Pos (11UL) /*!< MSSAR11 (Bit 11) */ - #define R_PSCU_MSSAR_MSSAR11_Msk (0x800UL) /*!< MSSAR11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR13_Pos (13UL) /*!< MSSAR13 (Bit 13) */ - #define R_PSCU_MSSAR_MSSAR13_Msk (0x2000UL) /*!< MSSAR13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR15_Pos (15UL) /*!< MSSAR15 (Bit 15) */ - #define R_PSCU_MSSAR_MSSAR15_Msk (0x8000UL) /*!< MSSAR15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR22_Pos (22UL) /*!< MSSAR22 (Bit 22) */ - #define R_PSCU_MSSAR_MSSAR22_Msk (0x400000UL) /*!< MSSAR22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR31_Pos (31UL) /*!< MSSAR31 (Bit 31) */ - #define R_PSCU_MSSAR_MSSAR31_Msk (0x80000000UL) /*!< MSSAR31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR_Pos (0UL) /*!< MSSAR (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR_Msk (0x1UL) /*!< MSSAR (Bitfield-Mask: 0x01) */ /* ========================================================= PPARB ========================================================= */ - #define R_PSCU_PPARB_PPARB4_Pos (4UL) /*!< PPARB4 (Bit 4) */ - #define R_PSCU_PPARB_PPARB4_Msk (0x10UL) /*!< PPARB4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB8_Pos (8UL) /*!< PPARB8 (Bit 8) */ - #define R_PSCU_PPARB_PPARB8_Msk (0x100UL) /*!< PPARB8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB9_Pos (9UL) /*!< PPARB9 (Bit 9) */ - #define R_PSCU_PPARB_PPARB9_Msk (0x200UL) /*!< PPARB9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB11_Pos (11UL) /*!< PPARB11 (Bit 11) */ - #define R_PSCU_PPARB_PPARB11_Msk (0x800UL) /*!< PPARB11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB12_Pos (12UL) /*!< PPARB12 (Bit 12) */ - #define R_PSCU_PPARB_PPARB12_Msk (0x1000UL) /*!< PPARB12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB15_Pos (15UL) /*!< PPARB15 (Bit 15) */ - #define R_PSCU_PPARB_PPARB15_Msk (0x8000UL) /*!< PPARB15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB16_Pos (16UL) /*!< PPARB16 (Bit 16) */ - #define R_PSCU_PPARB_PPARB16_Msk (0x10000UL) /*!< PPARB16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB18_Pos (18UL) /*!< PPARB18 (Bit 18) */ - #define R_PSCU_PPARB_PPARB18_Msk (0x40000UL) /*!< PPARB18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB19_Pos (19UL) /*!< PPARB19 (Bit 19) */ - #define R_PSCU_PPARB_PPARB19_Msk (0x80000UL) /*!< PPARB19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB22_Pos (22UL) /*!< PPARB22 (Bit 22) */ - #define R_PSCU_PPARB_PPARB22_Msk (0x400000UL) /*!< PPARB22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB27_Pos (27UL) /*!< PPARB27 (Bit 27) */ - #define R_PSCU_PPARB_PPARB27_Msk (0x8000000UL) /*!< PPARB27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB28_Pos (28UL) /*!< PPARB28 (Bit 28) */ - #define R_PSCU_PPARB_PPARB28_Msk (0x10000000UL) /*!< PPARB28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB29_Pos (29UL) /*!< PPARB29 (Bit 29) */ - #define R_PSCU_PPARB_PPARB29_Msk (0x20000000UL) /*!< PPARB29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB30_Pos (30UL) /*!< PPARB30 (Bit 30) */ - #define R_PSCU_PPARB_PPARB30_Msk (0x40000000UL) /*!< PPARB30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB31_Pos (31UL) /*!< PPARB31 (Bit 31) */ - #define R_PSCU_PPARB_PPARB31_Msk (0x80000000UL) /*!< PPARB31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB_Pos (0UL) /*!< PPARB (Bit 0) */ + #define R_PSCU_PPARB_PPARB_Msk (0x1UL) /*!< PPARB (Bitfield-Mask: 0x01) */ /* ========================================================= PPARC ========================================================= */ - #define R_PSCU_PPARC_PPARC0_Pos (0UL) /*!< PPARC0 (Bit 0) */ - #define R_PSCU_PPARC_PPARC0_Msk (0x1UL) /*!< PPARC0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC1_Pos (1UL) /*!< PPARC1 (Bit 1) */ - #define R_PSCU_PPARC_PPARC1_Msk (0x2UL) /*!< PPARC1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC7_Pos (7UL) /*!< PPARC7 (Bit 7) */ - #define R_PSCU_PPARC_PPARC7_Msk (0x80UL) /*!< PPARC7 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC8_Pos (8UL) /*!< PPARC8 (Bit 8) */ - #define R_PSCU_PPARC_PPARC8_Msk (0x100UL) /*!< PPARC8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC11_Pos (11UL) /*!< PPARC11 (Bit 11) */ - #define R_PSCU_PPARC_PPARC11_Msk (0x800UL) /*!< PPARC11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC12_Pos (12UL) /*!< PPARC12 (Bit 12) */ - #define R_PSCU_PPARC_PPARC12_Msk (0x1000UL) /*!< PPARC12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC13_Pos (13UL) /*!< PPARC13 (Bit 13) */ - #define R_PSCU_PPARC_PPARC13_Msk (0x2000UL) /*!< PPARC13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC15_Pos (15UL) /*!< PPARC15 (Bit 15) */ - #define R_PSCU_PPARC_PPARC15_Msk (0x8000UL) /*!< PPARC15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC16_Pos (16UL) /*!< PPARC16 (Bit 16) */ - #define R_PSCU_PPARC_PPARC16_Msk (0x10000UL) /*!< PPARC16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC26_Pos (26UL) /*!< PPARC26 (Bit 26) */ - #define R_PSCU_PPARC_PPARC26_Msk (0x4000000UL) /*!< PPARC26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC27_Pos (27UL) /*!< PPARC27 (Bit 27) */ - #define R_PSCU_PPARC_PPARC27_Msk (0x8000000UL) /*!< PPARC27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC31_Pos (31UL) /*!< PPARC31 (Bit 31) */ - #define R_PSCU_PPARC_PPARC31_Msk (0x80000000UL) /*!< PPARC31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARC_PPARC_Pos (0UL) /*!< PPARC (Bit 0) */ + #define R_PSCU_PPARC_PPARC_Msk (0x1UL) /*!< PPARC (Bitfield-Mask: 0x01) */ /* ========================================================= PPARD ========================================================= */ - #define R_PSCU_PPARD_PPARD4_Pos (4UL) /*!< PPARD4 (Bit 4) */ - #define R_PSCU_PPARD_PPARD4_Msk (0x10UL) /*!< PPARD4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD5_Pos (5UL) /*!< PPARD5 (Bit 5) */ - #define R_PSCU_PPARD_PPARD5_Msk (0x20UL) /*!< PPARD5 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD11_Pos (11UL) /*!< PPARD11 (Bit 11) */ - #define R_PSCU_PPARD_PPARD11_Msk (0x800UL) /*!< PPARD11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD12_Pos (12UL) /*!< PPARD12 (Bit 12) */ - #define R_PSCU_PPARD_PPARD12_Msk (0x1000UL) /*!< PPARD12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD13_Pos (13UL) /*!< PPARD13 (Bit 13) */ - #define R_PSCU_PPARD_PPARD13_Msk (0x2000UL) /*!< PPARD13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD14_Pos (14UL) /*!< PPARD14 (Bit 14) */ - #define R_PSCU_PPARD_PPARD14_Msk (0x4000UL) /*!< PPARD14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD15_Pos (15UL) /*!< PPARD15 (Bit 15) */ - #define R_PSCU_PPARD_PPARD15_Msk (0x8000UL) /*!< PPARD15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD16_Pos (16UL) /*!< PPARD16 (Bit 16) */ - #define R_PSCU_PPARD_PPARD16_Msk (0x10000UL) /*!< PPARD16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD20_Pos (20UL) /*!< PPARD20 (Bit 20) */ - #define R_PSCU_PPARD_PPARD20_Msk (0x100000UL) /*!< PPARD20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD22_Pos (22UL) /*!< PPARD22 (Bit 22) */ - #define R_PSCU_PPARD_PPARD22_Msk (0x400000UL) /*!< PPARD22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD27_Pos (27UL) /*!< PPARD27 (Bit 27) */ - #define R_PSCU_PPARD_PPARD27_Msk (0x8000000UL) /*!< PPARD27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD28_Pos (28UL) /*!< PPARD28 (Bit 28) */ - #define R_PSCU_PPARD_PPARD28_Msk (0x10000000UL) /*!< PPARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARD_PPARD_Pos (0UL) /*!< PPARD (Bit 0) */ + #define R_PSCU_PPARD_PPARD_Msk (0x1UL) /*!< PPARD (Bitfield-Mask: 0x01) */ /* ========================================================= PPARE ========================================================= */ - #define R_PSCU_PPARE_PPARE1_Pos (1UL) /*!< PPARE1 (Bit 1) */ - #define R_PSCU_PPARE_PPARE1_Msk (0x2UL) /*!< PPARE1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE2_Pos (2UL) /*!< PPARE2 (Bit 2) */ - #define R_PSCU_PPARE_PPARE2_Msk (0x4UL) /*!< PPARE2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE3_Pos (3UL) /*!< PPARE3 (Bit 3) */ - #define R_PSCU_PPARE_PPARE3_Msk (0x8UL) /*!< PPARE3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE8_Pos (8UL) /*!< PPARE8 (Bit 8) */ - #define R_PSCU_PPARE_PPARE8_Msk (0x100UL) /*!< PPARE8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE9_Pos (9UL) /*!< PPARE9 (Bit 9) */ - #define R_PSCU_PPARE_PPARE9_Msk (0x200UL) /*!< PPARE9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE18_Pos (18UL) /*!< PPARE18 (Bit 18) */ - #define R_PSCU_PPARE_PPARE18_Msk (0x40000UL) /*!< PPARE18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE19_Pos (19UL) /*!< PPARE19 (Bit 19) */ - #define R_PSCU_PPARE_PPARE19_Msk (0x80000UL) /*!< PPARE19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE20_Pos (20UL) /*!< PPARE20 (Bit 20) */ - #define R_PSCU_PPARE_PPARE20_Msk (0x100000UL) /*!< PPARE20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE21_Pos (21UL) /*!< PPARE21 (Bit 21) */ - #define R_PSCU_PPARE_PPARE21_Msk (0x200000UL) /*!< PPARE21 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE22_Pos (22UL) /*!< PPARE22 (Bit 22) */ - #define R_PSCU_PPARE_PPARE22_Msk (0x400000UL) /*!< PPARE22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE23_Pos (23UL) /*!< PPARE23 (Bit 23) */ - #define R_PSCU_PPARE_PPARE23_Msk (0x800000UL) /*!< PPARE23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE24_Pos (24UL) /*!< PPARE24 (Bit 24) */ - #define R_PSCU_PPARE_PPARE24_Msk (0x1000000UL) /*!< PPARE24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE25_Pos (25UL) /*!< PPARE25 (Bit 25) */ - #define R_PSCU_PPARE_PPARE25_Msk (0x2000000UL) /*!< PPARE25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE26_Pos (26UL) /*!< PPARE26 (Bit 26) */ - #define R_PSCU_PPARE_PPARE26_Msk (0x4000000UL) /*!< PPARE26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE27_Pos (27UL) /*!< PPARE27 (Bit 27) */ - #define R_PSCU_PPARE_PPARE27_Msk (0x8000000UL) /*!< PPARE27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE28_Pos (28UL) /*!< PPARE28 (Bit 28) */ - #define R_PSCU_PPARE_PPARE28_Msk (0x10000000UL) /*!< PPARE28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE29_Pos (29UL) /*!< PPARE29 (Bit 29) */ - #define R_PSCU_PPARE_PPARE29_Msk (0x20000000UL) /*!< PPARE29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE30_Pos (30UL) /*!< PPARE30 (Bit 30) */ - #define R_PSCU_PPARE_PPARE30_Msk (0x40000000UL) /*!< PPARE30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE31_Pos (31UL) /*!< PPARE31 (Bit 31) */ - #define R_PSCU_PPARE_PPARE31_Msk (0x80000000UL) /*!< PPARE31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE_Pos (0UL) /*!< PPARE (Bit 0) */ + #define R_PSCU_PPARE_PPARE_Msk (0x1UL) /*!< PPARE (Bitfield-Mask: 0x01) */ /* ========================================================= MSPAR ========================================================= */ - #define R_PSCU_MSPAR_MSPAR31_Pos (31UL) /*!< MSPAR31 (Bit 31) */ - #define R_PSCU_MSPAR_MSPAR31_Msk (0x80000000UL) /*!< MSPAR31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSPAR_MSPAR_Pos (0UL) /*!< MSPAR (Bit 0) */ + #define R_PSCU_MSPAR_MSPAR_Msk (0x1UL) /*!< MSPAR (Bitfield-Mask: 0x01) */ /* ======================================================= CFSAMONA ======================================================== */ - #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ - #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ /* ======================================================== DFSAMON ======================================================== */ - #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ - #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ /* ======================================================== DLMMON ========================================================= */ - #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ - #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ /* =========================================================================================================================== */ /* ================ R_BUS ================ */ @@ -24315,6 +24417,9 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -24796,6 +24901,11 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -24911,30 +25021,49 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -26118,10 +26247,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -26772,6 +26897,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ /* ========================================================= BSTE ========================================================== */ #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ @@ -26787,6 +26914,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ /* ========================================================== BIE ========================================================== */ #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ @@ -26802,6 +26931,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ /* ========================================================= BSTFC ========================================================= */ #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ @@ -26817,6 +26948,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ /* ========================================================= NTST ========================================================== */ #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ @@ -27019,6 +27152,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT1 ========================================================= */ @@ -27030,6 +27167,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT2 ========================================================= */ @@ -27041,6 +27182,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT3 ========================================================= */ @@ -27052,6 +27197,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ @@ -27065,6 +27214,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================= SDCTPIDL ======================================================== */ @@ -27126,6 +27279,13 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ /* ======================================================== BITCNT ========================================================= */ #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ @@ -27216,10 +27376,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* =========================================================================================================================== */ /* ======================================================== PCNTR1 ========================================================= */ - #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ - #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ /* ========================================================== PDR ========================================================== */ #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ @@ -27227,10 +27387,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ /* ======================================================== PCNTR2 ========================================================= */ - #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ - #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ /* ========================================================= PIDR ========================================================== */ #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ @@ -27238,10 +27398,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ /* ======================================================== PCNTR3 ========================================================= */ - #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ - #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ /* ========================================================= POSR ========================================================== */ #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ @@ -27249,10 +27409,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ /* ======================================================== PCNTR4 ========================================================= */ - #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ - #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ /* ========================================================= EOSR ========================================================== */ #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ @@ -27271,6 +27431,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================== PFENET ========================================================= */ #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ /* ========================================================= PWPR ========================================================== */ #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ @@ -27287,20 +27449,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -28762,8 +28914,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_SYSTEM_RSTSR1_CMRF_Msk (0x4000UL) /*!< CMRF (Bitfield-Mask: 0x01) */ #define R_SYSTEM_RSTSR1_WDT1RF_Pos (17UL) /*!< WDT1RF (Bit 17) */ #define R_SYSTEM_RSTSR1_WDT1RF_Msk (0x20000UL) /*!< WDT1RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_CLU1RF_Pos (20UL) /*!< CLU1RF (Bit 20) */ - #define R_SYSTEM_RSTSR1_CLU1RF_Msk (0x100000UL) /*!< CLU1RF (Bitfield-Mask: 0x01) */ #define R_SYSTEM_RSTSR1_LM1RF_Pos (21UL) /*!< LM1RF (Bit 21) */ #define R_SYSTEM_RSTSR1_LM1RF_Msk (0x200000UL) /*!< LM1RF (Bitfield-Mask: 0x01) */ #define R_SYSTEM_RSTSR1_NWRF_Pos (22UL) /*!< NWRF (Bit 22) */ @@ -29278,10 +29428,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_SYSTEM_SYRSTMSK0_BUSMASK_Pos (7UL) /*!< BUSMASK (Bit 7) */ #define R_SYSTEM_SYRSTMSK0_BUSMASK_Msk (0x80UL) /*!< BUSMASK (Bitfield-Mask: 0x01) */ /* ======================================================= SYRSTMSK1 ======================================================= */ - #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Pos (1UL) /*!< WDT1MASK (Bit 1) */ - #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Msk (0x2UL) /*!< WDT1MASK (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SYRSTMSK1_CLUP1MASK_Pos (4UL) /*!< CLUP1MASK (Bit 4) */ - #define R_SYSTEM_SYRSTMSK1_CLUP1MASK_Msk (0x10UL) /*!< CLUP1MASK (Bitfield-Mask: 0x01) */ #define R_SYSTEM_SYRSTMSK1_LM1MASK_Pos (5UL) /*!< LM1MASK (Bit 5) */ #define R_SYSTEM_SYRSTMSK1_LM1MASK_Msk (0x20UL) /*!< LM1MASK (Bitfield-Mask: 0x01) */ #define R_SYSTEM_SYRSTMSK1_NWMASK_Pos (7UL) /*!< NWMASK (Bit 7) */ @@ -30444,6 +30590,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ @@ -30467,6 +30615,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ @@ -30490,18 +30640,39 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================== ICUSARI ======================================================== */ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARA ======================================================== */ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARB ======================================================== */ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ /* ======================================================= MMPUSARA ======================================================== */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ /* ======================================================= DMACCHSAR ======================================================= */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8T1AH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8T1AH.h index 851b7125a..e97b28d16 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8T1AH.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8T1AH.h @@ -47,8 +47,8 @@ extern "C" { #define __ICACHE_PRESENT 1 /*!< Instruction Cache present */ #define __DCACHE_PRESENT 1 /*!< Data Cache present */ #define __SAUREGION_PRESENT 1 /*!< SAU region present */ - #define __PMU_PRESENT 0 /*!< PMU present */ - #define __PMU_NUM_EVENTCNT 0 /*!< PMU Event Counters */ + #define __PMU_PRESENT 1 /*!< PMU present */ + #define __PMU_NUM_EVENTCNT 8 /*!< PMU Event Counters */ /** @} */ /* End of group Configuration_of_CMSIS */ @@ -472,24 +472,41 @@ typedef struct uint8_t : 2; } STAT_b; }; - __IM uint8_t RESERVED[7]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - struct + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; }; - __IM uint8_t RESERVED1[7]; + __IM uint32_t RESERVED3; } R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** @@ -706,27 +723,13 @@ typedef struct union { - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union + struct { - __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU1TCMBI_b; - }; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; }; __IM uint32_t RESERVED12; @@ -1361,7 +1364,7 @@ typedef struct struct { __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry enable */ __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ } ID_b; @@ -1418,7 +1421,7 @@ typedef struct struct { __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ } ID_b; @@ -1643,7 +1646,7 @@ typedef struct } R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) */ typedef struct { @@ -4028,32 +4031,42 @@ typedef struct /*!< (@ 0x40204000) R_PSCU Structure union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ - - struct - { - uint32_t : 4; - __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C Bus Interface 2 Security Attribution */ - uint32_t : 3; - __IOM uint32_t PSARB8 : 1; /*!< [8..8] I2C Bus Interface 1 Security Attribution */ - __IOM uint32_t PSARB9 : 1; /*!< [9..9] I2C Bus Interface 0 Security Attribution */ - uint32_t : 1; - __IOM uint32_t PSARB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface 0 Security Attribution */ - __IOM uint32_t PSARB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface 0 Security Attribution */ - uint32_t : 2; - __IOM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0 Controller Security Attribution */ - __IOM uint32_t PSARB16 : 1; /*!< [16..16] Octa Memory Controller Security Attribution */ - uint32_t : 1; - __IOM uint32_t PSARB18 : 1; /*!< [18..18] Serial Peripheral Interface 1 Security Attribution */ - __IOM uint32_t PSARB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Security Attribution */ - uint32_t : 2; - __IOM uint32_t PSARB22 : 1; /*!< [22..22] Serial Communication Interface 9 Security Attribution */ - uint32_t : 4; - __IOM uint32_t PSARB27 : 1; /*!< [27..27] Serial Communication Interface 4 Security Attribution */ - __IOM uint32_t PSARB28 : 1; /*!< [28..28] Serial Communication Interface 3 Security Attribution */ - __IOM uint32_t PSARB29 : 1; /*!< [29..29] Serial Communication Interface 2 Security Attribution */ - __IOM uint32_t PSARB30 : 1; /*!< [30..30] Serial Communication Interface 1 Security Attribution */ - __IOM uint32_t PSARB31 : 1; /*!< [31..31] Serial Communication Interface 0 Security Attribution */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + __IOM uint32_t PSARB0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARB1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARB4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARB6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARB10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARB11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARB13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARB14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARB15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARB16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARB17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARB18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARB20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARB21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARB22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ } PSARB_b; }; @@ -4063,86 +4076,120 @@ typedef struct /*!< (@ 0x40204000) R_PSCU Structure struct { - __IOM uint32_t PSARC0 : 1; /*!< [0..0] Clock Frequency Accuracy Measurement Circuit Security - * Attribution */ - __IOM uint32_t PSARC1 : 1; /*!< [1..1] Cyclic Redundancy Check Calculator Security Attribution */ - uint32_t : 5; - __IOM uint32_t PSARC7 : 1; /*!< [7..7] Serial Sound Interface Enhanced (channel 1) Security - * Attribution */ - __IOM uint32_t PSARC8 : 1; /*!< [8..8] Serial Sound Interface Enhanced (channel 0) Security - * Attribution */ - uint32_t : 2; - __IOM uint32_t PSARC11 : 1; /*!< [11..11] Secure Digital Host IF 1 Security Attribution */ - __IOM uint32_t PSARC12 : 1; /*!< [12..12] Secure Digital Host IF 0 Security Attribution */ - __IOM uint32_t PSARC13 : 1; /*!< [13..13] Data Operation Circuit Security Attribution */ - uint32_t : 1; - __IOM uint32_t PSARC15 : 1; /*!< [15..15] Graph-ic(GLCDC,MIPI,DRW,JPEG) Security Attribution */ - __IOM uint32_t PSARC16 : 1; /*!< [16..16] CEU Security Attribution */ - uint32_t : 9; - __IOM uint32_t PSARC26 : 1; /*!< [26..26] Controller Area Network with Flexible Data-Rate 1 Security - * Attribution */ - __IOM uint32_t PSARC27 : 1; /*!< [27..27] Controller Area Network with Flexible Data-Rate 0 Security - * Attribution */ - uint32_t : 3; - __IOM uint32_t PSARC31 : 1; /*!< [31..31] SHIP Security Attribution */ + __IOM uint32_t PSARC0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARC2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARC3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARC4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARC5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARC6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARC7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARC8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARC9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARC10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARC11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARC12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARC14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARC15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARC16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARC17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARC18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARC19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARC20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARC21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARC22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARC23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARC24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARC25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARC26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARC27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARC28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARC29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARC30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARC31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ } PSARC_b; }; union { - __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ - - struct - { - uint32_t : 4; - __IOM uint32_t PSARD4 : 1; /*!< [4..4] Asynchronous General Purpose Timer 1 Security Attribution */ - __IOM uint32_t PSARD5 : 1; /*!< [5..5] Asynchronous General Purpose Timer 0 Security Attribution */ - uint32_t : 5; - __IOM uint32_t PSARD11 : 1; /*!< [11..11] Port Output Enable for GPT Group 3 Security Attribution */ - __IOM uint32_t PSARD12 : 1; /*!< [12..12] Port Output Enable for GPT Group 2 Security Attribution */ - __IOM uint32_t PSARD13 : 1; /*!< [13..13] Port Output Enable for GPT Group 1 Security Attribution */ - __IOM uint32_t PSARD14 : 1; /*!< [14..14] Port Output Enable for GPT Group 0 Security Attribution */ - __IOM uint32_t PSARD15 : 1; /*!< [15..15] 12-Bit A/D 1 Converter Security Attribution */ - __IOM uint32_t PSARD16 : 1; /*!< [16..16] 12-Bit A/D 0 Converter Security Attribution */ - uint32_t : 3; - __IOM uint32_t PSARD20 : 1; /*!< [20..20] 12-Bit D/A Converter Security Attribution */ - uint32_t : 1; - __IOM uint32_t PSARD22 : 1; /*!< [22..22] Temperature Sensor Security Attribution */ - uint32_t : 4; - __IOM uint32_t PSARD27 : 1; /*!< [27..27] High speed analog Comparator 1 Security Attribution */ - __IOM uint32_t PSARD28 : 1; /*!< [28..28] High speed analog Comparator 0 Security Attribution */ - uint32_t : 3; + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARD4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARD5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARD6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARD7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARD8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARD9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARD10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARD11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARD17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARD18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARD19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARD21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARD22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARD23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARD24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARD25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARD29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARD30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARD31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ } PSARD_b; }; union { - __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ - - struct - { - uint32_t : 1; - __IOM uint32_t PSARE1 : 1; /*!< [1..1] WDT0 Security Attribution */ - __IOM uint32_t PSARE2 : 1; /*!< [2..2] Independent Watchdog Timer Security Attribution */ - __IOM uint32_t PSARE3 : 1; /*!< [3..3] Real Time Clock Security Attribution */ - uint32_t : 4; - __IOM uint32_t PSARE8 : 1; /*!< [8..8] ULPT1 Security Attribution */ - __IOM uint32_t PSARE9 : 1; /*!< [9..9] ULPT0 Security Attribution */ - uint32_t : 8; - __IOM uint32_t PSARE18 : 1; /*!< [18..18] General PWM Timer channel13 Security Attribution */ - __IOM uint32_t PSARE19 : 1; /*!< [19..19] General PWM Timer channel12 Security Attribution */ - __IOM uint32_t PSARE20 : 1; /*!< [20..20] General PWM Timer channel11 Security Attribution */ - __IOM uint32_t PSARE21 : 1; /*!< [21..21] General PWM Timer channel10 Security Attribution */ - __IOM uint32_t PSARE22 : 1; /*!< [22..22] General PWM Timer channel9 Security Attribution */ - __IOM uint32_t PSARE23 : 1; /*!< [23..23] General PWM Timer channel8 Security Attribution */ - __IOM uint32_t PSARE24 : 1; /*!< [24..24] General PWM Timer channel7 Security Attribution */ - __IOM uint32_t PSARE25 : 1; /*!< [25..25] General PWM Timer channel6 Security Attribution */ - __IOM uint32_t PSARE26 : 1; /*!< [26..26] General PWM Timer channel5 Security Attribution */ - __IOM uint32_t PSARE27 : 1; /*!< [27..27] General PWM Timer channel4 Security Attribution */ - __IOM uint32_t PSARE28 : 1; /*!< [28..28] General PWM Timer channel3 Security Attribution */ - __IOM uint32_t PSARE29 : 1; /*!< [29..29] General PWM Timer channel2 Security Attribution */ - __IOM uint32_t PSARE30 : 1; /*!< [30..30] General PWM Timer channel1 Security Attribution */ - __IOM uint32_t PSARE31 : 1; /*!< [31..31] General PWM Timer channel0 Security Attribution */ + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARE3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARE4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARE5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARE6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARE7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARE8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARE9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARE10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARE11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARE12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARE13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARE14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARE16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARE17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARE18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARE19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARE20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARE21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARE22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ } PSARE_b; }; @@ -4152,50 +4199,80 @@ typedef struct /*!< (@ 0x40204000) R_PSCU Structure struct { - __IOM uint32_t MSSAR0 : 1; /*!< [0..0] SRAM0 Clock Stop Security Attribution */ - __IOM uint32_t MSSAR1 : 1; /*!< [1..1] SRAM1 Clock Stop Security Attribution */ - uint32_t : 9; - __IOM uint32_t MSSAR11 : 1; /*!< [11..11] CTCM0 Security Attribution */ - uint32_t : 1; - __IOM uint32_t MSSAR13 : 1; /*!< [13..13] STCM0 Security Attribution */ - uint32_t : 1; - __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Standby RAM Clock Stop Security Attribution */ - uint32_t : 6; - __IOM uint32_t MSSAR22 : 1; /*!< [22..22] DMAC0/DTC0 Clock Stop Security Attribution */ - uint32_t : 8; - __IOM uint32_t MSSAR31 : 1; /*!< [31..31] ELC clock stop Security Attribution */ + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] Module stop security attribution bit 0 */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] Module stop security attribution bit 1 */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] Module stop security attribution bit 2 */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] Module stop security attribution bit 3 */ + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] Module stop security attribution bit 4 */ + __IOM uint32_t MSSAR5 : 1; /*!< [5..5] Module stop security attribution bit 5 */ + __IOM uint32_t MSSAR6 : 1; /*!< [6..6] Module stop security attribution bit 6 */ + __IOM uint32_t MSSAR7 : 1; /*!< [7..7] Module stop security attribution bit 7 */ + __IOM uint32_t MSSAR8 : 1; /*!< [8..8] Module stop security attribution bit 8 */ + __IOM uint32_t MSSAR9 : 1; /*!< [9..9] Module stop security attribution bit 9 */ + __IOM uint32_t MSSAR10 : 1; /*!< [10..10] Module stop security attribution bit 10 */ + __IOM uint32_t MSSAR11 : 1; /*!< [11..11] Module stop security attribution bit 11 */ + __IOM uint32_t MSSAR12 : 1; /*!< [12..12] Module stop security attribution bit 12 */ + __IOM uint32_t MSSAR13 : 1; /*!< [13..13] Module stop security attribution bit 13 */ + __IOM uint32_t MSSAR14 : 1; /*!< [14..14] Module stop security attribution bit 14 */ + __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Module stop security attribution bit 15 */ + __IOM uint32_t MSSAR16 : 1; /*!< [16..16] Module stop security attribution bit 16 */ + __IOM uint32_t MSSAR17 : 1; /*!< [17..17] Module stop security attribution bit 17 */ + __IOM uint32_t MSSAR18 : 1; /*!< [18..18] Module stop security attribution bit 18 */ + __IOM uint32_t MSSAR19 : 1; /*!< [19..19] Module stop security attribution bit 19 */ + __IOM uint32_t MSSAR20 : 1; /*!< [20..20] Module stop security attribution bit 20 */ + __IOM uint32_t MSSAR21 : 1; /*!< [21..21] Module stop security attribution bit 21 */ + __IOM uint32_t MSSAR22 : 1; /*!< [22..22] Module stop security attribution bit 22 */ + __IOM uint32_t MSSAR23 : 1; /*!< [23..23] Module stop security attribution bit 23 */ + __IOM uint32_t MSSAR24 : 1; /*!< [24..24] Module stop security attribution bit 24 */ + __IOM uint32_t MSSAR25 : 1; /*!< [25..25] Module stop security attribution bit 25 */ + __IOM uint32_t MSSAR26 : 1; /*!< [26..26] Module stop security attribution bit 26 */ + __IOM uint32_t MSSAR27 : 1; /*!< [27..27] Module stop security attribution bit 27 */ + __IOM uint32_t MSSAR28 : 1; /*!< [28..28] Module stop security attribution bit 28 */ + __IOM uint32_t MSSAR29 : 1; /*!< [29..29] Module stop security attribution bit 29 */ + __IOM uint32_t MSSAR30 : 1; /*!< [30..30] Module stop security attribution bit 30 */ + __IOM uint32_t MSSAR31 : 1; /*!< [31..31] Module stop security attribution bit 31 */ } MSSAR_b; }; __IM uint32_t RESERVED1; union { - __IOM uint32_t PPARB; /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B */ - - struct - { - uint32_t : 4; - __IOM uint32_t PPARB4 : 1; /*!< [4..4] I3C Bus Interface 2 Privilege Attribution */ - uint32_t : 3; - __IOM uint32_t PPARB8 : 1; /*!< [8..8] I2C Bus Interface 1 Privilege Attribution */ - __IOM uint32_t PPARB9 : 1; /*!< [9..9] I2C Bus Interface 0 Privilege Attribution */ - uint32_t : 1; - __IOM uint32_t PPARB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface 0 Privilege Attribution */ - __IOM uint32_t PPARB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface 0 Privilege Attribution */ - uint32_t : 2; - __IOM uint32_t PPARB15 : 1; /*!< [15..15] ETHER0/EDMAC0 Controller Privilege Attribution */ - __IOM uint32_t PPARB16 : 1; /*!< [16..16] Octa Memory Controller Privilege Attribution */ - uint32_t : 1; - __IOM uint32_t PPARB18 : 1; /*!< [18..18] Serial Peripheral Interface 1 Privilege Attribution */ - __IOM uint32_t PPARB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Privilege Attribution */ - uint32_t : 2; - __IOM uint32_t PPARB22 : 1; /*!< [22..22] Serial Communication Interface 9 Privilege Attribution */ - uint32_t : 4; - __IOM uint32_t PPARB27 : 1; /*!< [27..27] Serial Communication Interface 4 Privilege Attribution */ - __IOM uint32_t PPARB28 : 1; /*!< [28..28] Serial Communication Interface 3 Privilege Attribution */ - __IOM uint32_t PPARB29 : 1; /*!< [29..29] Serial Communication Interface 2 Privilege Attribution */ - __IOM uint32_t PPARB30 : 1; /*!< [30..30] Serial Communication Interface 1 Privilege Attribution */ - __IOM uint32_t PPARB31 : 1; /*!< [31..31] Serial Communication Interface 0 Privilege Attribution */ + __IOM uint32_t PPARB; /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B */ + + struct + { + __IOM uint32_t PPARB0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARB1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARB2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARB3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARB4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARB5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARB6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARB7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARB8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARB9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARB10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARB11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARB12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARB13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARB14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARB15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARB16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARB17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARB18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARB19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARB20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARB21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARB22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARB23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARB24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARB25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARB26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARB27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARB28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARB29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARB30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARB31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ } PPARB_b; }; @@ -4205,104 +4282,167 @@ typedef struct /*!< (@ 0x40204000) R_PSCU Structure struct { - __IOM uint32_t PPARC0 : 1; /*!< [0..0] Clock Frequency Accuracy Measurement Circuit Privilege - * Attribution */ - __IOM uint32_t PPARC1 : 1; /*!< [1..1] Cyclic Redundancy Check Calculator Privilege Attribution */ - uint32_t : 5; - __IOM uint32_t PPARC7 : 1; /*!< [7..7] Serial Sound Interface Enhanced (channel 1) Privilege - * Attribution */ - __IOM uint32_t PPARC8 : 1; /*!< [8..8] Serial Sound Interface Enhanced (channel 0) Privilege - * Attribution */ - uint32_t : 2; - __IOM uint32_t PPARC11 : 1; /*!< [11..11] Privilege Digital Host IF 1 Privilege Attribution */ - __IOM uint32_t PPARC12 : 1; /*!< [12..12] Privilege Digital Host IF 0 Privilege Attribution */ - __IOM uint32_t PPARC13 : 1; /*!< [13..13] Data Operation Circuit Privilege Attribution */ - uint32_t : 1; - __IOM uint32_t PPARC15 : 1; /*!< [15..15] Graph-ic(GLCDC,MIPI,DRW,JPEG) Privilege Attribution */ - __IOM uint32_t PPARC16 : 1; /*!< [16..16] CEU Privilege Attribution */ - uint32_t : 9; - __IOM uint32_t PPARC26 : 1; /*!< [26..26] Controller Area Network with Flexible Data-Rate 1 Privilege - * Attribution */ - __IOM uint32_t PPARC27 : 1; /*!< [27..27] Controller Area Network with Flexible Data-Rate 0 Privilege - * Attribution */ - uint32_t : 3; - __IOM uint32_t PPARC31 : 1; /*!< [31..31] SHIP Privilege Attribution */ + __IOM uint32_t PPARC0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARC1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARC2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARC3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARC4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARC5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARC6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARC7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARC8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARC9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARC10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARC11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARC12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARC13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARC14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARC15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARC16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARC17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARC18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARC19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARC20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARC21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARC22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARC23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARC24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARC25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARC26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARC27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARC28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARC29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARC30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARC31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ } PPARC_b; }; union { - __IOM uint32_t PPARD; /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D */ - - struct - { - uint32_t : 4; - __IOM uint32_t PPARD4 : 1; /*!< [4..4] Asynchronous General Purpose Timer 1 Privilege Attribution */ - __IOM uint32_t PPARD5 : 1; /*!< [5..5] Asynchronous General Purpose Timer 0 Privilege Attribution */ - uint32_t : 5; - __IOM uint32_t PPARD11 : 1; /*!< [11..11] Port Output Enable for GPT Group 3 Privilege Attribution */ - __IOM uint32_t PPARD12 : 1; /*!< [12..12] Port Output Enable for GPT Group 2 Privilege Attribution */ - __IOM uint32_t PPARD13 : 1; /*!< [13..13] Port Output Enable for GPT Group 1 Privilege Attribution */ - __IOM uint32_t PPARD14 : 1; /*!< [14..14] Port Output Enable for GPT Group 0 Privilege Attribution */ - __IOM uint32_t PPARD15 : 1; /*!< [15..15] 12-Bit A/D 1 Converter Privilege Attribution */ - __IOM uint32_t PPARD16 : 1; /*!< [16..16] 12-Bit A/D 0 Converter Privilege Attribution */ - uint32_t : 3; - __IOM uint32_t PPARD20 : 1; /*!< [20..20] 12-Bit D/A Converter Privilege Attribution */ - uint32_t : 1; - __IOM uint32_t PPARD22 : 1; /*!< [22..22] Temperature Sensor Privilege Attribution */ - uint32_t : 4; - __IOM uint32_t PPARD27 : 1; /*!< [27..27] High speed analog Comparator 1 Privilege Attribution */ - __IOM uint32_t PPARD28 : 1; /*!< [28..28] High speed analog Comparator 0 Privilege Attribution */ - uint32_t : 3; + __IOM uint32_t PPARD; /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D */ + + struct + { + __IOM uint32_t PPARD0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARD1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARD2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARD3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARD4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARD5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARD6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARD7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARD8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARD9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARD10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARD11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARD12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARD13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARD14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARD15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARD16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARD17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARD18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARD19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARD20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARD21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARD22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARD23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARD24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARD25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARD26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARD27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARD28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARD29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARD30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARD31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ } PPARD_b; }; union { - __IOM uint32_t PPARE; /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E */ - - struct - { - uint32_t : 1; - __IOM uint32_t PPARE1 : 1; /*!< [1..1] Watchdog Timer0 Privilege Attribution */ - __IOM uint32_t PPARE2 : 1; /*!< [2..2] Independent Watchdog Timer Privilege Attribution */ - __IOM uint32_t PPARE3 : 1; /*!< [3..3] Real Time Clock Privilege Attribution */ - uint32_t : 4; - __IOM uint32_t PPARE8 : 1; /*!< [8..8] ULPT1 Privilege Attribution */ - __IOM uint32_t PPARE9 : 1; /*!< [9..9] ULPT0 Privilege Attribution */ - uint32_t : 8; - __IOM uint32_t PPARE18 : 1; /*!< [18..18] General PWM Timer channel13 Privilege Attribution */ - __IOM uint32_t PPARE19 : 1; /*!< [19..19] General PWM Timer channel12 Privilege Attribution */ - __IOM uint32_t PPARE20 : 1; /*!< [20..20] General PWM Timer channel11 Privilege Attribution */ - __IOM uint32_t PPARE21 : 1; /*!< [21..21] General PWM Timer channel10 Privilege Attribution */ - __IOM uint32_t PPARE22 : 1; /*!< [22..22] General PWM Timer channel9 Privilege Attribution */ - __IOM uint32_t PPARE23 : 1; /*!< [23..23] General PWM Timer channel8 Privilege Attribution */ - __IOM uint32_t PPARE24 : 1; /*!< [24..24] General PWM Timer channel7 Privilege Attribution */ - __IOM uint32_t PPARE25 : 1; /*!< [25..25] General PWM Timer channel6 Privilege Attribution */ - __IOM uint32_t PPARE26 : 1; /*!< [26..26] General PWM Timer channel5 Privilege Attribution */ - __IOM uint32_t PPARE27 : 1; /*!< [27..27] General PWM Timer channel4 Privilege Attribution */ - __IOM uint32_t PPARE28 : 1; /*!< [28..28] General PWM Timer channel3 Privilege Attribution */ - __IOM uint32_t PPARE29 : 1; /*!< [29..29] General PWM Timer channel2 Privilege Attribution */ - __IOM uint32_t PPARE30 : 1; /*!< [30..30] General PWM Timer channel1 Privilege Attribution */ - __IOM uint32_t PPARE31 : 1; /*!< [31..31] General PWM Timer channel0 Privilege Attribution */ + __IOM uint32_t PPARE; /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E */ + + struct + { + __IOM uint32_t PPARE0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARE1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARE2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARE3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARE4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARE5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARE6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARE7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARE8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARE9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARE10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARE11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARE12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARE13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARE14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARE15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARE16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARE17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARE18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARE19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARE20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARE21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARE22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARE23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARE24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARE25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARE26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARE27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARE28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARE29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARE30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARE31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ } PPARE_b; }; union { - __IOM uint32_t MSPAR; /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register */ - - struct - { - uint32_t : 31; - __IOM uint32_t MSPAR31 : 1; /*!< [31..31] ELC clock stop Privilege Attribution */ + __IOM uint32_t MSPAR; /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register */ + + struct + { + __IOM uint32_t MSPAR0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t MSPAR1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t MSPAR2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t MSPAR3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t MSPAR4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t MSPAR5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t MSPAR6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t MSPAR7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t MSPAR8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t MSPAR9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t MSPAR10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t MSPAR11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t MSPAR12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t MSPAR13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t MSPAR14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t MSPAR15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t MSPAR16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t MSPAR17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t MSPAR18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t MSPAR19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t MSPAR20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t MSPAR21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t MSPAR22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t MSPAR23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t MSPAR24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t MSPAR25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t MSPAR26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t MSPAR27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t MSPAR28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t MSPAR29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t MSPAR30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t MSPAR31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ } MSPAR_b; }; union { - __IM uint32_t CFSAMONA; /*!< (@ 0x00000030) Code Flash Security Attribution Monitor Register - * A */ + __IM uint32_t CFSAMONA; /*!< (@ 0x00000030) Code Flash Security Attribution Monitor Register */ struct { @@ -4423,9 +4563,22 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure uint32_t : 15; } BUSDIVBYP_b; }; - __IM uint32_t RESERVED7[319]; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED10[16]; union { @@ -4433,16 +4586,16 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address * and Read/Write Status registers. */ }; - __IM uint32_t RESERVED9[28]; + __IM uint32_t RESERVED11[28]; union { __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint32_t RESERVED10[16]; + __IM uint32_t RESERVED12[16]; __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED11[5]; + __IM uint32_t RESERVED13[5]; __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ } R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ @@ -5524,7 +5677,23 @@ typedef struct /*!< (@ 0x4000A800) R_DMA Structure }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; union { @@ -5540,7 +5709,7 @@ typedef struct /*!< (@ 0x4000A800) R_DMA Structure uint32_t : 15; } DMECHR_b; }; - __IM uint32_t RESERVED3[15]; + __IM uint32_t RESERVED6[15]; union { @@ -5838,11 +6007,22 @@ typedef struct /*!< (@ 0x4000AC00) R_DTC Structure struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ } DTCVBR_b; }; - __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; union { @@ -5854,7 +6034,7 @@ typedef struct /*!< (@ 0x4000AC00) R_DTC Structure uint8_t : 7; } DTCST_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED4; union { @@ -5877,15 +6057,34 @@ typedef struct /*!< (@ 0x4000AC00) R_DTC Structure struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; } DTCCR_SEC_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; union { @@ -5900,7 +6099,44 @@ typedef struct /*!< (@ 0x4000AC00) R_DTC Structure uint32_t : 15; } DTEVR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -8561,47 +8797,43 @@ typedef struct /*!< (@ 0x40323F00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40212000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40212000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 7; - __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ - __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ - __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ - __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; __IM uint32_t RESERVED[15]; @@ -9732,7 +9964,9 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ uint32_t : 3; __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; } BST_b; }; @@ -9753,7 +9987,9 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ uint32_t : 3; __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; } BSTE_b; }; @@ -9774,28 +10010,32 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ uint32_t : 3; __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 11; + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; } BIE_b; }; union { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ struct { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 11; + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; } BSTFC_b; }; @@ -10078,7 +10318,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT0_b; @@ -10095,7 +10336,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT1_b; @@ -10112,7 +10354,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT2_b; @@ -10129,7 +10372,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } MSDCT3_b; @@ -10147,7 +10391,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ uint32_t : 16; } SVDCT_b; @@ -10297,7 +10542,20 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28[2]; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; union { @@ -10423,9 +10681,7 @@ typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -11094,7 +11350,8 @@ typedef struct /*!< (@ 0x40400D00) R_PMISC Structure { uint8_t : 4; __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ - uint8_t : 3; + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; } PFENET_b; }; __IM uint8_t RESERVED; @@ -11146,14 +11403,16 @@ typedef struct /*!< (@ 0x40202000) R_RTC Structure struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ } R64CNT_b; }; __IM uint8_t RESERVED; @@ -13650,8 +13909,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - __IOM uint8_t CPUCK : 4; /*!< [3..0] CPU Clock (CPUCLK) Select */ - __IOM uint8_t CPUCK1 : 4; /*!< [7..4] CPU1 Clock (CPUCLK1) Select */ + __IOM uint8_t CPUCK : 4; /*!< [3..0] CPU Clock (CPUCLK) Select */ + uint8_t : 4; } SCKDIVCR2_b; }; __IM uint8_t RESERVED6; @@ -14316,10 +14575,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint32_t WDT1RF : 1; /*!< [17..17] Watchdog Timer1 Reset Detect Flag. NOTE: Writable only * to clear the flag. Confirm the value is 1 and then write * 0. */ - uint32_t : 2; - __IOM uint32_t CLU1RF : 1; /*!< [20..20] CPU1 Lockup Reset Detect Flag. NOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ + uint32_t : 3; __IOM uint32_t LM1RF : 1; /*!< [21..21] Local memory 1 error Reset Detect Flag. NOTE: Writable * only to clear the flag. Confirm the value is 1 and then * write 0. */ @@ -15252,13 +15508,10 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure struct { - uint8_t : 1; - __IOM uint8_t WDT1MASK : 1; /*!< [1..1] CPU1 Watchdog timer Reset Mask */ - uint8_t : 2; - __IOM uint8_t CLUP1MASK : 1; /*!< [4..4] CPU1 Lockup Reset Mask */ - __IOM uint8_t LM1MASK : 1; /*!< [5..5] Local memory 1 error Reset Mask */ - uint8_t : 1; - __IOM uint8_t NWMASK : 1; /*!< [7..7] Network Reset Mask */ + uint8_t : 5; + __IOM uint8_t LM1MASK : 1; /*!< [5..5] Local memory 1 error Reset Mask */ + uint8_t : 1; + __IOM uint8_t NWMASK : 1; /*!< [7..7] Network Reset Mask */ } SYRSTMSK1_b; }; __IM uint8_t RESERVED129; @@ -18143,21 +18396,22 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure struct { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 3; - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ } ICUSARE_b; }; @@ -18171,7 +18425,8 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 4; + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ @@ -18182,7 +18437,21 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 17; } ICUSARF_b; }; - __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + uint32_t : 28; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; union { @@ -18236,7 +18505,30 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } BUSSARB_b; }; - __IM uint32_t RESERVED5[10]; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; union { @@ -18261,7 +18553,33 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } MMPUSARB_b; }; - __IM uint32_t RESERVED6[26]; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; union { @@ -18274,7 +18592,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 24; } DMACCHSAR_b; }; - __IM uint32_t RESERVED7[3]; + __IM uint32_t RESERVED9[3]; union { @@ -18286,7 +18604,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[147]; + __IM uint32_t RESERVED10[147]; union { @@ -18315,7 +18633,7 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 11; } SRAMSABAR1_b; }; - __IM uint32_t RESERVED9[126]; + __IM uint32_t RESERVED11[126]; union { @@ -20192,6 +20510,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_AGTX9_BASE (0x40221900UL + BASE_NS_OFFSET) #define R_FLAD_BASE (0x4011C000UL + BASE_NS_OFFSET) #define R_OFS_DATAFLASH_BASE (0x27030000UL + BASE_NS_OFFSET) + #define R_SCI_B5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI_B6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI_B7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI_B8_BASE (0x40358800UL + BASE_NS_OFFSET) /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -20334,6 +20656,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) #define R_OFS_DATAFLASH ((R_OFS_DATAFLASH_Type *) R_OFS_DATAFLASH_BASE) + #define R_SCI_B5 ((R_SCI_B0_Type *) R_SCI_B5_BASE) + #define R_SCI_B6 ((R_SCI_B0_Type *) R_SCI_B6_BASE) + #define R_SCI_B7 ((R_SCI_B0_Type *) R_SCI_B7_BASE) + #define R_SCI_B8 ((R_SCI_B0_Type *) R_SCI_B8_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -20541,6 +20867,9 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ DMACDTCERR ================ */ @@ -20605,9 +20934,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================= CPU0SAHBI ======================================================= */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU1TCMBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSSABT1 ================ */ @@ -20952,6 +21278,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ @@ -20983,6 +21311,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ========================================================== ID =========================================================== */ #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ @@ -22041,272 +22371,44 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* =========================================================================================================================== */ /* ========================================================= PSARB ========================================================= */ - #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ - #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ - #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ - #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ - #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ - #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ - #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ - #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ - #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ - #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ - #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ - #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ - #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ - #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ - #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ - #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB_Pos (0UL) /*!< PSARB (Bit 0) */ + #define R_PSCU_PSARB_PSARB_Msk (0x1UL) /*!< PSARB (Bitfield-Mask: 0x01) */ /* ========================================================= PSARC ========================================================= */ - #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ - #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ - #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC7_Pos (7UL) /*!< PSARC7 (Bit 7) */ - #define R_PSCU_PSARC_PSARC7_Msk (0x80UL) /*!< PSARC7 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ - #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC11_Pos (11UL) /*!< PSARC11 (Bit 11) */ - #define R_PSCU_PSARC_PSARC11_Msk (0x800UL) /*!< PSARC11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ - #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ - #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC15_Pos (15UL) /*!< PSARC15 (Bit 15) */ - #define R_PSCU_PSARC_PSARC15_Msk (0x8000UL) /*!< PSARC15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC16_Pos (16UL) /*!< PSARC16 (Bit 16) */ - #define R_PSCU_PSARC_PSARC16_Msk (0x10000UL) /*!< PSARC16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC26_Pos (26UL) /*!< PSARC26 (Bit 26) */ - #define R_PSCU_PSARC_PSARC26_Msk (0x4000000UL) /*!< PSARC26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ - #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ - #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC_Pos (0UL) /*!< PSARC (Bit 0) */ + #define R_PSCU_PSARC_PSARC_Msk (0x1UL) /*!< PSARC (Bitfield-Mask: 0x01) */ /* ========================================================= PSARD ========================================================= */ - #define R_PSCU_PSARD_PSARD4_Pos (4UL) /*!< PSARD4 (Bit 4) */ - #define R_PSCU_PSARD_PSARD4_Msk (0x10UL) /*!< PSARD4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD5_Pos (5UL) /*!< PSARD5 (Bit 5) */ - #define R_PSCU_PSARD_PSARD5_Msk (0x20UL) /*!< PSARD5 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ - #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ - #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ - #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ - #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ - #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ - #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ - #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ - #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ - #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ - #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD_Pos (0UL) /*!< PSARD (Bit 0) */ + #define R_PSCU_PSARD_PSARD_Msk (0x1UL) /*!< PSARD (Bitfield-Mask: 0x01) */ /* ========================================================= PSARE ========================================================= */ - #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ - #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ - #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE3_Pos (3UL) /*!< PSARE3 (Bit 3) */ - #define R_PSCU_PSARE_PSARE3_Msk (0x8UL) /*!< PSARE3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE8_Pos (8UL) /*!< PSARE8 (Bit 8) */ - #define R_PSCU_PSARE_PSARE8_Msk (0x100UL) /*!< PSARE8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE9_Pos (9UL) /*!< PSARE9 (Bit 9) */ - #define R_PSCU_PSARE_PSARE9_Msk (0x200UL) /*!< PSARE9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE18_Pos (18UL) /*!< PSARE18 (Bit 18) */ - #define R_PSCU_PSARE_PSARE18_Msk (0x40000UL) /*!< PSARE18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE19_Pos (19UL) /*!< PSARE19 (Bit 19) */ - #define R_PSCU_PSARE_PSARE19_Msk (0x80000UL) /*!< PSARE19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE20_Pos (20UL) /*!< PSARE20 (Bit 20) */ - #define R_PSCU_PSARE_PSARE20_Msk (0x100000UL) /*!< PSARE20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE21_Pos (21UL) /*!< PSARE21 (Bit 21) */ - #define R_PSCU_PSARE_PSARE21_Msk (0x200000UL) /*!< PSARE21 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ - #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ - #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ - #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ - #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ - #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ - #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ - #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ - #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ - #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ - #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE_Pos (0UL) /*!< PSARE (Bit 0) */ + #define R_PSCU_PSARE_PSARE_Msk (0x1UL) /*!< PSARE (Bitfield-Mask: 0x01) */ /* ========================================================= MSSAR ========================================================= */ - #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ - #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ - #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR11_Pos (11UL) /*!< MSSAR11 (Bit 11) */ - #define R_PSCU_MSSAR_MSSAR11_Msk (0x800UL) /*!< MSSAR11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR13_Pos (13UL) /*!< MSSAR13 (Bit 13) */ - #define R_PSCU_MSSAR_MSSAR13_Msk (0x2000UL) /*!< MSSAR13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR15_Pos (15UL) /*!< MSSAR15 (Bit 15) */ - #define R_PSCU_MSSAR_MSSAR15_Msk (0x8000UL) /*!< MSSAR15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR22_Pos (22UL) /*!< MSSAR22 (Bit 22) */ - #define R_PSCU_MSSAR_MSSAR22_Msk (0x400000UL) /*!< MSSAR22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR31_Pos (31UL) /*!< MSSAR31 (Bit 31) */ - #define R_PSCU_MSSAR_MSSAR31_Msk (0x80000000UL) /*!< MSSAR31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR_Pos (0UL) /*!< MSSAR (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR_Msk (0x1UL) /*!< MSSAR (Bitfield-Mask: 0x01) */ /* ========================================================= PPARB ========================================================= */ - #define R_PSCU_PPARB_PPARB4_Pos (4UL) /*!< PPARB4 (Bit 4) */ - #define R_PSCU_PPARB_PPARB4_Msk (0x10UL) /*!< PPARB4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB8_Pos (8UL) /*!< PPARB8 (Bit 8) */ - #define R_PSCU_PPARB_PPARB8_Msk (0x100UL) /*!< PPARB8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB9_Pos (9UL) /*!< PPARB9 (Bit 9) */ - #define R_PSCU_PPARB_PPARB9_Msk (0x200UL) /*!< PPARB9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB11_Pos (11UL) /*!< PPARB11 (Bit 11) */ - #define R_PSCU_PPARB_PPARB11_Msk (0x800UL) /*!< PPARB11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB12_Pos (12UL) /*!< PPARB12 (Bit 12) */ - #define R_PSCU_PPARB_PPARB12_Msk (0x1000UL) /*!< PPARB12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB15_Pos (15UL) /*!< PPARB15 (Bit 15) */ - #define R_PSCU_PPARB_PPARB15_Msk (0x8000UL) /*!< PPARB15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB16_Pos (16UL) /*!< PPARB16 (Bit 16) */ - #define R_PSCU_PPARB_PPARB16_Msk (0x10000UL) /*!< PPARB16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB18_Pos (18UL) /*!< PPARB18 (Bit 18) */ - #define R_PSCU_PPARB_PPARB18_Msk (0x40000UL) /*!< PPARB18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB19_Pos (19UL) /*!< PPARB19 (Bit 19) */ - #define R_PSCU_PPARB_PPARB19_Msk (0x80000UL) /*!< PPARB19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB22_Pos (22UL) /*!< PPARB22 (Bit 22) */ - #define R_PSCU_PPARB_PPARB22_Msk (0x400000UL) /*!< PPARB22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB27_Pos (27UL) /*!< PPARB27 (Bit 27) */ - #define R_PSCU_PPARB_PPARB27_Msk (0x8000000UL) /*!< PPARB27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB28_Pos (28UL) /*!< PPARB28 (Bit 28) */ - #define R_PSCU_PPARB_PPARB28_Msk (0x10000000UL) /*!< PPARB28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB29_Pos (29UL) /*!< PPARB29 (Bit 29) */ - #define R_PSCU_PPARB_PPARB29_Msk (0x20000000UL) /*!< PPARB29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB30_Pos (30UL) /*!< PPARB30 (Bit 30) */ - #define R_PSCU_PPARB_PPARB30_Msk (0x40000000UL) /*!< PPARB30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARB_PPARB31_Pos (31UL) /*!< PPARB31 (Bit 31) */ - #define R_PSCU_PPARB_PPARB31_Msk (0x80000000UL) /*!< PPARB31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB_Pos (0UL) /*!< PPARB (Bit 0) */ + #define R_PSCU_PPARB_PPARB_Msk (0x1UL) /*!< PPARB (Bitfield-Mask: 0x01) */ /* ========================================================= PPARC ========================================================= */ - #define R_PSCU_PPARC_PPARC0_Pos (0UL) /*!< PPARC0 (Bit 0) */ - #define R_PSCU_PPARC_PPARC0_Msk (0x1UL) /*!< PPARC0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC1_Pos (1UL) /*!< PPARC1 (Bit 1) */ - #define R_PSCU_PPARC_PPARC1_Msk (0x2UL) /*!< PPARC1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC7_Pos (7UL) /*!< PPARC7 (Bit 7) */ - #define R_PSCU_PPARC_PPARC7_Msk (0x80UL) /*!< PPARC7 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC8_Pos (8UL) /*!< PPARC8 (Bit 8) */ - #define R_PSCU_PPARC_PPARC8_Msk (0x100UL) /*!< PPARC8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC11_Pos (11UL) /*!< PPARC11 (Bit 11) */ - #define R_PSCU_PPARC_PPARC11_Msk (0x800UL) /*!< PPARC11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC12_Pos (12UL) /*!< PPARC12 (Bit 12) */ - #define R_PSCU_PPARC_PPARC12_Msk (0x1000UL) /*!< PPARC12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC13_Pos (13UL) /*!< PPARC13 (Bit 13) */ - #define R_PSCU_PPARC_PPARC13_Msk (0x2000UL) /*!< PPARC13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC15_Pos (15UL) /*!< PPARC15 (Bit 15) */ - #define R_PSCU_PPARC_PPARC15_Msk (0x8000UL) /*!< PPARC15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC16_Pos (16UL) /*!< PPARC16 (Bit 16) */ - #define R_PSCU_PPARC_PPARC16_Msk (0x10000UL) /*!< PPARC16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC26_Pos (26UL) /*!< PPARC26 (Bit 26) */ - #define R_PSCU_PPARC_PPARC26_Msk (0x4000000UL) /*!< PPARC26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC27_Pos (27UL) /*!< PPARC27 (Bit 27) */ - #define R_PSCU_PPARC_PPARC27_Msk (0x8000000UL) /*!< PPARC27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARC_PPARC31_Pos (31UL) /*!< PPARC31 (Bit 31) */ - #define R_PSCU_PPARC_PPARC31_Msk (0x80000000UL) /*!< PPARC31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARC_PPARC_Pos (0UL) /*!< PPARC (Bit 0) */ + #define R_PSCU_PPARC_PPARC_Msk (0x1UL) /*!< PPARC (Bitfield-Mask: 0x01) */ /* ========================================================= PPARD ========================================================= */ - #define R_PSCU_PPARD_PPARD4_Pos (4UL) /*!< PPARD4 (Bit 4) */ - #define R_PSCU_PPARD_PPARD4_Msk (0x10UL) /*!< PPARD4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD5_Pos (5UL) /*!< PPARD5 (Bit 5) */ - #define R_PSCU_PPARD_PPARD5_Msk (0x20UL) /*!< PPARD5 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD11_Pos (11UL) /*!< PPARD11 (Bit 11) */ - #define R_PSCU_PPARD_PPARD11_Msk (0x800UL) /*!< PPARD11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD12_Pos (12UL) /*!< PPARD12 (Bit 12) */ - #define R_PSCU_PPARD_PPARD12_Msk (0x1000UL) /*!< PPARD12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD13_Pos (13UL) /*!< PPARD13 (Bit 13) */ - #define R_PSCU_PPARD_PPARD13_Msk (0x2000UL) /*!< PPARD13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD14_Pos (14UL) /*!< PPARD14 (Bit 14) */ - #define R_PSCU_PPARD_PPARD14_Msk (0x4000UL) /*!< PPARD14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD15_Pos (15UL) /*!< PPARD15 (Bit 15) */ - #define R_PSCU_PPARD_PPARD15_Msk (0x8000UL) /*!< PPARD15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD16_Pos (16UL) /*!< PPARD16 (Bit 16) */ - #define R_PSCU_PPARD_PPARD16_Msk (0x10000UL) /*!< PPARD16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD20_Pos (20UL) /*!< PPARD20 (Bit 20) */ - #define R_PSCU_PPARD_PPARD20_Msk (0x100000UL) /*!< PPARD20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD22_Pos (22UL) /*!< PPARD22 (Bit 22) */ - #define R_PSCU_PPARD_PPARD22_Msk (0x400000UL) /*!< PPARD22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD27_Pos (27UL) /*!< PPARD27 (Bit 27) */ - #define R_PSCU_PPARD_PPARD27_Msk (0x8000000UL) /*!< PPARD27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARD_PPARD28_Pos (28UL) /*!< PPARD28 (Bit 28) */ - #define R_PSCU_PPARD_PPARD28_Msk (0x10000000UL) /*!< PPARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARD_PPARD_Pos (0UL) /*!< PPARD (Bit 0) */ + #define R_PSCU_PPARD_PPARD_Msk (0x1UL) /*!< PPARD (Bitfield-Mask: 0x01) */ /* ========================================================= PPARE ========================================================= */ - #define R_PSCU_PPARE_PPARE1_Pos (1UL) /*!< PPARE1 (Bit 1) */ - #define R_PSCU_PPARE_PPARE1_Msk (0x2UL) /*!< PPARE1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE2_Pos (2UL) /*!< PPARE2 (Bit 2) */ - #define R_PSCU_PPARE_PPARE2_Msk (0x4UL) /*!< PPARE2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE3_Pos (3UL) /*!< PPARE3 (Bit 3) */ - #define R_PSCU_PPARE_PPARE3_Msk (0x8UL) /*!< PPARE3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE8_Pos (8UL) /*!< PPARE8 (Bit 8) */ - #define R_PSCU_PPARE_PPARE8_Msk (0x100UL) /*!< PPARE8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE9_Pos (9UL) /*!< PPARE9 (Bit 9) */ - #define R_PSCU_PPARE_PPARE9_Msk (0x200UL) /*!< PPARE9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE18_Pos (18UL) /*!< PPARE18 (Bit 18) */ - #define R_PSCU_PPARE_PPARE18_Msk (0x40000UL) /*!< PPARE18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE19_Pos (19UL) /*!< PPARE19 (Bit 19) */ - #define R_PSCU_PPARE_PPARE19_Msk (0x80000UL) /*!< PPARE19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE20_Pos (20UL) /*!< PPARE20 (Bit 20) */ - #define R_PSCU_PPARE_PPARE20_Msk (0x100000UL) /*!< PPARE20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE21_Pos (21UL) /*!< PPARE21 (Bit 21) */ - #define R_PSCU_PPARE_PPARE21_Msk (0x200000UL) /*!< PPARE21 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE22_Pos (22UL) /*!< PPARE22 (Bit 22) */ - #define R_PSCU_PPARE_PPARE22_Msk (0x400000UL) /*!< PPARE22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE23_Pos (23UL) /*!< PPARE23 (Bit 23) */ - #define R_PSCU_PPARE_PPARE23_Msk (0x800000UL) /*!< PPARE23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE24_Pos (24UL) /*!< PPARE24 (Bit 24) */ - #define R_PSCU_PPARE_PPARE24_Msk (0x1000000UL) /*!< PPARE24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE25_Pos (25UL) /*!< PPARE25 (Bit 25) */ - #define R_PSCU_PPARE_PPARE25_Msk (0x2000000UL) /*!< PPARE25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE26_Pos (26UL) /*!< PPARE26 (Bit 26) */ - #define R_PSCU_PPARE_PPARE26_Msk (0x4000000UL) /*!< PPARE26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE27_Pos (27UL) /*!< PPARE27 (Bit 27) */ - #define R_PSCU_PPARE_PPARE27_Msk (0x8000000UL) /*!< PPARE27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE28_Pos (28UL) /*!< PPARE28 (Bit 28) */ - #define R_PSCU_PPARE_PPARE28_Msk (0x10000000UL) /*!< PPARE28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE29_Pos (29UL) /*!< PPARE29 (Bit 29) */ - #define R_PSCU_PPARE_PPARE29_Msk (0x20000000UL) /*!< PPARE29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE30_Pos (30UL) /*!< PPARE30 (Bit 30) */ - #define R_PSCU_PPARE_PPARE30_Msk (0x40000000UL) /*!< PPARE30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PPARE_PPARE31_Pos (31UL) /*!< PPARE31 (Bit 31) */ - #define R_PSCU_PPARE_PPARE31_Msk (0x80000000UL) /*!< PPARE31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE_Pos (0UL) /*!< PPARE (Bit 0) */ + #define R_PSCU_PPARE_PPARE_Msk (0x1UL) /*!< PPARE (Bitfield-Mask: 0x01) */ /* ========================================================= MSPAR ========================================================= */ - #define R_PSCU_MSPAR_MSPAR31_Pos (31UL) /*!< MSPAR31 (Bit 31) */ - #define R_PSCU_MSPAR_MSPAR31_Msk (0x80000000UL) /*!< MSPAR31 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSPAR_MSPAR_Pos (0UL) /*!< MSPAR (Bit 0) */ + #define R_PSCU_MSPAR_MSPAR_Msk (0x1UL) /*!< MSPAR (Bitfield-Mask: 0x01) */ /* ======================================================= CFSAMONA ======================================================== */ - #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ - #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ /* ======================================================== DFSAMON ======================================================== */ - #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ - #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ /* ======================================================== DLMMON ========================================================= */ - #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ - #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ /* =========================================================================================================================== */ /* ================ R_BUS ================ */ @@ -22327,6 +22429,9 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -22808,6 +22913,11 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -22923,30 +23033,49 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ /* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ @@ -24130,10 +24259,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ - #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ - #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ @@ -24784,6 +24909,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ /* ========================================================= BSTE ========================================================== */ #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ @@ -24799,6 +24926,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ /* ========================================================== BIE ========================================================== */ #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ @@ -24814,6 +24943,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ /* ========================================================= BSTFC ========================================================= */ #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ @@ -24829,6 +24960,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ /* ========================================================= NTST ========================================================== */ #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ @@ -25031,6 +25164,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT1 ========================================================= */ @@ -25042,6 +25179,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT2 ========================================================= */ @@ -25053,6 +25194,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================== MSDCT3 ========================================================= */ @@ -25064,6 +25209,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ @@ -25077,6 +25226,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ /* ======================================================= SDCTPIDL ======================================================== */ @@ -25138,6 +25291,13 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ /* ======================================================== BITCNT ========================================================= */ #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ @@ -25228,10 +25388,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* =========================================================================================================================== */ /* ======================================================== PCNTR1 ========================================================= */ - #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ - #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ /* ========================================================== PDR ========================================================== */ #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ @@ -25239,10 +25399,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ /* ======================================================== PCNTR2 ========================================================= */ - #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ - #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ /* ========================================================= PIDR ========================================================== */ #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ @@ -25250,10 +25410,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ /* ======================================================== PCNTR3 ========================================================= */ - #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ - #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ /* ========================================================= POSR ========================================================== */ #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ @@ -25261,10 +25421,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ /* ======================================================== PCNTR4 ========================================================= */ - #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ - #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ /* ========================================================= EOSR ========================================================== */ #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ @@ -25283,6 +25443,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================== PFENET ========================================================= */ #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ /* ========================================================= PWPR ========================================================== */ #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ @@ -25299,20 +25461,10 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* =========================================================================================================================== */ /* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ - #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ - #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ - #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ - #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ - #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ - #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ - #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ /* ========================================================= BCNT0 ========================================================= */ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ @@ -26530,8 +26682,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================= SCKDIVCR2 ======================================================= */ #define R_SYSTEM_SCKDIVCR2_CPUCK_Pos (0UL) /*!< CPUCK (Bit 0) */ #define R_SYSTEM_SCKDIVCR2_CPUCK_Msk (0xfUL) /*!< CPUCK (Bitfield-Mask: 0x0f) */ - #define R_SYSTEM_SCKDIVCR2_CPUCK1_Pos (4UL) /*!< CPUCK1 (Bit 4) */ - #define R_SYSTEM_SCKDIVCR2_CPUCK1_Msk (0xf0UL) /*!< CPUCK1 (Bitfield-Mask: 0x0f) */ /* ======================================================== SCKSCR ========================================================= */ #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ @@ -26776,8 +26926,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_SYSTEM_RSTSR1_CMRF_Msk (0x4000UL) /*!< CMRF (Bitfield-Mask: 0x01) */ #define R_SYSTEM_RSTSR1_WDT1RF_Pos (17UL) /*!< WDT1RF (Bit 17) */ #define R_SYSTEM_RSTSR1_WDT1RF_Msk (0x20000UL) /*!< WDT1RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_CLU1RF_Pos (20UL) /*!< CLU1RF (Bit 20) */ - #define R_SYSTEM_RSTSR1_CLU1RF_Msk (0x100000UL) /*!< CLU1RF (Bitfield-Mask: 0x01) */ #define R_SYSTEM_RSTSR1_LM1RF_Pos (21UL) /*!< LM1RF (Bit 21) */ #define R_SYSTEM_RSTSR1_LM1RF_Msk (0x200000UL) /*!< LM1RF (Bitfield-Mask: 0x01) */ #define R_SYSTEM_RSTSR1_NWRF_Pos (22UL) /*!< NWRF (Bit 22) */ @@ -27292,10 +27440,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_SYSTEM_SYRSTMSK0_BUSMASK_Pos (7UL) /*!< BUSMASK (Bit 7) */ #define R_SYSTEM_SYRSTMSK0_BUSMASK_Msk (0x80UL) /*!< BUSMASK (Bitfield-Mask: 0x01) */ /* ======================================================= SYRSTMSK1 ======================================================= */ - #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Pos (1UL) /*!< WDT1MASK (Bit 1) */ - #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Msk (0x2UL) /*!< WDT1MASK (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SYRSTMSK1_CLUP1MASK_Pos (4UL) /*!< CLUP1MASK (Bit 4) */ - #define R_SYSTEM_SYRSTMSK1_CLUP1MASK_Msk (0x10UL) /*!< CLUP1MASK (Bitfield-Mask: 0x01) */ #define R_SYSTEM_SYRSTMSK1_LM1MASK_Pos (5UL) /*!< LM1MASK (Bit 5) */ #define R_SYSTEM_SYRSTMSK1_LM1MASK_Msk (0x20UL) /*!< LM1MASK (Bitfield-Mask: 0x01) */ #define R_SYSTEM_SYRSTMSK1_NWMASK_Pos (7UL) /*!< NWMASK (Bit 7) */ @@ -28458,6 +28602,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ @@ -28481,6 +28627,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ @@ -28504,18 +28652,39 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================== ICUSARI ======================================================== */ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARA ======================================================== */ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ /* ======================================================== BUSSARB ======================================================== */ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ /* ======================================================= MMPUSARA ======================================================== */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ /* ======================================================= DMACCHSAR ======================================================= */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h index b47f5443e..4526aabb6 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h @@ -25,19 +25,8 @@ extern "C" { #endif -/* Workaround for LLVM. __ARM_ARCH_8_1M_MAIN__ is defined for CM85 parts. But CMSIS_5 does not support this */ - #if defined(__llvm__) && !defined(__CLANG_TIDY__) && defined(__ARM_ARCH_8_1M_MAIN__) - #undef __ARM_ARCH_8_1M_MAIN__ - #define __ARM_ARCH_8M_MAIN__ 1 - #endif #include "cmsis_compiler.h" -/* Workaround for compilers that are not defining __ARM_ARCH_8_1M_MAIN__ for CM85 parts. Search CM85_WORKAROUND for related code changes */ - #if BSP_CFG_MCU_PART_SERIES == 8 - #undef __ARM_ARCH_8M_MAIN__ - #define __ARM_ARCH_8_1M_MAIN__ 1 - #endif - /** @addtogroup Configuration_of_CMSIS * @{ */ @@ -115,15 +104,36 @@ extern "C" { #endif #endif - #if __ARM_ARCH_7EM__ +/* + * ARM has advised to no longer use the __ARM_ARCH_8_1M_MAIN__ type macro and to instead use the __ARM_ARCH and __ARM_ARCH_ISA_THUMB + * macros for differentiating architectures. However, with all of our toolchains, neither paradigm is being correctly produced for Cortex-M85 + * and thus we still need a workaround. Below is a summary of the current macros produced by each toolchain for CM85: + * + * | Toolchain | __ARM_ARCH | _ARM_ARCH_xx__ | + * |-----------|------------|------------------------| + * | GCC | 8 | __ARM_ARCH_8M_MAIN__ | + * | LLVM | 8 | __ARM_ARCH_8_1M_MAIN__ | + * | AC6 | 8 | __ARM_ARCH_8_1M_MAIN__ | + * | IAR | 801 | __ARM_ARCH_8M_MAIN__ | + * + * The expected output for CM85 should be __ARM_ARCH == 801, __ARM_ARCH_ISA_THUMB == 2, and __ARM_ARCH_8_1M_MAIN__ + * + * IAR is currently the only toolchain producing the correct __ARM_ARCH value. + * + *- See https://github.com/ARM-software/CMSIS_6/issues/159 + */ + #if BSP_CFG_MCU_PART_SERIES == 8 && !defined(__ICCARM__) && BSP_CFG_CPU_CORE != 1 + #undef __ARM_ARCH + #define __ARM_ARCH 801 + #endif + + #if (__ARM_ARCH == 7) && (__ARM_ARCH_ISA_THUMB == 2) #define RENESAS_CORTEX_M4 - #elif __ARM_ARCH_6M__ - #define RENESAS_CORTEX_M0PLUS - #elif __ARM_ARCH_8M_BASE__ + #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 1) #define RENESAS_CORTEX_M23 - #elif __ARM_ARCH_8M_MAIN__ + #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 2) #define RENESAS_CORTEX_M33 - #elif __ARM_ARCH_8_1M_MAIN__ + #elif (__ARM_ARCH == 801) && (__ARM_ARCH_ISA_THUMB == 2) #define RENESAS_CORTEX_M85 #else #warning Unsupported Architecture diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c index 01fdf6616..283173aaa 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c @@ -16,6 +16,11 @@ #if defined(__GNUC__) && defined(__llvm__) && !defined(__ARMCC_VERSION) && !defined(__CLANG_TIDY__) #include #endif +#if defined(__ARMCC_VERSION) + #if defined(__ARMCC_USING_STANDARDLIB) + #include + #endif +#endif #include "bsp_api.h" /*********************************************************************************************************************** @@ -58,8 +63,10 @@ extern uint32_t Image$$BSS$$ZI$$Length; extern uint32_t Load$$DATA$$Base; extern uint32_t Image$$DATA$$Base; extern uint32_t Image$$DATA$$Length; -extern uint32_t Image$$STACK$$ZI$$Base; -extern uint32_t Image$$STACK$$ZI$$Length; + #if defined(__ARMCC_USING_STANDARDLIB) +extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base; +extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Length; + #endif #if BSP_FEATURE_BSP_HAS_ITCM extern uint32_t Load$$ITCM_DATA$$Base; extern uint32_t Load$$ITCM_PAD$$Limit; @@ -134,6 +141,7 @@ extern uint32_t NOCACHE$$Limit; extern uint32_t NOCACHE_SDRAM$$Base; extern uint32_t NOCACHE_SDRAM$$Limit; #endif + #endif /* Initialize static constructors */ @@ -212,7 +220,7 @@ static void bsp_init_mpu(void); /*******************************************************************************************************************//** * Initialize the MCU and the runtime environment. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void SystemInit (void) +void SystemInit (void) { #if defined(RENESAS_CORTEX_M85) @@ -262,7 +270,7 @@ BSP_SECTION_FLASH_GAP void SystemInit (void) SCB->VTOR = (uint32_t) &__Vectors; #endif -#if !BSP_TZ_CFG_SKIP_INIT +#if !BSP_TZ_CFG_SKIP_INIT && !BSP_CFG_SKIP_INIT #if BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP /* Unlock VBTCR1 register. */ @@ -299,10 +307,19 @@ BSP_SECTION_FLASH_GAP void SystemInit (void) /* Call pre clock initialization hook. */ R_BSP_WarmStart(BSP_WARM_START_RESET); -#if BSP_TZ_CFG_SKIP_INIT +#if BSP_TZ_CFG_SKIP_INIT || BSP_CFG_SKIP_INIT /* Initialize clock variables to be used with R_BSP_SoftwareDelay. */ bsp_clock_freq_var_init(); + + #if BSP_CFG_SKIP_INIT && (defined(R_CACHE) || BSP_FEATURE_BSP_FLASH_CACHE) + + /* Flush cache before enabling */ + R_CACHE->CCAFCT_b.FC = 1; + + /* Enable cache */ + R_BSP_FlashCacheEnable(); + #endif #else /* Configure system clocks. */ @@ -404,6 +421,10 @@ BSP_SECTION_FLASH_GAP void SystemInit (void) /* Initialize static constructors */ #if defined(__ARMCC_VERSION) + #if defined(__ARMCC_USING_STANDARDLIB) + __rt_lib_init((uint32_t) &Image$$ARM_LIB_HEAP$$ZI$$Base, + (uint32_t) &Image$$ARM_LIB_HEAP$$ZI$$Base + (uint32_t) &Image$$ARM_LIB_HEAP$$ZI$$Length); + #else int32_t count = Image$$INIT_ARRAY$$Limit - Image$$INIT_ARRAY$$Base; for (int32_t i = 0; i < count; i++) { @@ -411,7 +432,7 @@ BSP_SECTION_FLASH_GAP void SystemInit (void) (void (*)(void))((uint32_t) &Image$$INIT_ARRAY$$Base + (uint32_t) Image$$INIT_ARRAY$$Base[i]); p_init_func(); } - + #endif #elif defined(__GNUC__) int32_t count = __init_array_end - __init_array_start; for (int32_t i = 0; i < count; i++) @@ -432,14 +453,14 @@ BSP_SECTION_FLASH_GAP void SystemInit (void) #if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR /* For TZ project, it should be called by the secure application, whether RTC module is to be configured as secure or not. */ - #if !BSP_TZ_NONSECURE_BUILD && !BSP_CFG_BOOT_IMAGE + #if !BSP_TZ_NONSECURE_BUILD && !BSP_CFG_BOOT_IMAGE && !BSP_CFG_SKIP_INIT /* Perform RTC reset sequence to avoid unintended operation. */ R_BSP_Init_RTC(); #endif #endif -#if !BSP_CFG_PFS_PROTECT +#if !BSP_CFG_PFS_PROTECT && defined(R_PMISC) && !BSP_CFG_SKIP_INIT #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled @@ -449,7 +470,7 @@ BSP_SECTION_FLASH_GAP void SystemInit (void) #endif #endif -#if FSP_PRIV_TZ_USE_SECURE_REGS +#if FSP_PRIV_TZ_USE_SECURE_REGS && !BSP_CFG_SKIP_INIT /* Ensure that the PMSAR registers are set to their default value. */ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); @@ -488,7 +509,7 @@ BSP_SECTION_FLASH_GAP void SystemInit (void) SCB_EnableDCache(); #endif -#if BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN +#if BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN && !BSP_CFG_SKIP_INIT if ((((0 == R_SYSTEM->PGCSAR) && FSP_PRIV_TZ_USE_SECURE_REGS) || ((1 == R_SYSTEM->PGCSAR) && BSP_TZ_NONSECURE_BUILD)) && (0 != R_SYSTEM->PDCTRGD)) { @@ -503,6 +524,10 @@ BSP_SECTION_FLASH_GAP void SystemInit (void) } #endif +#if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS && !BSP_CFG_SKIP_INIT + bsp_internal_prv_enable_extra_power_domain(); +#endif + /* Call Post C runtime initialization hook. */ R_BSP_WarmStart(BSP_WARM_START_POST_C); @@ -617,7 +642,6 @@ static void bsp_init_uninitialized_vars (void) #endif #if BSP_CFG_C_RUNTIME_INIT - #if (BSP_FEATURE_BSP_HAS_ITCM || BSP_FEATURE_BSP_HAS_DTCM) /*******************************************************************************************************************//** @@ -685,11 +709,9 @@ static void memset_64 (uint64_t * destination, const uint64_t value, size_t coun } #endif - #endif #if BSP_CFG_C_RUNTIME_INIT - #if BSP_FEATURE_BSP_HAS_ITCM /*******************************************************************************************************************//** @@ -759,7 +781,6 @@ static void bsp_init_dtcm (void) } #endif - #endif #if BSP_CFG_DCACHE_ENABLED diff --git a/ra/board/ra8d1_ek/board_sdram.h b/ra/fsp/src/bsp/mcu/all/board_sdram.h similarity index 73% rename from ra/board/ra8d1_ek/board_sdram.h rename to ra/fsp/src/bsp/mcu/all/board_sdram.h index 1eabd492c..5f614bcbb 100644 --- a/ra/board/ra8d1_ek/board_sdram.h +++ b/ra/fsp/src/bsp/mcu/all/board_sdram.h @@ -7,10 +7,6 @@ #ifndef BOARD_SDRAM_H #define BOARD_SDRAM_H -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ @@ -20,13 +16,17 @@ **********************************************************************************************************************/ /*********************************************************************************************************************** - * Exported global variables (to be accessed by other files) + * Exported global variables **********************************************************************************************************************/ -void bsp_sdram_init(void); - /*********************************************************************************************************************** - * Private global variables and functions + * Exported global functions (to be accessed by other files) **********************************************************************************************************************/ +/* DEPRECATED: This is a temporary alias to the new SDRAM support in bsp_sdram.c. It will be removed in FSP v6.0.0. + * It is only present if the new support has not been enabled. */ +#if 1 != BSP_CFG_SDRAM_ENABLED + #define bsp_sdram_init() R_BSP_SdramInit(true) +#endif + #endif diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c index 325473227..5f42b4f5c 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c @@ -22,6 +22,9 @@ #define BSP_PRV_PRCR_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x3U) #define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) +/* Key code for writing LSMRWDIS register. */ +#define BSP_PRV_LSMRDIS_KEY (0xA500U) + /* Wait state definitions for MEMWAIT. */ #define BSP_PRV_MEMWAIT_ZERO_WAIT_CYCLES (0U) #define BSP_PRV_MEMWAIT_ONE_WAIT_CYCLES (1U) @@ -50,6 +53,13 @@ #define BSP_PRV_SRAM_LOCK (((BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE) << \ BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET) | 0x0U) +/* Determine whether SRAM wait states should be enabled */ +#if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS + #define BSP_PRV_SRAM_WAIT_CYCLES BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE +#else + #define BSP_PRV_SRAM_WAIT_CYCLES BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE +#endif + /* Calculate value to write to MOMCR/CMC (MODRV controls main clock drive strength and MOSEL determines the source of the * main oscillator). */ #if BSP_FEATURE_CGC_MODRV_MASK @@ -131,6 +141,10 @@ #define BSP_PRV_UCK_DIV (3U) #elif BSP_CLOCKS_USB_CLOCK_DIV_8 == BSP_CFG_UCK_DIV #define BSP_PRV_UCK_DIV (4U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_10 == BSP_CFG_UCK_DIV + #define BSP_PRV_UCK_DIV (7U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_16 == BSP_CFG_UCK_DIV + #define BSP_PRV_UCK_DIV (8U) #else #error "BSP_CFG_UCK_DIV not supported." @@ -138,94 +152,100 @@ #endif #endif #endif -#if BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ - #define BSP_CLOCKS_USB60_CLOCK_DIV_1 (0) // Divide USB source clock by 1 - #define BSP_CLOCKS_USB60_CLOCK_DIV_2 (1) // Divide USB source clock by 2 - #define BSP_CLOCKS_USB60_CLOCK_DIV_3 (5) // Divide USB source clock by 3 - #define BSP_CLOCKS_USB60_CLOCK_DIV_4 (2) // Divide USB source clock by 4 - #define BSP_CLOCKS_USB60_CLOCK_DIV_5 (6) // Divide USB source clock by 5 - #define BSP_CLOCKS_USB60_CLOCK_DIV_6 (3) // Divide USB source clock by 6 - #define BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) // Divide USB source clock by 8 -#endif /* BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ*/ + /* Choose the value to write to FLLCR2 (if applicable). */ #if BSP_PRV_HOCO_USE_FLL #if 1U == BSP_CFG_HOCO_FREQUENCY - #define BSP_PRV_FLL_FLLCR2 (0x226U) + #define BSP_PRV_FLL_FLLCR2 (0x226U) #elif 2U == BSP_CFG_HOCO_FREQUENCY - #define BSP_PRV_FLL_FLLCR2 (0x263U) + #define BSP_PRV_FLL_FLLCR2 (0x263U) #elif 4U == BSP_CFG_HOCO_FREQUENCY - #define BSP_PRV_FLL_FLLCR2 (0x263U) + #define BSP_PRV_FLL_FLLCR2 (0x263U) #else /* When BSP_CFG_HOCO_FREQUENCY is 0, 4, 7 */ - #define BSP_PRV_FLL_FLLCR2 (0x1E9U) + #define BSP_PRV_FLL_FLLCR2 (0x1E9U) #endif #endif /* Calculate the value to write to SCKDIVCR. */ -#define BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS ((BSP_CFG_ICLK_DIV & 0xFU) << 24U) +#define BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS ((BSP_CFG_ICLK_DIV & 0xFU) << 24U) #if BSP_FEATURE_CGC_HAS_PCLKE - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS ((BSP_CFG_PCLKE_DIV & 0xFU) << 20U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS ((BSP_CFG_PCLKE_DIV & 0xFU) << 20U) #else - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS (0U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS (0U) #endif #if BSP_FEATURE_CGC_HAS_PCLKD - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (BSP_CFG_PCLKD_DIV & 0xFU) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (BSP_CFG_PCLKD_DIV & 0xFU) #else - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (0U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (0U) #endif #if BSP_FEATURE_CGC_HAS_PCLKC - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS ((BSP_CFG_PCLKC_DIV & 0xFU) << 4U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS ((BSP_CFG_PCLKC_DIV & 0xFU) << 4U) #else - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS (0U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS (0U) #endif #if BSP_FEATURE_CGC_HAS_PCLKB - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 8U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 8U) #else - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS (0U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS (0U) #endif #if BSP_FEATURE_CGC_HAS_PCLKA - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS ((BSP_CFG_PCLKA_DIV & 0xFU) << 12U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS ((BSP_CFG_PCLKA_DIV & 0xFU) << 12U) #else - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS (0U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS (0U) #endif #if BSP_FEATURE_CGC_HAS_BCLK - #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_BCLK_DIV & 0xFU) << 16U) + #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_BCLK_DIV & 0xFU) << 16U) #elif BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB /* Some MCUs have a requirement that bits 18-16 be set to the same value as the bits for configuring the PCLKB divisor. */ - #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 16U) + #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 16U) #else - #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS (0U) + #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS (0U) #endif #if BSP_FEATURE_CGC_HAS_FCLK - #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS ((BSP_CFG_FCLK_DIV & 0xFU) << 28U) + #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS ((BSP_CFG_FCLK_DIV & 0xFU) << 28U) #else - #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS (0U) -#endif -#define BSP_PRV_STARTUP_SCKDIVCR (BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS | \ - BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS | \ - BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS | \ - BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS | \ - BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS | \ - BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS | \ - BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS | \ - BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS) + #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS (0U) +#endif +#define BSP_PRV_STARTUP_SCKDIVCR (BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS) #if BSP_FEATURE_CGC_HAS_CPUCLK - #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (BSP_CFG_CPUCLK_DIV & 0xFU) - #define BSP_PRV_STARTUP_SCKDIVCR2 (BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS) + #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (BSP_CFG_CPUCLK_DIV & 0xFU) +#else + #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (0) +#endif +#if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + #define BSP_PRV_STARTUP_SCKDIVCR2_EXTRACK1_BITS ((BSP_CFG_EXTRACLK1_DIV & 0xFU) << 4U) + #define BSP_PRV_STARTUP_SCKDIVCR2_EXTRACK2_BITS ((BSP_CFG_EXTRACLK2_DIV & 0xFU) << 8U) + #define BSP_PRV_STARTUP_SCKDIVCR2_EXTRACK3_BITS ((BSP_CFG_EXTRACLK3_DIV & 0xFU) << 12U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR2_EXTRACK1_BITS (0) + #define BSP_PRV_STARTUP_SCKDIVCR2_EXTRACK2_BITS (0) + #define BSP_PRV_STARTUP_SCKDIVCR2_EXTRACK3_BITS (0) #endif +#define BSP_PRV_STARTUP_SCKDIVCR2 (BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR2_EXTRACK1_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR2_EXTRACK2_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR2_EXTRACK3_BITS) /* The number of clocks is used to size the g_clock_freq array. */ #if BSP_PRV_PLL2_SUPPORTED - #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL2 + \ - (BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS - 1) + \ - BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS) + #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL2 + \ + (BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS - 1) + \ + BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS) #elif BSP_PRV_PLL_SUPPORTED - #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL + \ - BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS) + #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL + \ + BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS) #else - #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK + 1U) + #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK + 1U) #endif /* Calculate PLLCCR value. */ @@ -262,7 +282,7 @@ #define BSP_PRV_PLLCCR ((BSP_PRV_PLLCCR2_PLLMUL & BSP_PRV_PLLCCR2_PLLMUL_MASK) | \ (BSP_CFG_PLL_DIV << BSP_PRV_PLLCCR2_PLODIV_BIT)) #endif - #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE #define BSP_PRV_PLSRCSEL (0) #define BSP_PRV_PLL_USED (1) @@ -347,7 +367,7 @@ #define BSP_PRV_PLL2_USED (0) #endif - #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) #define BSP_PRV_PLL2_MUL_CFG_MACRO_PLLMUL_MASK (0x3FF) #define BSP_PRV_PLL2_MUL_CFG_MACRO_PLLMULNF_MASK (0x003U) #define BSP_PRV_PLL2CCR_PLLMULNF_BIT (6) // PLLMULNF in PLLCCR starts at bit 6 @@ -419,6 +439,8 @@ #define BSP_PRV_MAIN_OSC_USED (1) #elif defined(BSP_CFG_UARTA_CLOCK_SOURCE) && (BSP_CFG_UARTA_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) #elif defined(BSP_CFG_TML_FITL0_SOURCE) && (BSP_CFG_TML_FITL0_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) #define BSP_PRV_MAIN_OSC_USED (1) #elif defined(BSP_CFG_TML_FITL1_SOURCE) && (BSP_CFG_TML_FITL1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) @@ -464,6 +486,8 @@ #define BSP_PRV_HOCO_USED (1) #elif defined(BSP_CFG_UARTA_CLOCK_SOURCE) && (BSP_CFG_UARTA_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_HOCO) #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_HOCO) + #define BSP_PRV_HOCO_USED (1) #elif defined(BSP_CFG_TML_FITL0_SOURCE) && (BSP_CFG_TML_FITL0_SOURCE == BSP_CLOCKS_SOURCE_HOCO) #define BSP_PRV_HOCO_USED (1) #elif defined(BSP_CFG_TML_FITL1_SOURCE) && (BSP_CFG_TML_FITL1_SOURCE == BSP_CLOCKS_SOURCE_HOCO) @@ -503,6 +527,8 @@ #define BSP_PRV_MOCO_USED (1) #elif defined(BSP_CFG_UARTA_CLOCK_SOURCE) && (BSP_CFG_UARTA_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) #elif defined(BSP_CFG_TML_FITL0_SOURCE) && (BSP_CFG_TML_FITL0_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) #define BSP_PRV_MOCO_USED (1) #elif defined(BSP_CFG_TML_FITL1_SOURCE) && (BSP_CFG_TML_FITL1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) @@ -534,6 +560,10 @@ #elif (defined(BSP_CFG_UARTA_CLOCK_SOURCE) && (BSP_CFG_UARTA_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_FSXP)) && \ (defined(BSP_CFG_FSXP_SOURCE) && (BSP_CFG_FSXP_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)) #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_UARTA_CLOCK_SOURCE) && (BSP_CFG_UARTA_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) #elif (defined(BSP_CFG_FSXP_SOURCE) && (BSP_CFG_FSXP_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)) #define BSP_PRV_LOCO_USED (1) #else @@ -562,18 +592,21 @@ (BSP_FEATURE_BSP_HAS_SCISPI_CLOCK && (BSP_CFG_SCISPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ (BSP_FEATURE_BSP_HAS_SCI_CLOCK && (BSP_CFG_SCICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ (BSP_FEATURE_BSP_HAS_SPI_CLOCK && (BSP_CFG_SPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ - (BSP_FEATURE_BSP_HAS_GPT_CLOCK && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_PERIPHERAL_GPT_GTCLK_PRESENT && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ (BSP_FEATURE_BSP_HAS_IIC_CLOCK && (BSP_CFG_IICCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ (BSP_FEATURE_BSP_HAS_CEC_CLOCK && (BSP_CFG_CECCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ (BSP_FEATURE_BSP_HAS_I3C_CLOCK && (BSP_CFG_I3CCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ - (BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ && (BSP_CFG_U60CK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ - (BSP_FEATURE_BSP_HAS_LCD_CLOCK && (BSP_CFG_LCDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) + (BSP_FEATURE_BSP_HAS_USB60_CLOCK && (BSP_CFG_U60CK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_BSP_HAS_LCD_CLOCK && (BSP_CFG_LCDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_BSP_HAS_ADC_CLOCK && (BSP_CFG_ADCCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) #define BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS (1U) #else #define BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS (0U) #endif +#define BSP_PRV_HZ_PER_MHZ (1000000) + /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ @@ -598,7 +631,7 @@ static void bsp_clock_set_memwait(uint32_t updated_freq_hz); static void bsp_prv_operating_mode_opccr_set(uint8_t operating_mode); #endif -void prv_clock_dividers_set(uint32_t sckdivcr, uint8_t sckdivcr2); +void prv_clock_dividers_set(uint32_t sckdivcr, uint16_t sckdivcr2); #else static void bsp_prv_cmc_init(void); @@ -888,7 +921,7 @@ void bsp_prv_prepare_pll (uint32_t clock, uint32_t const * const p_pll_hz) /*******************************************************************************************************************//** * Update SystemCoreClock variable based on current clock settings. **********************************************************************************************************************/ -void SystemCoreClockUpdate (void) +BSP_SECTION_FLASH_GAP void SystemCoreClockUpdate (void) { #if !BSP_FEATURE_CGC_REGISTER_SET_B #if BSP_FEATURE_TZ_HAS_TRUSTZONE && (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2 @@ -902,8 +935,13 @@ void SystemCoreClockUpdate (void) (FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, secure) & R_SYSTEM_SCKDIVCR_ICK_Msk) >> R_SYSTEM_SCKDIVCR_ICK_Pos; SystemCoreClock = g_clock_freq[clock_index] >> ick; #else + #if BSP_ALT_BUILD + uint8_t cpuck = (FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, secure) & BSP_INTERNAL_SCKDIVCR2_EXTRACK1_MASK) >> + BSP_INTERNAL_SCKDIVCR2_EXTRACK1_POS; + #else uint8_t cpuck = (FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, secure) & R_SYSTEM_SCKDIVCR2_CPUCK_Msk) >> R_SYSTEM_SCKDIVCR2_CPUCK_Pos; + #endif uint8_t cpuclk_div = cpuck; if (8U == cpuclk_div) @@ -918,6 +956,10 @@ void SystemCoreClockUpdate (void) { SystemCoreClock = g_clock_freq[clock_index] / 12U; } + else if (11U == cpuclk_div) + { + SystemCoreClock = g_clock_freq[clock_index] / 24U; + } else { SystemCoreClock = g_clock_freq[clock_index] >> cpuclk_div; @@ -1033,25 +1075,31 @@ void bsp_prv_power_change_mstp_clear (uint32_t mstp_clear_bitmask) * @param[in] sckdivcr The new SCKDIVCR setting. * @param[in] sckdivcr2 The new SCKDIVCR2 setting. **********************************************************************************************************************/ -void prv_clock_dividers_set (uint32_t sckdivcr, uint8_t sckdivcr2) +void prv_clock_dividers_set (uint32_t sckdivcr, uint16_t sckdivcr2) { #if BSP_FEATURE_CGC_HAS_CPUCLK uint32_t requested_iclk_div = BSP_PRV_SCKDIVCR_DIV_VALUE( (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK); uint32_t current_iclk_div = BSP_PRV_SCKDIVCR_DIV_VALUE(R_SYSTEM->SCKDIVCR_b.ICK); + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + uint16_t temp_sckdivcr2 = sckdivcr2; + #else + uint8_t temp_sckdivcr2 = ((uint8_t) sckdivcr2) & R_SYSTEM_SCKDIVCR2_CPUCK_Msk; + #endif + if (requested_iclk_div >= current_iclk_div) { /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ R_SYSTEM->SCKDIVCR = sckdivcr; - R_SYSTEM->SCKDIVCR2 = sckdivcr2; + R_SYSTEM->SCKDIVCR2 = temp_sckdivcr2; } else { /* If the requested ICLK divider is less than the current ICLK divider, then writing to SCKDIVCR2 first * will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ - R_SYSTEM->SCKDIVCR2 = sckdivcr2; + R_SYSTEM->SCKDIVCR2 = temp_sckdivcr2; R_SYSTEM->SCKDIVCR = sckdivcr; } @@ -1070,7 +1118,7 @@ void prv_clock_dividers_set (uint32_t sckdivcr, uint8_t sckdivcr2) * @param[in] sckdivcr Value to set in SCKDIVCR register * @param[in] sckdivcr2 Value to set in SCKDIVCR2 register **********************************************************************************************************************/ -void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2) +void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint16_t sckdivcr2) { #if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED @@ -1092,9 +1140,29 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2) * set is higher than before. */ uint8_t new_rom_wait_state = bsp_clock_set_prechange(iclk_freq_hz_post_change); + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + uint32_t extraclk1_div = (sckdivcr2 & BSP_INTERNAL_SCKDIVCR2_EXTRACK1_MASK) >> + BSP_INTERNAL_SCKDIVCR2_EXTRACK1_POS; + uint32_t extraclk2_div = (sckdivcr2 & BSP_INTERNAL_SCKDIVCR2_EXTRACK2_MASK) >> + BSP_INTERNAL_SCKDIVCR2_EXTRACK2_POS; + uint32_t extraclk3_div = (sckdivcr2 & BSP_INTERNAL_SCKDIVCR2_EXTRACK3_MASK) >> + BSP_INTERNAL_SCKDIVCR2_EXTRACK3_POS; + + uint32_t extraclk3_freq_mhz_post_change = g_clock_freq[clock] / BSP_PRV_SCKDIVCR_DIV_VALUE(extraclk3_div) / + BSP_PRV_HZ_PER_MHZ; + + /* Clear the PFB before doing any clock changes according to Frequency Change Procedure. */ + bsp_internal_prv_clear_pfb(); + #endif + /* Switching to a faster source clock. */ if (g_clock_freq[clock] >= g_clock_freq[R_SYSTEM->SCKSCR]) { + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* New source clock will be faster so set wait state frequency according to Frequency Change Procedure. */ + bsp_internal_prv_set_wait_state_frequency(extraclk3_freq_mhz_post_change); + #endif #if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE bool post_div_set_delay = false; @@ -1103,7 +1171,8 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2) { /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ - if (iclk_div == sckdivcr2) + + if (iclk_div == cpuclk_div) { /* If dividers are equal, bump both down 1 notch. * /1 and /2 are the only possible options. */ @@ -1115,21 +1184,77 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2) R_SYSTEM->SCKDIVCR = (sckdivcr & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | (new_div << R_SYSTEM_SCKDIVCR_ICK_Pos); + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* Bump down dividers to new_div for other sckdivcr2 dividers if needed. */ + uint32_t new_extraclk1_div = (extraclk1_div < new_div) ? new_div : extraclk1_div; + uint32_t new_extraclk2_div = (extraclk2_div < new_div) ? new_div : extraclk2_div; + uint32_t new_extraclk3_div = (extraclk3_div < new_div) ? new_div : extraclk3_div; + + R_SYSTEM->SCKDIVCR2 = + (uint16_t) (new_div | (new_extraclk1_div << BSP_INTERNAL_SCKDIVCR2_EXTRACK1_POS) | + (new_extraclk2_div << BSP_INTERNAL_SCKDIVCR2_EXTRACK2_POS) | + (new_extraclk3_div << BSP_INTERNAL_SCKDIVCR2_EXTRACK3_POS)); + #else R_SYSTEM->SCKDIVCR2 = (uint8_t) new_div; + #endif } else { R_SYSTEM->SCKDIVCR = sckdivcr; if (cpuclk_div == BSP_CLOCKS_SYS_CLOCK_DIV_1) { + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* Determine what the other dividers are using and stay aligned with that. */ + uint32_t new_cpuclk0_div = + (iclk_div & 0x8) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + + /* Bump down dividers to new_div for other sckdivcr2 dividers if needed. */ + uint32_t new_extraclk1_div = + (extraclk1_div < new_cpuclk0_div) ? new_cpuclk0_div : extraclk1_div; + uint32_t new_extraclk2_div = + (extraclk2_div < new_cpuclk0_div) ? new_cpuclk0_div : extraclk2_div; + uint32_t new_extraclk3_div = + (extraclk3_div < new_cpuclk0_div) ? new_cpuclk0_div : extraclk3_div; + + R_SYSTEM->SCKDIVCR2 = + (uint16_t) (new_cpuclk0_div | + (new_extraclk1_div << BSP_INTERNAL_SCKDIVCR2_EXTRACK1_POS) | + (new_extraclk2_div << BSP_INTERNAL_SCKDIVCR2_EXTRACK2_POS) | + (new_extraclk3_div << BSP_INTERNAL_SCKDIVCR2_EXTRACK3_POS)); + #else + /* Determine what the other dividers are using and stay aligned with that. */ R_SYSTEM->SCKDIVCR2 = (iclk_div & 0x8) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + #endif } else { + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* If not /1, can just add 1 to it. */ + uint32_t new_cpuclk0_div = sckdivcr2 + 1; + + /* Bump down dividers to new_div for other sckdivcr2 dividers if needed. */ + uint32_t new_extraclk1_div = + (extraclk1_div < new_cpuclk0_div) ? new_cpuclk0_div : extraclk1_div; + uint32_t new_extraclk2_div = + (extraclk2_div < new_cpuclk0_div) ? new_cpuclk0_div : extraclk2_div; + uint32_t new_extraclk3_div = + (extraclk3_div < new_cpuclk0_div) ? new_cpuclk0_div : extraclk3_div; + + R_SYSTEM->SCKDIVCR2 = + (uint16_t) (new_cpuclk0_div | + (new_extraclk1_div << BSP_INTERNAL_SCKDIVCR2_EXTRACK1_POS) | + (new_extraclk2_div << BSP_INTERNAL_SCKDIVCR2_EXTRACK2_POS) | + (new_extraclk3_div << BSP_INTERNAL_SCKDIVCR2_EXTRACK3_POS)); + #else + /* If not /1, can just add 1 to it. */ - R_SYSTEM->SCKDIVCR2 = sckdivcr2 + 1; + R_SYSTEM->SCKDIVCR2 = (uint8_t) sckdivcr2 + 1; + #endif } } @@ -1175,11 +1300,16 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2) uint32_t current_sckdivcr = R_SYSTEM->SCKDIVCR; /* Must first step CPUCLK down by factor of 2 or 3 if it is currently above threshold. */ + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + if ((R_SYSTEM->SCKDIVCR2 & R_SYSTEM_SCKDIVCR2_CPUCK_Msk) == + ((current_sckdivcr >> R_SYSTEM_SCKDIVCR_ICK_Pos) & 0xF)) + #else if (R_SYSTEM->SCKDIVCR2 == ((current_sckdivcr >> R_SYSTEM_SCKDIVCR_ICK_Pos) & 0xF)) + #endif { /* If ICLK and CPUCLK have same divider currently, move ICLK down 1 notch first. */ uint32_t current_iclk_div = (current_sckdivcr >> R_SYSTEM_SCKDIVCR_ICK_Pos) & 0xF; - uint32_t new_div = current_iclk_div + 1; + uint32_t new_div = (uint16_t) current_iclk_div + 1; if (current_iclk_div == 0) { /* Align with already selected divider for PCLKA because it must have one > 1 already. */ @@ -1191,7 +1321,20 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2) R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); R_SYSTEM->SCKDIVCR = (current_sckdivcr & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | (new_div << R_SYSTEM_SCKDIVCR_ICK_Pos); + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* Bump down dividers to new_div for other sckdivcr2 dividers if needed. */ + uint32_t new_extraclk1_div = (extraclk1_div < new_div) ? new_div : extraclk1_div; + uint32_t new_extraclk2_div = (extraclk2_div < new_div) ? new_div : extraclk2_div; + uint32_t new_extraclk3_div = (extraclk3_div < new_div) ? new_div : extraclk3_div; + + R_SYSTEM->SCKDIVCR2 = + (uint16_t) (new_div | (new_extraclk1_div << BSP_INTERNAL_SCKDIVCR2_EXTRACK1_POS) | + (new_extraclk2_div << BSP_INTERNAL_SCKDIVCR2_EXTRACK2_POS) | + (new_extraclk3_div << BSP_INTERNAL_SCKDIVCR2_EXTRACK3_POS)); + #else R_SYSTEM->SCKDIVCR2 = (uint8_t) new_div; + #endif SystemCoreClockUpdate(); } @@ -1202,8 +1345,18 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2) /* Set the clock dividers after switching to the new clock source. */ prv_clock_dividers_set(sckdivcr, sckdivcr2); + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* New source clock will be slower so set wait state frequency after changing clock frequency according to Frequency Change Procedure. */ + bsp_internal_prv_set_wait_state_frequency(extraclk3_freq_mhz_post_change); + #endif } + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + bsp_internal_prv_set_pfb(extraclk3_freq_mhz_post_change); + #endif + /* Clock is now at requested frequency. */ /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ @@ -1480,6 +1633,12 @@ static void bsp_prv_clock_set_hard_reset (void) #endif #endif + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* Clear the PFB before doing any clock changes according to Frequency Change Procedure. */ + bsp_internal_prv_clear_pfb(); + #endif + /* In order to avoid a system clock (momentarily) higher than expected, the order of switching the clock and * dividers must be so that the frequency of the clock goes lower, instead of higher, before being correct. */ @@ -1487,6 +1646,12 @@ static void bsp_prv_clock_set_hard_reset (void) * then set the clock dividers before switching to the new source clock. */ #if BSP_MOCO_FREQ_HZ <= BSP_STARTUP_SOURCE_CLOCK_HZ #if BSP_FEATURE_CGC_HAS_CPUCLK + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* New source clock will be faster so set wait state frequency before changing clock frequency + * according to Frequency Change Procedure. */ + bsp_internal_prv_set_wait_state_frequency(BSP_STARTUP_EXTRACLK3_HZ / BSP_PRV_HZ_PER_MHZ); + #endif #if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE && (BSP_STARTUP_CPUCLK_HZ >= BSP_MAX_CLOCK_CHANGE_THRESHOLD) /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to @@ -1498,22 +1663,93 @@ static void bsp_prv_clock_set_hard_reset (void) #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 R_SYSTEM->SCKDIVCR = (BSP_PRV_STARTUP_SCKDIVCR & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | (BSP_CLOCKS_SYS_CLOCK_DIV_2 << R_SYSTEM_SCKDIVCR_ICK_Pos); + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + R_SYSTEM->SCKDIVCR2 = BSP_CLOCKS_SYS_CLOCK_DIV_2 | + #if BSP_CFG_EXTRACLK1_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 + (BSP_CLOCKS_SYS_CLOCK_DIV_2 << BSP_INTERNAL_SCKDIVCR2_EXTRACK1_POS) | + #else + (BSP_CFG_EXTRACLK1_DIV << BSP_INTERNAL_SCKDIVCR2_EXTRACK1_POS) | + #endif + #if BSP_CFG_EXTRACLK2_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 + (BSP_CLOCKS_SYS_CLOCK_DIV_2 << BSP_INTERNAL_SCKDIVCR2_EXTRACK2_POS) | + #else + (BSP_CFG_EXTRACLK2_DIV << BSP_INTERNAL_SCKDIVCR2_EXTRACK2_POS) | + #endif + #if BSP_CFG_EXTRACLK3_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 + (BSP_CLOCKS_SYS_CLOCK_DIV_2 << BSP_INTERNAL_SCKDIVCR2_EXTRACK3_POS); + #else + (BSP_CFG_EXTRACLK3_DIV << BSP_INTERNAL_SCKDIVCR2_EXTRACK3_POS); + #endif + #else R_SYSTEM->SCKDIVCR2 = BSP_CLOCKS_SYS_CLOCK_DIV_2; + #endif #else R_SYSTEM->SCKDIVCR = (BSP_PRV_STARTUP_SCKDIVCR & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | (BSP_CLOCKS_SYS_CLOCK_DIV_4 << R_SYSTEM_SCKDIVCR_ICK_Pos); + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + R_SYSTEM->SCKDIVCR2 = BSP_CLOCKS_SYS_CLOCK_DIV_4 | + #if BSP_CFG_EXTRACLK1_DIV < BSP_CLOCKS_SYS_CLOCK_DIV_4 + (BSP_CLOCKS_SYS_CLOCK_DIV_4 << BSP_INTERNAL_SCKDIVCR2_EXTRACK1_POS) + #else + (BSP_CFG_EXTRACLK1_DIV << BSP_INTERNAL_SCKDIVCR2_EXTRACK1_POS) | + #endif + #if BSP_CFG_EXTRACLK2_DIV < BSP_CLOCKS_SYS_CLOCK_DIV_4 + (BSP_CLOCKS_SYS_CLOCK_DIV_4 << BSP_INTERNAL_SCKDIVCR2_EXTRACK2_POS) | + #else + (BSP_CFG_EXTRACLK2_DIV << BSP_INTERNAL_SCKDIVCR2_EXTRACK2_POS) | + #endif + #if BSP_CFG_EXTRACLK3_DIV < BSP_CLOCKS_SYS_CLOCK_DIV_4 + (BSP_CLOCKS_SYS_CLOCK_DIV_4 << BSP_INTERNAL_SCKDIVCR2_EXTRACK3_POS); + #else + (BSP_CFG_EXTRACLK3_DIV << BSP_INTERNAL_SCKDIVCR2_EXTRACK3_POS); + #endif + #else R_SYSTEM->SCKDIVCR2 = BSP_CLOCKS_SYS_CLOCK_DIV_4; + #endif #endif #else R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* Determine what the other dividers are using and stay aligned with that. */ + uint32_t new_cpuclk0_div = (BSP_CFG_ICLK_DIV & 0x8) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + + /* Bump down dividers to new_div for other sckdivcr2 dividers if needed. */ + uint32_t new_extraclk1_div = (BSP_CFG_EXTRACLK1_DIV < new_cpuclk0_div) ? new_cpuclk0_div : BSP_CFG_EXTRACLK1_DIV; + uint32_t new_extraclk2_div = (BSP_CFG_EXTRACLK2_DIV < new_cpuclk0_div) ? new_cpuclk0_div : BSP_CFG_EXTRACLK2_DIV; + uint32_t new_extraclk3_div = (BSP_CFG_EXTRACLK3_DIV < new_cpuclk0_div) ? new_cpuclk0_div : BSP_CFG_EXTRACLK3_DIV; + + R_SYSTEM->SCKDIVCR2 = + (uint16_t) (new_cpuclk0_div | ((new_extraclk1_div) << BSP_INTERNAL_SCKDIVCR2_EXTRACK1_POS) | + ((new_extraclk2_div) << BSP_INTERNAL_SCKDIVCR2_EXTRACK2_POS) | + ((new_extraclk3_div) << BSP_INTERNAL_SCKDIVCR2_EXTRACK3_POS)); + #else /* Determine what the other dividers are using and stay aligned with that. */ R_SYSTEM->SCKDIVCR2 = (BSP_CFG_ICLK_DIV & 0x8) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + #endif #else + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* If not /1, can just add 1 to it. */ + uint32_t new_cpuclk0_div = BSP_PRV_STARTUP_SCKDIVCR2 + 1; + + /* Bump down dividers to new_div for other sckdivcr2 dividers if needed. */ + uint32_t new_extraclk1_div = (BSP_CFG_EXTRACLK1_DIV < new_cpuclk0_div) ? new_cpuclk0_div : BSP_CFG_EXTRACLK1_DIV; + uint32_t new_extraclk2_div = (BSP_CFG_EXTRACLK2_DIV < new_cpuclk0_div) ? new_cpuclk0_div : BSP_CFG_EXTRACLK2_DIV; + uint32_t new_extraclk3_div = (BSP_CFG_EXTRACLK3_DIV < new_cpuclk0_div) ? new_cpuclk0_div : BSP_CFG_EXTRACLK3_DIV; + + R_SYSTEM->SCKDIVCR2 = + (uint16_t) (new_cpuclk0_div | ((new_extraclk1_div) << BSP_INTERNAL_SCKDIVCR2_EXTRACK1_POS) | + ((new_extraclk2_div) << BSP_INTERNAL_SCKDIVCR2_EXTRACK2_POS) | + ((new_extraclk3_div) << BSP_INTERNAL_SCKDIVCR2_EXTRACK3_POS)); + #else /* If not /1, can just add 1 to it. */ R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2 + 1; + #endif #endif #endif @@ -1558,6 +1794,11 @@ static void bsp_prv_clock_set_hard_reset (void) * then set the clock dividers after switching to the new source clock. */ #if BSP_MOCO_FREQ_HZ > BSP_STARTUP_SOURCE_CLOCK_HZ #if BSP_FEATURE_CGC_HAS_CPUCLK + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* New source clock will be slower so set wait state frequency after changing clock frequency according to Frequency Change Procedure. */ + bsp_internal_prv_set_wait_state_frequency(BSP_STARTUP_EXTRACLK3_HZ / BSP_PRV_HZ_PER_MHZ); + #endif #if BSP_PRV_ICLK_DIV_VALUE >= BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_FEATURE_CGC_ICLK_DIV_RESET) /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to @@ -1576,6 +1817,10 @@ static void bsp_prv_clock_set_hard_reset (void) #endif #endif + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + bsp_internal_prv_set_pfb(BSP_STARTUP_EXTRACLK3_HZ / BSP_PRV_HZ_PER_MHZ); + #endif + /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ SystemCoreClockUpdate(); @@ -1584,20 +1829,29 @@ static void bsp_prv_clock_set_hard_reset (void) /* Adjust the MCU specific wait state soon after the system clock is set, if the system clock frequency to be * set is lower than previous. */ #if BSP_FEATURE_CGC_HAS_SRAMWTSC - #if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS - #if BSP_FEATURE_CGC_HAS_SRAMPRCR2 == 1 + #if BSP_FEATURE_CGC_HAS_SRAMPRCR2 == 1 R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_UNLOCK; - R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE; + R_SRAM->SRAMWTSC = BSP_PRV_SRAM_WAIT_CYCLES; R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK; + #else + + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_UNLOCK; #else R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; + #endif /* Execute data memory barrier before and after setting the wait states, See Section 50.4.2 in the RA8M1 * manual R01UH0994EJ0100 */ __DMB(); - R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE; + R_SRAM->SRAMWTSC = BSP_PRV_SRAM_WAIT_CYCLES; __DMB(); + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_LOCK; + #else R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK; #endif #endif @@ -1611,7 +1865,7 @@ static void bsp_prv_clock_set_hard_reset (void) /*******************************************************************************************************************//** * Initializes variable to store system clock frequencies. **********************************************************************************************************************/ -#if BSP_TZ_NONSECURE_BUILD +#if BSP_TZ_NONSECURE_BUILD || BSP_ALT_BUILD void bsp_clock_freq_var_init (void) #else static void bsp_clock_freq_var_init (void) @@ -1632,7 +1886,7 @@ static void bsp_clock_freq_var_init (void) #endif #if BSP_PRV_PLL_SUPPORTED #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE - #if (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) + #if (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (6U != BSP_FEATURE_CGC_PLLCCR_TYPE) /* The PLL Is the startup clock. */ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_STARTUP_SOURCE_CLOCK_HZ; @@ -1659,24 +1913,26 @@ static void bsp_clock_freq_var_init (void) #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) / (BSP_CFG_PLL_DIV + 1U); - #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_CFG_PLL1P_FREQUENCY_HZ; g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1Q] = BSP_CFG_PLL1Q_FREQUENCY_HZ; g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1R] = BSP_CFG_PLL1R_FREQUENCY_HZ; #elif (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = (g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U; #else - g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) >> - BSP_CFG_PLL_DIV; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = + ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) >> + BSP_CFG_PLL_DIV; #endif #endif /* Update PLL2 Clock Frequency based on BSP Configuration. */ #if BSP_PRV_PLL2_SUPPORTED && BSP_PRV_PLL2_USED #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) - g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] = ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) / - (BSP_CFG_PLL2_DIV + 1U); - #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] = + ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) / + (BSP_CFG_PLL2_DIV + 1U); + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] = BSP_CFG_PLL2P_FREQUENCY_HZ; g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2Q] = BSP_CFG_PLL2Q_FREQUENCY_HZ; g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2R] = BSP_CFG_PLL2R_FREQUENCY_HZ; @@ -1751,7 +2007,7 @@ void bsp_soft_reset_prepare (void) * - Note that PLL type 2 does not support running off of the HOCO */ #if BSP_PRV_PLL_USED - #if 3 == BSP_FEATURE_CGC_PLLCCR_TYPE + #if (3 == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6 == BSP_FEATURE_CGC_PLLCCR_TYPE) if ((BSP_PRV_PLLCCR != R_SYSTEM->PLLCCR) || (BSP_PRV_PLLCCR2 != R_SYSTEM->PLLCCR2) || (stop_hoco && (1 == R_SYSTEM->PLLCCR_b.PLSRCSEL))) #elif 2 == BSP_FEATURE_CGC_PLLCCR_TYPE @@ -1777,7 +2033,7 @@ void bsp_soft_reset_prepare (void) * - Note that PLL type 2 does not support running off of the HOCO */ #if BSP_PRV_PLL2_USED - #if 3 == BSP_FEATURE_CGC_PLLCCR_TYPE + #if (3 == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6 == BSP_FEATURE_CGC_PLLCCR_TYPE) if ((BSP_PRV_PLL2CCR != R_SYSTEM->PLL2CCR) || (BSP_PRV_PLL2CCR2 != R_SYSTEM->PLL2CCR2) || (stop_hoco && (1 == R_SYSTEM->PLL2CCR_b.PL2SRCSEL))) #else @@ -1932,7 +2188,7 @@ void bsp_clock_init (void) R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; #endif -#if BSP_FEATURE_BSP_FLASH_CACHE +#if BSP_FEATURE_BSP_FLASH_CACHE || defined(R_CACHE) #if !BSP_CFG_USE_LOW_VOLTAGE_MODE && BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM /* Disable flash cache before modifying MEMWAIT, SOPCCR, or OPCCR. */ @@ -2162,7 +2418,7 @@ void bsp_clock_init (void) #endif { R_SYSTEM->PLL2CCR = BSP_PRV_PLL2CCR; - #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) R_SYSTEM->PLL2CCR2 = BSP_PRV_PLL2CCR2; #endif @@ -2181,8 +2437,12 @@ void bsp_clock_init (void) R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR; #elif 2U == BSP_FEATURE_CGC_PLLCCR_TYPE R_SYSTEM->PLLCCR2 = (uint8_t) BSP_PRV_PLLCCR; - #elif 3U == BSP_FEATURE_CGC_PLLCCR_TYPE - R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR; + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if 6U == BSP_FEATURE_CGC_PLLCCR_TYPE + R_SYSTEM->PLLCCR = BSP_PRV_PLLCCR; + #else + R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR; + #endif R_SYSTEM->PLLCCR2 = (uint16_t) BSP_PRV_PLLCCR2; #endif @@ -2196,6 +2456,14 @@ void bsp_clock_init (void) bsp_prv_software_delay_loop(BSP_DELAY_LOOPS_CALCULATE(BSP_PRV_MAX_HOCO_CYCLES_PER_US)); #endif + #if BSP_MCU_GROUP_NEPTUNE + + /* Always set not high VSCR_1 (non-default), change before enabling PLL. + * - Note this will consume more power than necessary for certain configuraitons. See User Manual for more infomration. */ + R_SYSTEM->VSCR_b.VSCM = 0x1U; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->VSCR_b.VSCMTSF, 0U); + #endif + R_SYSTEM->PLLCR = 0U; #if BSP_PRV_STABILIZE_PLL @@ -2383,7 +2651,7 @@ void bsp_clock_init (void) #endif /* Set the GPT clock if it exists on the MCU */ -#if BSP_FEATURE_BSP_HAS_GPT_CLOCK && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) +#if BSP_PERIPHERAL_GPT_GTCLK_PRESENT && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) bsp_peripheral_clock_set(&R_SYSTEM->GPTCKCR, &R_SYSTEM->GPTCKDIVCR, BSP_CFG_GPTCLK_DIV, BSP_CFG_GPTCLK_SOURCE); #endif @@ -2408,10 +2676,15 @@ void bsp_clock_init (void) #endif /* Set the USB-HS clock if it exists on the MCU */ -#if BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ && (BSP_CFG_U60CK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) +#if BSP_FEATURE_BSP_HAS_USB60_CLOCK && (BSP_CFG_U60CK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) bsp_peripheral_clock_set(&R_SYSTEM->USB60CKCR, &R_SYSTEM->USB60CKDIVCR, BSP_CFG_U60CK_DIV, BSP_CFG_U60CK_SOURCE); #endif + /* Set the ADC clock if it exists on the MCU */ +#if BSP_FEATURE_BSP_HAS_ADC_CLOCK && (BSP_CFG_ADCCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->ADCCKCR, &R_SYSTEM->ADCCKDIVCR, BSP_CFG_ADCCLK_DIV, BSP_CFG_ADCCLK_SOURCE); +#endif + /* Set the SDADC clock if it exists on the MCU. */ #if BSP_FEATURE_BSP_HAS_SDADC_CLOCK && (BSP_CFG_SDADC_CLOCK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) #if BSP_CFG_SDADC_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO @@ -2433,7 +2706,7 @@ void bsp_clock_init (void) R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif -#if BSP_FEATURE_BSP_FLASH_CACHE && BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM +#if (BSP_FEATURE_BSP_FLASH_CACHE || defined(R_CACHE)) && BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM R_BSP_FlashCacheEnable(); #endif @@ -2546,7 +2819,13 @@ static uint8_t bsp_clock_set_prechange (uint32_t requested_freq_hz) R_SRAM->SRAMWTSC = BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE; R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK; #else + + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_UNLOCK; + #else R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; + #endif /* Execute data memory barrier before and after setting the wait states, See Section 50.4.2 in the RA8M1 * manual R01UH0994EJ0100 */ @@ -2554,7 +2833,12 @@ static uint8_t bsp_clock_set_prechange (uint32_t requested_freq_hz) R_SRAM->SRAMWTSC = BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE; __DMB(); + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_LOCK; + #else R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK; + #endif #endif } #endif @@ -2700,7 +2984,13 @@ static void bsp_clock_set_postchange (uint32_t updated_freq_hz, uint8_t new_rom_ R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE; R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK; #else + + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_UNLOCK; + #else R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; + #endif /* Execute data memory barrier before and after setting the wait states,See Section 50.4.2 in the RA8M1 * manual R01UH0994EJ0100*/ @@ -2708,7 +2998,12 @@ static void bsp_clock_set_postchange (uint32_t updated_freq_hz, uint8_t new_rom_ R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE; __DMB(); + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_LOCK; + #else R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK; + #endif #endif } #endif @@ -2976,6 +3271,58 @@ void R_BSP_Init_RTC (void) R_SYSTEM->VBTICTLR = 0U; R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); #endif + + #if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + + /* Enable low power counter measures. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + R_SYSTEM->LPOPT = R_SYSTEM_LPOPT_LPOPTEN_Msk; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + + /* Disable RTC Register Read/Write Clock to reduce power consumption. */ + bsp_prv_rtc_register_clock_set(false); + + /* Enable Asynchronous interrupts */ + R_ICU->IELEN = R_ICU_IELEN_RTCINTEN_Msk | R_ICU_IELEN_IELEN_Msk; + #endif +} + +#endif + +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + +/*******************************************************************************************************************//** + * Enable or disable the RTC Register Read/Write Clock in order to save power. + **********************************************************************************************************************/ +bool bsp_prv_rtc_register_clock_set (bool enable) +{ + /* Save the previous state of RTCRWDIS. + * - RTCRWDIS = 0: Register Clock enabled. + * - RTCRWDIS = 1: Register Clock disabled. + */ + bool previous_state = !R_MSTP->LSMRWDIS_b.RTCRWDIS; + + if (previous_state == enable) + { + return previous_state; + } + + /* Critical section required when writing to registers that are shared between modules. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Set WREN. */ + R_MSTP->LSMRWDIS = BSP_PRV_LSMRDIS_KEY | R_MSTP_LSMRWDIS_WREN_Msk; + + /* Set RTCRWDIS and clear WREN. */ + R_MSTP->LSMRWDIS = BSP_PRV_LSMRDIS_KEY | !enable; + + /* Wait 2 cycles of PCLKB (See Table 3.2 "Access Cycles" in the RA2A2 user manual). */ + FSP_REGISTER_READ(R_MSTP->LSMRWDIS); + + FSP_CRITICAL_SECTION_EXIT; + + return previous_state; } #endif diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h index c7af9e181..0c750cfd6 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h @@ -74,6 +74,7 @@ FSP_HEADER (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ (4U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ (5U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ + (6U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ !BSP_CLOCK_CFG_MAIN_OSC_POPULATED) #define BSP_PRV_PLL_SUPPORTED (1) #if BSP_FEATURE_CGC_HAS_PLL2 @@ -133,7 +134,7 @@ FSP_HEADER #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) #define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \ (BSP_CFG_PLL_DIV)) - #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_PLL1P_FREQUENCY_HZ) #endif #endif @@ -155,6 +156,7 @@ FSP_HEADER #define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV) #define BSP_PRV_BCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_BCLK_DIV) #define BSP_PRV_FCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_FCLK_DIV) +#define BSP_PRV_EXTRACLK3_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_EXTRACLK3_DIV) /* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */ @@ -167,6 +169,7 @@ FSP_HEADER #define BSP_STARTUP_PCLKE_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKE_DIV_VALUE) #define BSP_STARTUP_BCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_BCLK_DIV_VALUE) #define BSP_STARTUP_FCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_FCLK_DIV_VALUE) +#define BSP_STARTUP_EXTRACLK3_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_EXTRACLK3_DIV_VALUE) /* System clock divider options. */ #define BSP_CLOCKS_SYS_CLOCK_DIV_1 (0) // System clock divided by 1. @@ -180,6 +183,7 @@ FSP_HEADER #define BSP_CLOCKS_SYS_CLOCK_DIV_3 (8) // System clock divided by 3. #define BSP_CLOCKS_SYS_CLOCK_DIV_6 (9) // System clock divided by 6. #define BSP_CLOCKS_SYS_CLOCK_DIV_12 (10) // System clock divided by 12. +#define BSP_CLOCKS_SYS_CLOCK_DIV_24 (11) // System clock divided by 24. /* USB clock divider options. */ #define BSP_CLOCKS_USB_CLOCK_DIV_1 (0) // Divide USB source clock by 1 @@ -189,6 +193,9 @@ FSP_HEADER #define BSP_CLOCKS_USB_CLOCK_DIV_5 (4) // Divide USB source clock by 5 #define BSP_CLOCKS_USB_CLOCK_DIV_6 (5) // Divide USB source clock by 6 #define BSP_CLOCKS_USB_CLOCK_DIV_8 (7) // Divide USB source clock by 8 +#define BSP_CLOCKS_USB_CLOCK_DIV_10 (9) // Divide USB source clock by 10 +#define BSP_CLOCKS_USB_CLOCK_DIV_16 (15) // Divide USB source clock by 16 +#define BSP_CLOCKS_USB_CLOCK_DIV_32 (9) // Divide USB source clock by 32 /* USB60 clock divider options. */ #define BSP_CLOCKS_USB60_CLOCK_DIV_1 (0) // Divide USB60 source clock by 1 @@ -198,6 +205,9 @@ FSP_HEADER #define BSP_CLOCKS_USB60_CLOCK_DIV_5 (6) // Divide USB60 source clock by 5 #define BSP_CLOCKS_USB60_CLOCK_DIV_6 (3) // Divide USB66 source clock by 6 #define BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) // Divide USB60 source clock by 8 +#define BSP_CLOCKS_USB60_CLOCK_DIV_10 (7) // Divide USB60 source clock by 10 +#define BSP_CLOCKS_USB60_CLOCK_DIV_16 (8) // Divide USB60 source clock by 16 +#define BSP_CLOCKS_USB60_CLOCK_DIV_32 (9) // Divide USB60 source clock by 32 /* GLCD clock divider options. */ #define BSP_CLOCKS_LCD_CLOCK_DIV_1 (0) // Divide LCD source clock by 1 @@ -207,6 +217,9 @@ FSP_HEADER #define BSP_CLOCKS_LCD_CLOCK_DIV_5 (6) // Divide LCD source clock by 5 #define BSP_CLOCKS_LCD_CLOCK_DIV_6 (3) // Divide LCD source clock by 6 #define BSP_CLOCKS_LCD_CLOCK_DIV_8 (4) // Divide LCD source clock by 8 +#define BSP_CLOCKS_LCD_CLOCK_DIV_10 (7) // Divide LCD source clock by 10 +#define BSP_CLOCKS_LCD_CLOCK_DIV_16 (8) // Divide LCD source clock by 16 +#define BSP_CLOCKS_LCD_CLOCK_DIV_32 (9) // Divide LCD source clock by 32 /* OCTA clock divider options. */ #define BSP_CLOCKS_OCTA_CLOCK_DIV_1 (0) // Divide OCTA source clock by 1 @@ -216,6 +229,9 @@ FSP_HEADER #define BSP_CLOCKS_OCTA_CLOCK_DIV_5 (6) // Divide OCTA source clock by 5 #define BSP_CLOCKS_OCTA_CLOCK_DIV_6 (3) // Divide OCTA source clock by 6 #define BSP_CLOCKS_OCTA_CLOCK_DIV_8 (4) // Divide OCTA source clock by 8 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_10 (7) // Divide OCTA source clock by 10 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_16 (8) // Divide OCTA source clock by 16 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_32 (9) // Divide OCTA source clock by 32 /* CANFD clock divider options. */ #define BSP_CLOCKS_CANFD_CLOCK_DIV_1 (0) // Divide CANFD source clock by 1 @@ -225,6 +241,9 @@ FSP_HEADER #define BSP_CLOCKS_CANFD_CLOCK_DIV_5 (6) // Divide CANFD source clock by 5 #define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6 #define BSP_CLOCKS_CANFD_CLOCK_DIV_8 (4) // Divide CANFD source clock by 8 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_10 (7) // Divide CANFD source clock by 10 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_16 (8) // Divide CANFD source clock by 16 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_32 (9) // Divide CANFD source clock by 32 /* SCI clock divider options. */ #define BSP_CLOCKS_SCI_CLOCK_DIV_1 (0) // Divide SCI source clock by 1 @@ -234,6 +253,9 @@ FSP_HEADER #define BSP_CLOCKS_SCI_CLOCK_DIV_5 (6) // Divide SCI source clock by 5 #define BSP_CLOCKS_SCI_CLOCK_DIV_6 (3) // Divide SCI source clock by 6 #define BSP_CLOCKS_SCI_CLOCK_DIV_8 (4) // Divide SCI source clock by 8 +#define BSP_CLOCKS_SCI_CLOCK_DIV_10 (7) // Divide SCI source clock by 10 +#define BSP_CLOCKS_SCI_CLOCK_DIV_16 (8) // Divide SCI source clock by 16 +#define BSP_CLOCKS_SCI_CLOCK_DIV_32 (9) // Divide SCI source clock by 32 /* SPI clock divider options. */ #define BSP_CLOCKS_SPI_CLOCK_DIV_1 (0) // Divide SPI source clock by 1 @@ -243,6 +265,9 @@ FSP_HEADER #define BSP_CLOCKS_SPI_CLOCK_DIV_5 (6) // Divide SPI source clock by 5 #define BSP_CLOCKS_SPI_CLOCK_DIV_6 (3) // Divide SPI source clock by 6 #define BSP_CLOCKS_SPI_CLOCK_DIV_8 (4) // Divide SPI source clock by 8 +#define BSP_CLOCKS_SPI_CLOCK_DIV_10 (7) // Divide SPI source clock by 10 +#define BSP_CLOCKS_SPI_CLOCK_DIV_16 (8) // Divide SPI source clock by 16 +#define BSP_CLOCKS_SPI_CLOCK_DIV_32 (9) // Divide SPI source clock by 32 /* SCISPI clock divider options. */ #define BSP_CLOCKS_SCISPI_CLOCK_DIV_1 (0) // Divide SCISPI source clock by 1 @@ -259,6 +284,9 @@ FSP_HEADER #define BSP_CLOCKS_GPT_CLOCK_DIV_5 (6) // Divide GPT source clock by 5 #define BSP_CLOCKS_GPT_CLOCK_DIV_6 (3) // Divide GPT source clock by 6 #define BSP_CLOCKS_GPT_CLOCK_DIV_8 (4) // Divide GPT source clock by 8 +#define BSP_CLOCKS_GPT_CLOCK_DIV_10 (7) // Divide GPT source clock by 10 +#define BSP_CLOCKS_GPT_CLOCK_DIV_16 (8) // Divide GPT source clock by 16 +#define BSP_CLOCKS_GPT_CLOCK_DIV_32 (9) // Divide GPT source clock by 32 /* IIC clock divider options. */ #define BSP_CLOCKS_IIC_CLOCK_DIV_1 (0) // Divide IIC source clock by 1 @@ -279,6 +307,21 @@ FSP_HEADER #define BSP_CLOCKS_I3C_CLOCK_DIV_5 (6) // Divide I3C source clock by 5 #define BSP_CLOCKS_I3C_CLOCK_DIV_6 (3) // Divide I3C source clock by 6 #define BSP_CLOCKS_I3C_CLOCK_DIV_8 (4) // Divide I3C source clock by 8 +#define BSP_CLOCKS_I3C_CLOCK_DIV_10 (7) // Divide I3C source clock by 10 +#define BSP_CLOCKS_I3C_CLOCK_DIV_16 (8) // Divide I3C source clock by 16 +#define BSP_CLOCKS_I3C_CLOCK_DIV_32 (9) // Divide I3C source clock by 32 + +/* ADC clock divider options. */ +#define BSP_CLOCKS_ADC_CLOCK_DIV_1 (0) // Divide ADC source clock by 1 +#define BSP_CLOCKS_ADC_CLOCK_DIV_2 (1) // Divide ADC source clock by 2 +#define BSP_CLOCKS_ADC_CLOCK_DIV_3 (5) // Divide ADC source clock by 3 +#define BSP_CLOCKS_ADC_CLOCK_DIV_4 (2) // Divide ADC source clock by 4 +#define BSP_CLOCKS_ADC_CLOCK_DIV_5 (6) // Divide ADC source clock by 5 +#define BSP_CLOCKS_ADC_CLOCK_DIV_6 (3) // Divide ADC source clock by 6 +#define BSP_CLOCKS_ADC_CLOCK_DIV_8 (4) // Divide ADC source clock by 8 +#define BSP_CLOCKS_ADC_CLOCK_DIV_10 (7) // Divide ADC source clock by 10 +#define BSP_CLOCKS_ADC_CLOCK_DIV_16 (8) // Divide ADC source clock by 16 +#define BSP_CLOCKS_ADC_CLOCK_DIV_32 (9) // Divide ADC source clock by 32 /* SAU clock divider options. */ #define BSP_CLOCKS_SAU_CLOCK_DIV_1 (0) // Divide SAU source clock by 1 @@ -307,6 +350,7 @@ FSP_HEADER #define BSP_CLOCKS_PLL_DIV_6 (5) #define BSP_CLOCKS_PLL_DIV_8 (7) #define BSP_CLOCKS_PLL_DIV_9 (8) +#define BSP_CLOCKS_PLL_DIV_1_5 (9) #define BSP_CLOCKS_PLL_DIV_16 (15) /* PLL multiplier options. */ @@ -321,7 +365,7 @@ FSP_HEADER */ #define BSP_CLOCKS_PLL_MUL(X, Y) (X - BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET) -#elif (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) +#elif (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (6U != BSP_FEATURE_CGC_PLLCCR_TYPE) /** * X=Integer portion of the multiplier. @@ -1113,6 +1157,486 @@ typedef enum e_cgc_pll_mul CGC_PLL_MUL_180_33 = BSP_CLOCKS_PLL_MUL(180U, 33U), ///< PLL multiplier of 180.33 CGC_PLL_MUL_180_5 = BSP_CLOCKS_PLL_MUL(180U, 50U), ///< PLL multiplier of 180.50 CGC_PLL_MUL_180_66 = BSP_CLOCKS_PLL_MUL(180U, 66U), ///< PLL multiplier of 180.66 + CGC_PLL_MUL_181_0 = BSP_CLOCKS_PLL_MUL(181U, 0U), ///< PLL multiplier of 181.00 + CGC_PLL_MUL_181_33 = BSP_CLOCKS_PLL_MUL(181U, 33U), ///< PLL multiplier of 181.33 + CGC_PLL_MUL_181_5 = BSP_CLOCKS_PLL_MUL(181U, 50U), ///< PLL multiplier of 181.50 + CGC_PLL_MUL_181_66 = BSP_CLOCKS_PLL_MUL(181U, 66U), ///< PLL multiplier of 181.66 + CGC_PLL_MUL_182_0 = BSP_CLOCKS_PLL_MUL(182U, 0U), ///< PLL multiplier of 182.00 + CGC_PLL_MUL_182_33 = BSP_CLOCKS_PLL_MUL(182U, 33U), ///< PLL multiplier of 182.33 + CGC_PLL_MUL_182_5 = BSP_CLOCKS_PLL_MUL(182U, 50U), ///< PLL multiplier of 182.50 + CGC_PLL_MUL_182_66 = BSP_CLOCKS_PLL_MUL(182U, 66U), ///< PLL multiplier of 182.66 + CGC_PLL_MUL_183_0 = BSP_CLOCKS_PLL_MUL(183U, 0U), ///< PLL multiplier of 183.00 + CGC_PLL_MUL_183_33 = BSP_CLOCKS_PLL_MUL(183U, 33U), ///< PLL multiplier of 183.33 + CGC_PLL_MUL_183_5 = BSP_CLOCKS_PLL_MUL(183U, 50U), ///< PLL multiplier of 183.50 + CGC_PLL_MUL_183_66 = BSP_CLOCKS_PLL_MUL(183U, 66U), ///< PLL multiplier of 183.66 + CGC_PLL_MUL_184_0 = BSP_CLOCKS_PLL_MUL(184U, 0U), ///< PLL multiplier of 184.00 + CGC_PLL_MUL_184_33 = BSP_CLOCKS_PLL_MUL(184U, 33U), ///< PLL multiplier of 184.33 + CGC_PLL_MUL_184_5 = BSP_CLOCKS_PLL_MUL(184U, 50U), ///< PLL multiplier of 184.50 + CGC_PLL_MUL_184_66 = BSP_CLOCKS_PLL_MUL(184U, 66U), ///< PLL multiplier of 184.66 + CGC_PLL_MUL_185_0 = BSP_CLOCKS_PLL_MUL(185U, 0U), ///< PLL multiplier of 185.00 + CGC_PLL_MUL_185_33 = BSP_CLOCKS_PLL_MUL(185U, 33U), ///< PLL multiplier of 185.33 + CGC_PLL_MUL_185_5 = BSP_CLOCKS_PLL_MUL(185U, 50U), ///< PLL multiplier of 185.50 + CGC_PLL_MUL_185_66 = BSP_CLOCKS_PLL_MUL(185U, 66U), ///< PLL multiplier of 185.66 + CGC_PLL_MUL_186_0 = BSP_CLOCKS_PLL_MUL(186U, 0U), ///< PLL multiplier of 186.00 + CGC_PLL_MUL_186_33 = BSP_CLOCKS_PLL_MUL(186U, 33U), ///< PLL multiplier of 186.33 + CGC_PLL_MUL_186_5 = BSP_CLOCKS_PLL_MUL(186U, 50U), ///< PLL multiplier of 186.50 + CGC_PLL_MUL_186_66 = BSP_CLOCKS_PLL_MUL(186U, 66U), ///< PLL multiplier of 186.66 + CGC_PLL_MUL_187_0 = BSP_CLOCKS_PLL_MUL(187U, 0U), ///< PLL multiplier of 187.00 + CGC_PLL_MUL_187_33 = BSP_CLOCKS_PLL_MUL(187U, 33U), ///< PLL multiplier of 187.33 + CGC_PLL_MUL_187_5 = BSP_CLOCKS_PLL_MUL(187U, 50U), ///< PLL multiplier of 187.50 + CGC_PLL_MUL_187_66 = BSP_CLOCKS_PLL_MUL(187U, 66U), ///< PLL multiplier of 187.66 + CGC_PLL_MUL_188_0 = BSP_CLOCKS_PLL_MUL(188U, 0U), ///< PLL multiplier of 188.00 + CGC_PLL_MUL_188_33 = BSP_CLOCKS_PLL_MUL(188U, 33U), ///< PLL multiplier of 188.33 + CGC_PLL_MUL_188_5 = BSP_CLOCKS_PLL_MUL(188U, 50U), ///< PLL multiplier of 188.50 + CGC_PLL_MUL_188_66 = BSP_CLOCKS_PLL_MUL(188U, 66U), ///< PLL multiplier of 188.66 + CGC_PLL_MUL_189_0 = BSP_CLOCKS_PLL_MUL(189U, 0U), ///< PLL multiplier of 189.00 + CGC_PLL_MUL_189_33 = BSP_CLOCKS_PLL_MUL(189U, 33U), ///< PLL multiplier of 189.33 + CGC_PLL_MUL_189_5 = BSP_CLOCKS_PLL_MUL(189U, 50U), ///< PLL multiplier of 189.50 + CGC_PLL_MUL_189_66 = BSP_CLOCKS_PLL_MUL(189U, 66U), ///< PLL multiplier of 189.66 + CGC_PLL_MUL_190_0 = BSP_CLOCKS_PLL_MUL(190U, 0U), ///< PLL multiplier of 190.00 + CGC_PLL_MUL_190_33 = BSP_CLOCKS_PLL_MUL(190U, 33U), ///< PLL multiplier of 190.33 + CGC_PLL_MUL_190_5 = BSP_CLOCKS_PLL_MUL(190U, 50U), ///< PLL multiplier of 190.50 + CGC_PLL_MUL_190_66 = BSP_CLOCKS_PLL_MUL(190U, 66U), ///< PLL multiplier of 190.66 + CGC_PLL_MUL_191_0 = BSP_CLOCKS_PLL_MUL(191U, 0U), ///< PLL multiplier of 191.00 + CGC_PLL_MUL_191_33 = BSP_CLOCKS_PLL_MUL(191U, 33U), ///< PLL multiplier of 191.33 + CGC_PLL_MUL_191_5 = BSP_CLOCKS_PLL_MUL(191U, 50U), ///< PLL multiplier of 191.50 + CGC_PLL_MUL_191_66 = BSP_CLOCKS_PLL_MUL(191U, 66U), ///< PLL multiplier of 191.66 + CGC_PLL_MUL_192_0 = BSP_CLOCKS_PLL_MUL(192U, 0U), ///< PLL multiplier of 192.00 + CGC_PLL_MUL_192_33 = BSP_CLOCKS_PLL_MUL(192U, 33U), ///< PLL multiplier of 192.33 + CGC_PLL_MUL_192_5 = BSP_CLOCKS_PLL_MUL(192U, 50U), ///< PLL multiplier of 192.50 + CGC_PLL_MUL_192_66 = BSP_CLOCKS_PLL_MUL(192U, 66U), ///< PLL multiplier of 192.66 + CGC_PLL_MUL_193_0 = BSP_CLOCKS_PLL_MUL(193U, 0U), ///< PLL multiplier of 193.00 + CGC_PLL_MUL_193_33 = BSP_CLOCKS_PLL_MUL(193U, 33U), ///< PLL multiplier of 193.33 + CGC_PLL_MUL_193_5 = BSP_CLOCKS_PLL_MUL(193U, 50U), ///< PLL multiplier of 193.50 + CGC_PLL_MUL_193_66 = BSP_CLOCKS_PLL_MUL(193U, 66U), ///< PLL multiplier of 193.66 + CGC_PLL_MUL_194_0 = BSP_CLOCKS_PLL_MUL(194U, 0U), ///< PLL multiplier of 194.00 + CGC_PLL_MUL_194_33 = BSP_CLOCKS_PLL_MUL(194U, 33U), ///< PLL multiplier of 194.33 + CGC_PLL_MUL_194_5 = BSP_CLOCKS_PLL_MUL(194U, 50U), ///< PLL multiplier of 194.50 + CGC_PLL_MUL_194_66 = BSP_CLOCKS_PLL_MUL(194U, 66U), ///< PLL multiplier of 194.66 + CGC_PLL_MUL_195_0 = BSP_CLOCKS_PLL_MUL(195U, 0U), ///< PLL multiplier of 195.00 + CGC_PLL_MUL_195_33 = BSP_CLOCKS_PLL_MUL(195U, 33U), ///< PLL multiplier of 195.33 + CGC_PLL_MUL_195_5 = BSP_CLOCKS_PLL_MUL(195U, 50U), ///< PLL multiplier of 195.50 + CGC_PLL_MUL_195_66 = BSP_CLOCKS_PLL_MUL(195U, 66U), ///< PLL multiplier of 195.66 + CGC_PLL_MUL_196_0 = BSP_CLOCKS_PLL_MUL(196U, 0U), ///< PLL multiplier of 196.00 + CGC_PLL_MUL_196_33 = BSP_CLOCKS_PLL_MUL(196U, 33U), ///< PLL multiplier of 196.33 + CGC_PLL_MUL_196_5 = BSP_CLOCKS_PLL_MUL(196U, 50U), ///< PLL multiplier of 196.50 + CGC_PLL_MUL_196_66 = BSP_CLOCKS_PLL_MUL(196U, 66U), ///< PLL multiplier of 196.66 + CGC_PLL_MUL_197_0 = BSP_CLOCKS_PLL_MUL(197U, 0U), ///< PLL multiplier of 197.00 + CGC_PLL_MUL_197_33 = BSP_CLOCKS_PLL_MUL(197U, 33U), ///< PLL multiplier of 197.33 + CGC_PLL_MUL_197_5 = BSP_CLOCKS_PLL_MUL(197U, 50U), ///< PLL multiplier of 197.50 + CGC_PLL_MUL_197_66 = BSP_CLOCKS_PLL_MUL(197U, 66U), ///< PLL multiplier of 197.66 + CGC_PLL_MUL_198_0 = BSP_CLOCKS_PLL_MUL(198U, 0U), ///< PLL multiplier of 198.00 + CGC_PLL_MUL_198_33 = BSP_CLOCKS_PLL_MUL(198U, 33U), ///< PLL multiplier of 198.33 + CGC_PLL_MUL_198_5 = BSP_CLOCKS_PLL_MUL(198U, 50U), ///< PLL multiplier of 198.50 + CGC_PLL_MUL_198_66 = BSP_CLOCKS_PLL_MUL(198U, 66U), ///< PLL multiplier of 198.66 + CGC_PLL_MUL_199_0 = BSP_CLOCKS_PLL_MUL(199U, 0U), ///< PLL multiplier of 199.00 + CGC_PLL_MUL_199_33 = BSP_CLOCKS_PLL_MUL(199U, 33U), ///< PLL multiplier of 199.33 + CGC_PLL_MUL_199_5 = BSP_CLOCKS_PLL_MUL(199U, 50U), ///< PLL multiplier of 199.50 + CGC_PLL_MUL_199_66 = BSP_CLOCKS_PLL_MUL(199U, 66U), ///< PLL multiplier of 199.66 + CGC_PLL_MUL_200_0 = BSP_CLOCKS_PLL_MUL(200U, 0U), ///< PLL multiplier of 200.00 + CGC_PLL_MUL_200_33 = BSP_CLOCKS_PLL_MUL(200U, 33U), ///< PLL multiplier of 200.33 + CGC_PLL_MUL_200_5 = BSP_CLOCKS_PLL_MUL(200U, 50U), ///< PLL multiplier of 200.50 + CGC_PLL_MUL_200_66 = BSP_CLOCKS_PLL_MUL(200U, 66U), ///< PLL multiplier of 200.66 + CGC_PLL_MUL_201_0 = BSP_CLOCKS_PLL_MUL(201U, 0U), ///< PLL multiplier of 201.00 + CGC_PLL_MUL_201_33 = BSP_CLOCKS_PLL_MUL(201U, 33U), ///< PLL multiplier of 201.33 + CGC_PLL_MUL_201_5 = BSP_CLOCKS_PLL_MUL(201U, 50U), ///< PLL multiplier of 201.50 + CGC_PLL_MUL_201_66 = BSP_CLOCKS_PLL_MUL(201U, 66U), ///< PLL multiplier of 201.66 + CGC_PLL_MUL_202_0 = BSP_CLOCKS_PLL_MUL(202U, 0U), ///< PLL multiplier of 202.00 + CGC_PLL_MUL_202_33 = BSP_CLOCKS_PLL_MUL(202U, 33U), ///< PLL multiplier of 202.33 + CGC_PLL_MUL_202_5 = BSP_CLOCKS_PLL_MUL(202U, 50U), ///< PLL multiplier of 202.50 + CGC_PLL_MUL_202_66 = BSP_CLOCKS_PLL_MUL(202U, 66U), ///< PLL multiplier of 202.66 + CGC_PLL_MUL_203_0 = BSP_CLOCKS_PLL_MUL(203U, 0U), ///< PLL multiplier of 203.00 + CGC_PLL_MUL_203_33 = BSP_CLOCKS_PLL_MUL(203U, 33U), ///< PLL multiplier of 203.33 + CGC_PLL_MUL_203_5 = BSP_CLOCKS_PLL_MUL(203U, 50U), ///< PLL multiplier of 203.50 + CGC_PLL_MUL_203_66 = BSP_CLOCKS_PLL_MUL(203U, 66U), ///< PLL multiplier of 203.66 + CGC_PLL_MUL_204_0 = BSP_CLOCKS_PLL_MUL(204U, 0U), ///< PLL multiplier of 204.00 + CGC_PLL_MUL_204_33 = BSP_CLOCKS_PLL_MUL(204U, 33U), ///< PLL multiplier of 204.33 + CGC_PLL_MUL_204_5 = BSP_CLOCKS_PLL_MUL(204U, 50U), ///< PLL multiplier of 204.50 + CGC_PLL_MUL_204_66 = BSP_CLOCKS_PLL_MUL(204U, 66U), ///< PLL multiplier of 204.66 + CGC_PLL_MUL_205_0 = BSP_CLOCKS_PLL_MUL(205U, 0U), ///< PLL multiplier of 205.00 + CGC_PLL_MUL_205_33 = BSP_CLOCKS_PLL_MUL(205U, 33U), ///< PLL multiplier of 205.33 + CGC_PLL_MUL_205_5 = BSP_CLOCKS_PLL_MUL(205U, 50U), ///< PLL multiplier of 205.50 + CGC_PLL_MUL_205_66 = BSP_CLOCKS_PLL_MUL(205U, 66U), ///< PLL multiplier of 205.66 + CGC_PLL_MUL_206_0 = BSP_CLOCKS_PLL_MUL(206U, 0U), ///< PLL multiplier of 206.00 + CGC_PLL_MUL_206_33 = BSP_CLOCKS_PLL_MUL(206U, 33U), ///< PLL multiplier of 206.33 + CGC_PLL_MUL_206_5 = BSP_CLOCKS_PLL_MUL(206U, 50U), ///< PLL multiplier of 206.50 + CGC_PLL_MUL_206_66 = BSP_CLOCKS_PLL_MUL(206U, 66U), ///< PLL multiplier of 206.66 + CGC_PLL_MUL_207_0 = BSP_CLOCKS_PLL_MUL(207U, 0U), ///< PLL multiplier of 207.00 + CGC_PLL_MUL_207_33 = BSP_CLOCKS_PLL_MUL(207U, 33U), ///< PLL multiplier of 207.33 + CGC_PLL_MUL_207_5 = BSP_CLOCKS_PLL_MUL(207U, 50U), ///< PLL multiplier of 207.50 + CGC_PLL_MUL_207_66 = BSP_CLOCKS_PLL_MUL(207U, 66U), ///< PLL multiplier of 207.66 + CGC_PLL_MUL_208_0 = BSP_CLOCKS_PLL_MUL(208U, 0U), ///< PLL multiplier of 208.00 + CGC_PLL_MUL_208_33 = BSP_CLOCKS_PLL_MUL(208U, 33U), ///< PLL multiplier of 208.33 + CGC_PLL_MUL_208_5 = BSP_CLOCKS_PLL_MUL(208U, 50U), ///< PLL multiplier of 208.50 + CGC_PLL_MUL_208_66 = BSP_CLOCKS_PLL_MUL(208U, 66U), ///< PLL multiplier of 208.66 + CGC_PLL_MUL_209_0 = BSP_CLOCKS_PLL_MUL(209U, 0U), ///< PLL multiplier of 209.00 + CGC_PLL_MUL_209_33 = BSP_CLOCKS_PLL_MUL(209U, 33U), ///< PLL multiplier of 209.33 + CGC_PLL_MUL_209_5 = BSP_CLOCKS_PLL_MUL(209U, 50U), ///< PLL multiplier of 209.50 + CGC_PLL_MUL_209_66 = BSP_CLOCKS_PLL_MUL(209U, 66U), ///< PLL multiplier of 209.66 + CGC_PLL_MUL_210_0 = BSP_CLOCKS_PLL_MUL(210U, 0U), ///< PLL multiplier of 210.00 + CGC_PLL_MUL_210_33 = BSP_CLOCKS_PLL_MUL(210U, 33U), ///< PLL multiplier of 210.33 + CGC_PLL_MUL_210_5 = BSP_CLOCKS_PLL_MUL(210U, 50U), ///< PLL multiplier of 210.50 + CGC_PLL_MUL_210_66 = BSP_CLOCKS_PLL_MUL(210U, 66U), ///< PLL multiplier of 210.66 + CGC_PLL_MUL_211_0 = BSP_CLOCKS_PLL_MUL(211U, 0U), ///< PLL multiplier of 211.00 + CGC_PLL_MUL_211_33 = BSP_CLOCKS_PLL_MUL(211U, 33U), ///< PLL multiplier of 211.33 + CGC_PLL_MUL_211_5 = BSP_CLOCKS_PLL_MUL(211U, 50U), ///< PLL multiplier of 211.50 + CGC_PLL_MUL_211_66 = BSP_CLOCKS_PLL_MUL(211U, 66U), ///< PLL multiplier of 211.66 + CGC_PLL_MUL_212_0 = BSP_CLOCKS_PLL_MUL(212U, 0U), ///< PLL multiplier of 212.00 + CGC_PLL_MUL_212_33 = BSP_CLOCKS_PLL_MUL(212U, 33U), ///< PLL multiplier of 212.33 + CGC_PLL_MUL_212_5 = BSP_CLOCKS_PLL_MUL(212U, 50U), ///< PLL multiplier of 212.50 + CGC_PLL_MUL_212_66 = BSP_CLOCKS_PLL_MUL(212U, 66U), ///< PLL multiplier of 212.66 + CGC_PLL_MUL_213_0 = BSP_CLOCKS_PLL_MUL(213U, 0U), ///< PLL multiplier of 213.00 + CGC_PLL_MUL_213_33 = BSP_CLOCKS_PLL_MUL(213U, 33U), ///< PLL multiplier of 213.33 + CGC_PLL_MUL_213_5 = BSP_CLOCKS_PLL_MUL(213U, 50U), ///< PLL multiplier of 213.50 + CGC_PLL_MUL_213_66 = BSP_CLOCKS_PLL_MUL(213U, 66U), ///< PLL multiplier of 213.66 + CGC_PLL_MUL_214_0 = BSP_CLOCKS_PLL_MUL(214U, 0U), ///< PLL multiplier of 214.00 + CGC_PLL_MUL_214_33 = BSP_CLOCKS_PLL_MUL(214U, 33U), ///< PLL multiplier of 214.33 + CGC_PLL_MUL_214_5 = BSP_CLOCKS_PLL_MUL(214U, 50U), ///< PLL multiplier of 214.50 + CGC_PLL_MUL_214_66 = BSP_CLOCKS_PLL_MUL(214U, 66U), ///< PLL multiplier of 214.66 + CGC_PLL_MUL_215_0 = BSP_CLOCKS_PLL_MUL(215U, 0U), ///< PLL multiplier of 215.00 + CGC_PLL_MUL_215_33 = BSP_CLOCKS_PLL_MUL(215U, 33U), ///< PLL multiplier of 215.33 + CGC_PLL_MUL_215_5 = BSP_CLOCKS_PLL_MUL(215U, 50U), ///< PLL multiplier of 215.50 + CGC_PLL_MUL_215_66 = BSP_CLOCKS_PLL_MUL(215U, 66U), ///< PLL multiplier of 215.66 + CGC_PLL_MUL_216_0 = BSP_CLOCKS_PLL_MUL(216U, 0U), ///< PLL multiplier of 216.00 + CGC_PLL_MUL_216_33 = BSP_CLOCKS_PLL_MUL(216U, 33U), ///< PLL multiplier of 216.33 + CGC_PLL_MUL_216_5 = BSP_CLOCKS_PLL_MUL(216U, 50U), ///< PLL multiplier of 216.50 + CGC_PLL_MUL_216_66 = BSP_CLOCKS_PLL_MUL(216U, 66U), ///< PLL multiplier of 216.66 + CGC_PLL_MUL_217_0 = BSP_CLOCKS_PLL_MUL(217U, 0U), ///< PLL multiplier of 217.00 + CGC_PLL_MUL_217_33 = BSP_CLOCKS_PLL_MUL(217U, 33U), ///< PLL multiplier of 217.33 + CGC_PLL_MUL_217_5 = BSP_CLOCKS_PLL_MUL(217U, 50U), ///< PLL multiplier of 217.50 + CGC_PLL_MUL_217_66 = BSP_CLOCKS_PLL_MUL(217U, 66U), ///< PLL multiplier of 217.66 + CGC_PLL_MUL_218_0 = BSP_CLOCKS_PLL_MUL(218U, 0U), ///< PLL multiplier of 218.00 + CGC_PLL_MUL_218_33 = BSP_CLOCKS_PLL_MUL(218U, 33U), ///< PLL multiplier of 218.33 + CGC_PLL_MUL_218_5 = BSP_CLOCKS_PLL_MUL(218U, 50U), ///< PLL multiplier of 218.50 + CGC_PLL_MUL_218_66 = BSP_CLOCKS_PLL_MUL(218U, 66U), ///< PLL multiplier of 218.66 + CGC_PLL_MUL_219_0 = BSP_CLOCKS_PLL_MUL(219U, 0U), ///< PLL multiplier of 219.00 + CGC_PLL_MUL_219_33 = BSP_CLOCKS_PLL_MUL(219U, 33U), ///< PLL multiplier of 219.33 + CGC_PLL_MUL_219_5 = BSP_CLOCKS_PLL_MUL(219U, 50U), ///< PLL multiplier of 219.50 + CGC_PLL_MUL_219_66 = BSP_CLOCKS_PLL_MUL(219U, 66U), ///< PLL multiplier of 219.66 + CGC_PLL_MUL_220_0 = BSP_CLOCKS_PLL_MUL(220U, 0U), ///< PLL multiplier of 220.00 + CGC_PLL_MUL_220_33 = BSP_CLOCKS_PLL_MUL(220U, 33U), ///< PLL multiplier of 220.33 + CGC_PLL_MUL_220_5 = BSP_CLOCKS_PLL_MUL(220U, 50U), ///< PLL multiplier of 220.50 + CGC_PLL_MUL_220_66 = BSP_CLOCKS_PLL_MUL(220U, 66U), ///< PLL multiplier of 220.66 + CGC_PLL_MUL_221_0 = BSP_CLOCKS_PLL_MUL(221U, 0U), ///< PLL multiplier of 221.00 + CGC_PLL_MUL_221_33 = BSP_CLOCKS_PLL_MUL(221U, 33U), ///< PLL multiplier of 221.33 + CGC_PLL_MUL_221_5 = BSP_CLOCKS_PLL_MUL(221U, 50U), ///< PLL multiplier of 221.50 + CGC_PLL_MUL_221_66 = BSP_CLOCKS_PLL_MUL(221U, 66U), ///< PLL multiplier of 221.66 + CGC_PLL_MUL_222_0 = BSP_CLOCKS_PLL_MUL(222U, 0U), ///< PLL multiplier of 222.00 + CGC_PLL_MUL_222_33 = BSP_CLOCKS_PLL_MUL(222U, 33U), ///< PLL multiplier of 222.33 + CGC_PLL_MUL_222_5 = BSP_CLOCKS_PLL_MUL(222U, 50U), ///< PLL multiplier of 222.50 + CGC_PLL_MUL_222_66 = BSP_CLOCKS_PLL_MUL(222U, 66U), ///< PLL multiplier of 222.66 + CGC_PLL_MUL_223_0 = BSP_CLOCKS_PLL_MUL(223U, 0U), ///< PLL multiplier of 223.00 + CGC_PLL_MUL_223_33 = BSP_CLOCKS_PLL_MUL(223U, 33U), ///< PLL multiplier of 223.33 + CGC_PLL_MUL_223_5 = BSP_CLOCKS_PLL_MUL(223U, 50U), ///< PLL multiplier of 223.50 + CGC_PLL_MUL_223_66 = BSP_CLOCKS_PLL_MUL(223U, 66U), ///< PLL multiplier of 223.66 + CGC_PLL_MUL_224_0 = BSP_CLOCKS_PLL_MUL(224U, 0U), ///< PLL multiplier of 224.00 + CGC_PLL_MUL_224_33 = BSP_CLOCKS_PLL_MUL(224U, 33U), ///< PLL multiplier of 224.33 + CGC_PLL_MUL_224_5 = BSP_CLOCKS_PLL_MUL(224U, 50U), ///< PLL multiplier of 224.50 + CGC_PLL_MUL_224_66 = BSP_CLOCKS_PLL_MUL(224U, 66U), ///< PLL multiplier of 224.66 + CGC_PLL_MUL_225_0 = BSP_CLOCKS_PLL_MUL(225U, 0U), ///< PLL multiplier of 225.00 + CGC_PLL_MUL_225_33 = BSP_CLOCKS_PLL_MUL(225U, 33U), ///< PLL multiplier of 225.33 + CGC_PLL_MUL_225_5 = BSP_CLOCKS_PLL_MUL(225U, 50U), ///< PLL multiplier of 225.50 + CGC_PLL_MUL_225_66 = BSP_CLOCKS_PLL_MUL(225U, 66U), ///< PLL multiplier of 225.66 + CGC_PLL_MUL_226_0 = BSP_CLOCKS_PLL_MUL(226U, 0U), ///< PLL multiplier of 226.00 + CGC_PLL_MUL_226_33 = BSP_CLOCKS_PLL_MUL(226U, 33U), ///< PLL multiplier of 226.33 + CGC_PLL_MUL_226_5 = BSP_CLOCKS_PLL_MUL(226U, 50U), ///< PLL multiplier of 226.50 + CGC_PLL_MUL_226_66 = BSP_CLOCKS_PLL_MUL(226U, 66U), ///< PLL multiplier of 226.66 + CGC_PLL_MUL_227_0 = BSP_CLOCKS_PLL_MUL(227U, 0U), ///< PLL multiplier of 227.00 + CGC_PLL_MUL_227_33 = BSP_CLOCKS_PLL_MUL(227U, 33U), ///< PLL multiplier of 227.33 + CGC_PLL_MUL_227_5 = BSP_CLOCKS_PLL_MUL(227U, 50U), ///< PLL multiplier of 227.50 + CGC_PLL_MUL_227_66 = BSP_CLOCKS_PLL_MUL(227U, 66U), ///< PLL multiplier of 227.66 + CGC_PLL_MUL_228_0 = BSP_CLOCKS_PLL_MUL(228U, 0U), ///< PLL multiplier of 228.00 + CGC_PLL_MUL_228_33 = BSP_CLOCKS_PLL_MUL(228U, 33U), ///< PLL multiplier of 228.33 + CGC_PLL_MUL_228_5 = BSP_CLOCKS_PLL_MUL(228U, 50U), ///< PLL multiplier of 228.50 + CGC_PLL_MUL_228_66 = BSP_CLOCKS_PLL_MUL(228U, 66U), ///< PLL multiplier of 228.66 + CGC_PLL_MUL_229_0 = BSP_CLOCKS_PLL_MUL(229U, 0U), ///< PLL multiplier of 229.00 + CGC_PLL_MUL_229_33 = BSP_CLOCKS_PLL_MUL(229U, 33U), ///< PLL multiplier of 229.33 + CGC_PLL_MUL_229_5 = BSP_CLOCKS_PLL_MUL(229U, 50U), ///< PLL multiplier of 229.50 + CGC_PLL_MUL_229_66 = BSP_CLOCKS_PLL_MUL(229U, 66U), ///< PLL multiplier of 229.66 + CGC_PLL_MUL_230_0 = BSP_CLOCKS_PLL_MUL(230U, 0U), ///< PLL multiplier of 230.00 + CGC_PLL_MUL_230_33 = BSP_CLOCKS_PLL_MUL(230U, 33U), ///< PLL multiplier of 230.33 + CGC_PLL_MUL_230_5 = BSP_CLOCKS_PLL_MUL(230U, 50U), ///< PLL multiplier of 230.50 + CGC_PLL_MUL_230_66 = BSP_CLOCKS_PLL_MUL(230U, 66U), ///< PLL multiplier of 230.66 + CGC_PLL_MUL_231_0 = BSP_CLOCKS_PLL_MUL(231U, 0U), ///< PLL multiplier of 231.00 + CGC_PLL_MUL_231_33 = BSP_CLOCKS_PLL_MUL(231U, 33U), ///< PLL multiplier of 231.33 + CGC_PLL_MUL_231_5 = BSP_CLOCKS_PLL_MUL(231U, 50U), ///< PLL multiplier of 231.50 + CGC_PLL_MUL_231_66 = BSP_CLOCKS_PLL_MUL(231U, 66U), ///< PLL multiplier of 231.66 + CGC_PLL_MUL_232_0 = BSP_CLOCKS_PLL_MUL(232U, 0U), ///< PLL multiplier of 232.00 + CGC_PLL_MUL_232_33 = BSP_CLOCKS_PLL_MUL(232U, 33U), ///< PLL multiplier of 232.33 + CGC_PLL_MUL_232_5 = BSP_CLOCKS_PLL_MUL(232U, 50U), ///< PLL multiplier of 232.50 + CGC_PLL_MUL_232_66 = BSP_CLOCKS_PLL_MUL(232U, 66U), ///< PLL multiplier of 232.66 + CGC_PLL_MUL_233_0 = BSP_CLOCKS_PLL_MUL(233U, 0U), ///< PLL multiplier of 233.00 + CGC_PLL_MUL_233_33 = BSP_CLOCKS_PLL_MUL(233U, 33U), ///< PLL multiplier of 233.33 + CGC_PLL_MUL_233_5 = BSP_CLOCKS_PLL_MUL(233U, 50U), ///< PLL multiplier of 233.50 + CGC_PLL_MUL_233_66 = BSP_CLOCKS_PLL_MUL(233U, 66U), ///< PLL multiplier of 233.66 + CGC_PLL_MUL_234_0 = BSP_CLOCKS_PLL_MUL(234U, 0U), ///< PLL multiplier of 234.00 + CGC_PLL_MUL_234_33 = BSP_CLOCKS_PLL_MUL(234U, 33U), ///< PLL multiplier of 234.33 + CGC_PLL_MUL_234_5 = BSP_CLOCKS_PLL_MUL(234U, 50U), ///< PLL multiplier of 234.50 + CGC_PLL_MUL_234_66 = BSP_CLOCKS_PLL_MUL(234U, 66U), ///< PLL multiplier of 234.66 + CGC_PLL_MUL_235_0 = BSP_CLOCKS_PLL_MUL(235U, 0U), ///< PLL multiplier of 235.00 + CGC_PLL_MUL_235_33 = BSP_CLOCKS_PLL_MUL(235U, 33U), ///< PLL multiplier of 235.33 + CGC_PLL_MUL_235_5 = BSP_CLOCKS_PLL_MUL(235U, 50U), ///< PLL multiplier of 235.50 + CGC_PLL_MUL_235_66 = BSP_CLOCKS_PLL_MUL(235U, 66U), ///< PLL multiplier of 235.66 + CGC_PLL_MUL_236_0 = BSP_CLOCKS_PLL_MUL(236U, 0U), ///< PLL multiplier of 236.00 + CGC_PLL_MUL_236_33 = BSP_CLOCKS_PLL_MUL(236U, 33U), ///< PLL multiplier of 236.33 + CGC_PLL_MUL_236_5 = BSP_CLOCKS_PLL_MUL(236U, 50U), ///< PLL multiplier of 236.50 + CGC_PLL_MUL_236_66 = BSP_CLOCKS_PLL_MUL(236U, 66U), ///< PLL multiplier of 236.66 + CGC_PLL_MUL_237_0 = BSP_CLOCKS_PLL_MUL(237U, 0U), ///< PLL multiplier of 237.00 + CGC_PLL_MUL_237_33 = BSP_CLOCKS_PLL_MUL(237U, 33U), ///< PLL multiplier of 237.33 + CGC_PLL_MUL_237_5 = BSP_CLOCKS_PLL_MUL(237U, 50U), ///< PLL multiplier of 237.50 + CGC_PLL_MUL_237_66 = BSP_CLOCKS_PLL_MUL(237U, 66U), ///< PLL multiplier of 237.66 + CGC_PLL_MUL_238_0 = BSP_CLOCKS_PLL_MUL(238U, 0U), ///< PLL multiplier of 238.00 + CGC_PLL_MUL_238_33 = BSP_CLOCKS_PLL_MUL(238U, 33U), ///< PLL multiplier of 238.33 + CGC_PLL_MUL_238_5 = BSP_CLOCKS_PLL_MUL(238U, 50U), ///< PLL multiplier of 238.50 + CGC_PLL_MUL_238_66 = BSP_CLOCKS_PLL_MUL(238U, 66U), ///< PLL multiplier of 238.66 + CGC_PLL_MUL_239_0 = BSP_CLOCKS_PLL_MUL(239U, 0U), ///< PLL multiplier of 239.00 + CGC_PLL_MUL_239_33 = BSP_CLOCKS_PLL_MUL(239U, 33U), ///< PLL multiplier of 239.33 + CGC_PLL_MUL_239_5 = BSP_CLOCKS_PLL_MUL(239U, 50U), ///< PLL multiplier of 239.50 + CGC_PLL_MUL_239_66 = BSP_CLOCKS_PLL_MUL(239U, 66U), ///< PLL multiplier of 239.66 + CGC_PLL_MUL_240_0 = BSP_CLOCKS_PLL_MUL(240U, 0U), ///< PLL multiplier of 240.00 + CGC_PLL_MUL_240_33 = BSP_CLOCKS_PLL_MUL(240U, 33U), ///< PLL multiplier of 240.33 + CGC_PLL_MUL_240_5 = BSP_CLOCKS_PLL_MUL(240U, 50U), ///< PLL multiplier of 240.50 + CGC_PLL_MUL_240_66 = BSP_CLOCKS_PLL_MUL(240U, 66U), ///< PLL multiplier of 240.66 + CGC_PLL_MUL_241_0 = BSP_CLOCKS_PLL_MUL(241U, 0U), ///< PLL multiplier of 241.00 + CGC_PLL_MUL_241_33 = BSP_CLOCKS_PLL_MUL(241U, 33U), ///< PLL multiplier of 241.33 + CGC_PLL_MUL_241_5 = BSP_CLOCKS_PLL_MUL(241U, 50U), ///< PLL multiplier of 241.50 + CGC_PLL_MUL_241_66 = BSP_CLOCKS_PLL_MUL(241U, 66U), ///< PLL multiplier of 241.66 + CGC_PLL_MUL_242_0 = BSP_CLOCKS_PLL_MUL(242U, 0U), ///< PLL multiplier of 242.00 + CGC_PLL_MUL_242_33 = BSP_CLOCKS_PLL_MUL(242U, 33U), ///< PLL multiplier of 242.33 + CGC_PLL_MUL_242_5 = BSP_CLOCKS_PLL_MUL(242U, 50U), ///< PLL multiplier of 242.50 + CGC_PLL_MUL_242_66 = BSP_CLOCKS_PLL_MUL(242U, 66U), ///< PLL multiplier of 242.66 + CGC_PLL_MUL_243_0 = BSP_CLOCKS_PLL_MUL(243U, 0U), ///< PLL multiplier of 243.00 + CGC_PLL_MUL_243_33 = BSP_CLOCKS_PLL_MUL(243U, 33U), ///< PLL multiplier of 243.33 + CGC_PLL_MUL_243_5 = BSP_CLOCKS_PLL_MUL(243U, 50U), ///< PLL multiplier of 243.50 + CGC_PLL_MUL_243_66 = BSP_CLOCKS_PLL_MUL(243U, 66U), ///< PLL multiplier of 243.66 + CGC_PLL_MUL_244_0 = BSP_CLOCKS_PLL_MUL(244U, 0U), ///< PLL multiplier of 244.00 + CGC_PLL_MUL_244_33 = BSP_CLOCKS_PLL_MUL(244U, 33U), ///< PLL multiplier of 244.33 + CGC_PLL_MUL_244_5 = BSP_CLOCKS_PLL_MUL(244U, 50U), ///< PLL multiplier of 244.50 + CGC_PLL_MUL_244_66 = BSP_CLOCKS_PLL_MUL(244U, 66U), ///< PLL multiplier of 244.66 + CGC_PLL_MUL_245_0 = BSP_CLOCKS_PLL_MUL(245U, 0U), ///< PLL multiplier of 245.00 + CGC_PLL_MUL_245_33 = BSP_CLOCKS_PLL_MUL(245U, 33U), ///< PLL multiplier of 245.33 + CGC_PLL_MUL_245_5 = BSP_CLOCKS_PLL_MUL(245U, 50U), ///< PLL multiplier of 245.50 + CGC_PLL_MUL_245_66 = BSP_CLOCKS_PLL_MUL(245U, 66U), ///< PLL multiplier of 245.66 + CGC_PLL_MUL_246_0 = BSP_CLOCKS_PLL_MUL(246U, 0U), ///< PLL multiplier of 246.00 + CGC_PLL_MUL_246_33 = BSP_CLOCKS_PLL_MUL(246U, 33U), ///< PLL multiplier of 246.33 + CGC_PLL_MUL_246_5 = BSP_CLOCKS_PLL_MUL(246U, 50U), ///< PLL multiplier of 246.50 + CGC_PLL_MUL_246_66 = BSP_CLOCKS_PLL_MUL(246U, 66U), ///< PLL multiplier of 246.66 + CGC_PLL_MUL_247_0 = BSP_CLOCKS_PLL_MUL(247U, 0U), ///< PLL multiplier of 247.00 + CGC_PLL_MUL_247_33 = BSP_CLOCKS_PLL_MUL(247U, 33U), ///< PLL multiplier of 247.33 + CGC_PLL_MUL_247_5 = BSP_CLOCKS_PLL_MUL(247U, 50U), ///< PLL multiplier of 247.50 + CGC_PLL_MUL_247_66 = BSP_CLOCKS_PLL_MUL(247U, 66U), ///< PLL multiplier of 247.66 + CGC_PLL_MUL_248_0 = BSP_CLOCKS_PLL_MUL(248U, 0U), ///< PLL multiplier of 248.00 + CGC_PLL_MUL_248_33 = BSP_CLOCKS_PLL_MUL(248U, 33U), ///< PLL multiplier of 248.33 + CGC_PLL_MUL_248_5 = BSP_CLOCKS_PLL_MUL(248U, 50U), ///< PLL multiplier of 248.50 + CGC_PLL_MUL_248_66 = BSP_CLOCKS_PLL_MUL(248U, 66U), ///< PLL multiplier of 248.66 + CGC_PLL_MUL_249_0 = BSP_CLOCKS_PLL_MUL(249U, 0U), ///< PLL multiplier of 249.00 + CGC_PLL_MUL_249_33 = BSP_CLOCKS_PLL_MUL(249U, 33U), ///< PLL multiplier of 249.33 + CGC_PLL_MUL_249_5 = BSP_CLOCKS_PLL_MUL(249U, 50U), ///< PLL multiplier of 249.50 + CGC_PLL_MUL_249_66 = BSP_CLOCKS_PLL_MUL(249U, 66U), ///< PLL multiplier of 249.66 + CGC_PLL_MUL_250_0 = BSP_CLOCKS_PLL_MUL(250U, 0U), ///< PLL multiplier of 250.00 + CGC_PLL_MUL_250_33 = BSP_CLOCKS_PLL_MUL(250U, 33U), ///< PLL multiplier of 250.33 + CGC_PLL_MUL_250_5 = BSP_CLOCKS_PLL_MUL(250U, 50U), ///< PLL multiplier of 250.50 + CGC_PLL_MUL_250_66 = BSP_CLOCKS_PLL_MUL(250U, 66U), ///< PLL multiplier of 250.66 + CGC_PLL_MUL_251_0 = BSP_CLOCKS_PLL_MUL(251U, 0U), ///< PLL multiplier of 251.00 + CGC_PLL_MUL_251_33 = BSP_CLOCKS_PLL_MUL(251U, 33U), ///< PLL multiplier of 251.33 + CGC_PLL_MUL_251_5 = BSP_CLOCKS_PLL_MUL(251U, 50U), ///< PLL multiplier of 251.50 + CGC_PLL_MUL_251_66 = BSP_CLOCKS_PLL_MUL(251U, 66U), ///< PLL multiplier of 251.66 + CGC_PLL_MUL_252_0 = BSP_CLOCKS_PLL_MUL(252U, 0U), ///< PLL multiplier of 252.00 + CGC_PLL_MUL_252_33 = BSP_CLOCKS_PLL_MUL(252U, 33U), ///< PLL multiplier of 252.33 + CGC_PLL_MUL_252_5 = BSP_CLOCKS_PLL_MUL(252U, 50U), ///< PLL multiplier of 252.50 + CGC_PLL_MUL_252_66 = BSP_CLOCKS_PLL_MUL(252U, 66U), ///< PLL multiplier of 252.66 + CGC_PLL_MUL_253_0 = BSP_CLOCKS_PLL_MUL(253U, 0U), ///< PLL multiplier of 253.00 + CGC_PLL_MUL_253_33 = BSP_CLOCKS_PLL_MUL(253U, 33U), ///< PLL multiplier of 253.33 + CGC_PLL_MUL_253_5 = BSP_CLOCKS_PLL_MUL(253U, 50U), ///< PLL multiplier of 253.50 + CGC_PLL_MUL_253_66 = BSP_CLOCKS_PLL_MUL(253U, 66U), ///< PLL multiplier of 253.66 + CGC_PLL_MUL_254_0 = BSP_CLOCKS_PLL_MUL(254U, 0U), ///< PLL multiplier of 254.00 + CGC_PLL_MUL_254_33 = BSP_CLOCKS_PLL_MUL(254U, 33U), ///< PLL multiplier of 254.33 + CGC_PLL_MUL_254_5 = BSP_CLOCKS_PLL_MUL(254U, 50U), ///< PLL multiplier of 254.50 + CGC_PLL_MUL_254_66 = BSP_CLOCKS_PLL_MUL(254U, 66U), ///< PLL multiplier of 254.66 + CGC_PLL_MUL_255_0 = BSP_CLOCKS_PLL_MUL(255U, 0U), ///< PLL multiplier of 255.00 + CGC_PLL_MUL_255_33 = BSP_CLOCKS_PLL_MUL(255U, 33U), ///< PLL multiplier of 255.33 + CGC_PLL_MUL_255_5 = BSP_CLOCKS_PLL_MUL(255U, 50U), ///< PLL multiplier of 255.50 + CGC_PLL_MUL_255_66 = BSP_CLOCKS_PLL_MUL(255U, 66U), ///< PLL multiplier of 255.66 + CGC_PLL_MUL_256_0 = BSP_CLOCKS_PLL_MUL(256U, 0U), ///< PLL multiplier of 256.00 + CGC_PLL_MUL_256_33 = BSP_CLOCKS_PLL_MUL(256U, 33U), ///< PLL multiplier of 256.33 + CGC_PLL_MUL_256_5 = BSP_CLOCKS_PLL_MUL(256U, 50U), ///< PLL multiplier of 256.50 + CGC_PLL_MUL_256_66 = BSP_CLOCKS_PLL_MUL(256U, 66U), ///< PLL multiplier of 256.66 + CGC_PLL_MUL_257_0 = BSP_CLOCKS_PLL_MUL(257U, 0U), ///< PLL multiplier of 257.00 + CGC_PLL_MUL_257_33 = BSP_CLOCKS_PLL_MUL(257U, 33U), ///< PLL multiplier of 257.33 + CGC_PLL_MUL_257_5 = BSP_CLOCKS_PLL_MUL(257U, 50U), ///< PLL multiplier of 257.50 + CGC_PLL_MUL_257_66 = BSP_CLOCKS_PLL_MUL(257U, 66U), ///< PLL multiplier of 257.66 + CGC_PLL_MUL_258_0 = BSP_CLOCKS_PLL_MUL(258U, 0U), ///< PLL multiplier of 258.00 + CGC_PLL_MUL_258_33 = BSP_CLOCKS_PLL_MUL(258U, 33U), ///< PLL multiplier of 258.33 + CGC_PLL_MUL_258_5 = BSP_CLOCKS_PLL_MUL(258U, 50U), ///< PLL multiplier of 258.50 + CGC_PLL_MUL_258_66 = BSP_CLOCKS_PLL_MUL(258U, 66U), ///< PLL multiplier of 258.66 + CGC_PLL_MUL_259_0 = BSP_CLOCKS_PLL_MUL(259U, 0U), ///< PLL multiplier of 259.00 + CGC_PLL_MUL_259_33 = BSP_CLOCKS_PLL_MUL(259U, 33U), ///< PLL multiplier of 259.33 + CGC_PLL_MUL_259_5 = BSP_CLOCKS_PLL_MUL(259U, 50U), ///< PLL multiplier of 259.50 + CGC_PLL_MUL_259_66 = BSP_CLOCKS_PLL_MUL(259U, 66U), ///< PLL multiplier of 259.66 + CGC_PLL_MUL_260_0 = BSP_CLOCKS_PLL_MUL(260U, 0U), ///< PLL multiplier of 260.00 + CGC_PLL_MUL_260_33 = BSP_CLOCKS_PLL_MUL(260U, 33U), ///< PLL multiplier of 260.33 + CGC_PLL_MUL_260_5 = BSP_CLOCKS_PLL_MUL(260U, 50U), ///< PLL multiplier of 260.50 + CGC_PLL_MUL_260_66 = BSP_CLOCKS_PLL_MUL(260U, 66U), ///< PLL multiplier of 260.66 + CGC_PLL_MUL_261_0 = BSP_CLOCKS_PLL_MUL(261U, 0U), ///< PLL multiplier of 261.00 + CGC_PLL_MUL_261_33 = BSP_CLOCKS_PLL_MUL(261U, 33U), ///< PLL multiplier of 261.33 + CGC_PLL_MUL_261_5 = BSP_CLOCKS_PLL_MUL(261U, 50U), ///< PLL multiplier of 261.50 + CGC_PLL_MUL_261_66 = BSP_CLOCKS_PLL_MUL(261U, 66U), ///< PLL multiplier of 261.66 + CGC_PLL_MUL_262_0 = BSP_CLOCKS_PLL_MUL(262U, 0U), ///< PLL multiplier of 262.00 + CGC_PLL_MUL_262_33 = BSP_CLOCKS_PLL_MUL(262U, 33U), ///< PLL multiplier of 262.33 + CGC_PLL_MUL_262_5 = BSP_CLOCKS_PLL_MUL(262U, 50U), ///< PLL multiplier of 262.50 + CGC_PLL_MUL_262_66 = BSP_CLOCKS_PLL_MUL(262U, 66U), ///< PLL multiplier of 262.66 + CGC_PLL_MUL_263_0 = BSP_CLOCKS_PLL_MUL(263U, 0U), ///< PLL multiplier of 263.00 + CGC_PLL_MUL_263_33 = BSP_CLOCKS_PLL_MUL(263U, 33U), ///< PLL multiplier of 263.33 + CGC_PLL_MUL_263_5 = BSP_CLOCKS_PLL_MUL(263U, 50U), ///< PLL multiplier of 263.50 + CGC_PLL_MUL_263_66 = BSP_CLOCKS_PLL_MUL(263U, 66U), ///< PLL multiplier of 263.66 + CGC_PLL_MUL_264_0 = BSP_CLOCKS_PLL_MUL(264U, 0U), ///< PLL multiplier of 264.00 + CGC_PLL_MUL_264_33 = BSP_CLOCKS_PLL_MUL(264U, 33U), ///< PLL multiplier of 264.33 + CGC_PLL_MUL_264_5 = BSP_CLOCKS_PLL_MUL(264U, 50U), ///< PLL multiplier of 264.50 + CGC_PLL_MUL_264_66 = BSP_CLOCKS_PLL_MUL(264U, 66U), ///< PLL multiplier of 264.66 + CGC_PLL_MUL_265_0 = BSP_CLOCKS_PLL_MUL(265U, 0U), ///< PLL multiplier of 265.00 + CGC_PLL_MUL_265_33 = BSP_CLOCKS_PLL_MUL(265U, 33U), ///< PLL multiplier of 265.33 + CGC_PLL_MUL_265_5 = BSP_CLOCKS_PLL_MUL(265U, 50U), ///< PLL multiplier of 265.50 + CGC_PLL_MUL_265_66 = BSP_CLOCKS_PLL_MUL(265U, 66U), ///< PLL multiplier of 265.66 + CGC_PLL_MUL_266_0 = BSP_CLOCKS_PLL_MUL(266U, 0U), ///< PLL multiplier of 266.00 + CGC_PLL_MUL_266_33 = BSP_CLOCKS_PLL_MUL(266U, 33U), ///< PLL multiplier of 266.33 + CGC_PLL_MUL_266_5 = BSP_CLOCKS_PLL_MUL(266U, 50U), ///< PLL multiplier of 266.50 + CGC_PLL_MUL_266_66 = BSP_CLOCKS_PLL_MUL(266U, 66U), ///< PLL multiplier of 266.66 + CGC_PLL_MUL_267_0 = BSP_CLOCKS_PLL_MUL(267U, 0U), ///< PLL multiplier of 267.00 + CGC_PLL_MUL_267_33 = BSP_CLOCKS_PLL_MUL(267U, 33U), ///< PLL multiplier of 267.33 + CGC_PLL_MUL_267_5 = BSP_CLOCKS_PLL_MUL(267U, 50U), ///< PLL multiplier of 267.50 + CGC_PLL_MUL_267_66 = BSP_CLOCKS_PLL_MUL(267U, 66U), ///< PLL multiplier of 267.66 + CGC_PLL_MUL_268_0 = BSP_CLOCKS_PLL_MUL(268U, 0U), ///< PLL multiplier of 268.00 + CGC_PLL_MUL_268_33 = BSP_CLOCKS_PLL_MUL(268U, 33U), ///< PLL multiplier of 268.33 + CGC_PLL_MUL_268_5 = BSP_CLOCKS_PLL_MUL(268U, 50U), ///< PLL multiplier of 268.50 + CGC_PLL_MUL_268_66 = BSP_CLOCKS_PLL_MUL(268U, 66U), ///< PLL multiplier of 268.66 + CGC_PLL_MUL_269_0 = BSP_CLOCKS_PLL_MUL(269U, 0U), ///< PLL multiplier of 269.00 + CGC_PLL_MUL_269_33 = BSP_CLOCKS_PLL_MUL(269U, 33U), ///< PLL multiplier of 269.33 + CGC_PLL_MUL_269_5 = BSP_CLOCKS_PLL_MUL(269U, 50U), ///< PLL multiplier of 269.50 + CGC_PLL_MUL_269_66 = BSP_CLOCKS_PLL_MUL(269U, 66U), ///< PLL multiplier of 269.66 + CGC_PLL_MUL_270_0 = BSP_CLOCKS_PLL_MUL(270U, 0U), ///< PLL multiplier of 270.00 + CGC_PLL_MUL_270_33 = BSP_CLOCKS_PLL_MUL(270U, 33U), ///< PLL multiplier of 270.33 + CGC_PLL_MUL_270_5 = BSP_CLOCKS_PLL_MUL(270U, 50U), ///< PLL multiplier of 270.50 + CGC_PLL_MUL_270_66 = BSP_CLOCKS_PLL_MUL(270U, 66U), ///< PLL multiplier of 270.66 + CGC_PLL_MUL_271_0 = BSP_CLOCKS_PLL_MUL(271U, 0U), ///< PLL multiplier of 271.00 + CGC_PLL_MUL_271_33 = BSP_CLOCKS_PLL_MUL(271U, 33U), ///< PLL multiplier of 271.33 + CGC_PLL_MUL_271_5 = BSP_CLOCKS_PLL_MUL(271U, 50U), ///< PLL multiplier of 271.50 + CGC_PLL_MUL_271_66 = BSP_CLOCKS_PLL_MUL(271U, 66U), ///< PLL multiplier of 271.66 + CGC_PLL_MUL_272_0 = BSP_CLOCKS_PLL_MUL(272U, 0U), ///< PLL multiplier of 272.00 + CGC_PLL_MUL_272_33 = BSP_CLOCKS_PLL_MUL(272U, 33U), ///< PLL multiplier of 272.33 + CGC_PLL_MUL_272_5 = BSP_CLOCKS_PLL_MUL(272U, 50U), ///< PLL multiplier of 272.50 + CGC_PLL_MUL_272_66 = BSP_CLOCKS_PLL_MUL(272U, 66U), ///< PLL multiplier of 272.66 + CGC_PLL_MUL_273_0 = BSP_CLOCKS_PLL_MUL(273U, 0U), ///< PLL multiplier of 273.00 + CGC_PLL_MUL_273_33 = BSP_CLOCKS_PLL_MUL(273U, 33U), ///< PLL multiplier of 273.33 + CGC_PLL_MUL_273_5 = BSP_CLOCKS_PLL_MUL(273U, 50U), ///< PLL multiplier of 273.50 + CGC_PLL_MUL_273_66 = BSP_CLOCKS_PLL_MUL(273U, 66U), ///< PLL multiplier of 273.66 + CGC_PLL_MUL_274_0 = BSP_CLOCKS_PLL_MUL(274U, 0U), ///< PLL multiplier of 274.00 + CGC_PLL_MUL_274_33 = BSP_CLOCKS_PLL_MUL(274U, 33U), ///< PLL multiplier of 274.33 + CGC_PLL_MUL_274_5 = BSP_CLOCKS_PLL_MUL(274U, 50U), ///< PLL multiplier of 274.50 + CGC_PLL_MUL_274_66 = BSP_CLOCKS_PLL_MUL(274U, 66U), ///< PLL multiplier of 274.66 + CGC_PLL_MUL_275_0 = BSP_CLOCKS_PLL_MUL(275U, 0U), ///< PLL multiplier of 275.00 + CGC_PLL_MUL_275_33 = BSP_CLOCKS_PLL_MUL(275U, 33U), ///< PLL multiplier of 275.33 + CGC_PLL_MUL_275_5 = BSP_CLOCKS_PLL_MUL(275U, 50U), ///< PLL multiplier of 275.50 + CGC_PLL_MUL_275_66 = BSP_CLOCKS_PLL_MUL(275U, 66U), ///< PLL multiplier of 275.66 + CGC_PLL_MUL_276_0 = BSP_CLOCKS_PLL_MUL(276U, 0U), ///< PLL multiplier of 276.00 + CGC_PLL_MUL_276_33 = BSP_CLOCKS_PLL_MUL(276U, 33U), ///< PLL multiplier of 276.33 + CGC_PLL_MUL_276_5 = BSP_CLOCKS_PLL_MUL(276U, 50U), ///< PLL multiplier of 276.50 + CGC_PLL_MUL_276_66 = BSP_CLOCKS_PLL_MUL(276U, 66U), ///< PLL multiplier of 276.66 + CGC_PLL_MUL_277_0 = BSP_CLOCKS_PLL_MUL(277U, 0U), ///< PLL multiplier of 277.00 + CGC_PLL_MUL_277_33 = BSP_CLOCKS_PLL_MUL(277U, 33U), ///< PLL multiplier of 277.33 + CGC_PLL_MUL_277_5 = BSP_CLOCKS_PLL_MUL(277U, 50U), ///< PLL multiplier of 277.50 + CGC_PLL_MUL_277_66 = BSP_CLOCKS_PLL_MUL(277U, 66U), ///< PLL multiplier of 277.66 + CGC_PLL_MUL_278_0 = BSP_CLOCKS_PLL_MUL(278U, 0U), ///< PLL multiplier of 278.00 + CGC_PLL_MUL_278_33 = BSP_CLOCKS_PLL_MUL(278U, 33U), ///< PLL multiplier of 278.33 + CGC_PLL_MUL_278_5 = BSP_CLOCKS_PLL_MUL(278U, 50U), ///< PLL multiplier of 278.50 + CGC_PLL_MUL_278_66 = BSP_CLOCKS_PLL_MUL(278U, 66U), ///< PLL multiplier of 278.66 + CGC_PLL_MUL_279_0 = BSP_CLOCKS_PLL_MUL(279U, 0U), ///< PLL multiplier of 279.00 + CGC_PLL_MUL_279_33 = BSP_CLOCKS_PLL_MUL(279U, 33U), ///< PLL multiplier of 279.33 + CGC_PLL_MUL_279_5 = BSP_CLOCKS_PLL_MUL(279U, 50U), ///< PLL multiplier of 279.50 + CGC_PLL_MUL_279_66 = BSP_CLOCKS_PLL_MUL(279U, 66U), ///< PLL multiplier of 279.66 + CGC_PLL_MUL_280_0 = BSP_CLOCKS_PLL_MUL(280U, 0U), ///< PLL multiplier of 280.00 + CGC_PLL_MUL_280_33 = BSP_CLOCKS_PLL_MUL(280U, 33U), ///< PLL multiplier of 280.33 + CGC_PLL_MUL_280_5 = BSP_CLOCKS_PLL_MUL(280U, 50U), ///< PLL multiplier of 280.50 + CGC_PLL_MUL_280_66 = BSP_CLOCKS_PLL_MUL(280U, 66U), ///< PLL multiplier of 280.66 + CGC_PLL_MUL_281_0 = BSP_CLOCKS_PLL_MUL(281U, 0U), ///< PLL multiplier of 281.00 + CGC_PLL_MUL_281_33 = BSP_CLOCKS_PLL_MUL(281U, 33U), ///< PLL multiplier of 281.33 + CGC_PLL_MUL_281_5 = BSP_CLOCKS_PLL_MUL(281U, 50U), ///< PLL multiplier of 281.50 + CGC_PLL_MUL_281_66 = BSP_CLOCKS_PLL_MUL(281U, 66U), ///< PLL multiplier of 281.66 + CGC_PLL_MUL_282_0 = BSP_CLOCKS_PLL_MUL(282U, 0U), ///< PLL multiplier of 282.00 + CGC_PLL_MUL_282_33 = BSP_CLOCKS_PLL_MUL(282U, 33U), ///< PLL multiplier of 282.33 + CGC_PLL_MUL_282_5 = BSP_CLOCKS_PLL_MUL(282U, 50U), ///< PLL multiplier of 282.50 + CGC_PLL_MUL_282_66 = BSP_CLOCKS_PLL_MUL(282U, 66U), ///< PLL multiplier of 282.66 + CGC_PLL_MUL_283_0 = BSP_CLOCKS_PLL_MUL(283U, 0U), ///< PLL multiplier of 283.00 + CGC_PLL_MUL_283_33 = BSP_CLOCKS_PLL_MUL(283U, 33U), ///< PLL multiplier of 283.33 + CGC_PLL_MUL_283_5 = BSP_CLOCKS_PLL_MUL(283U, 50U), ///< PLL multiplier of 283.50 + CGC_PLL_MUL_283_66 = BSP_CLOCKS_PLL_MUL(283U, 66U), ///< PLL multiplier of 283.66 + CGC_PLL_MUL_284_0 = BSP_CLOCKS_PLL_MUL(284U, 0U), ///< PLL multiplier of 284.00 + CGC_PLL_MUL_284_33 = BSP_CLOCKS_PLL_MUL(284U, 33U), ///< PLL multiplier of 284.33 + CGC_PLL_MUL_284_5 = BSP_CLOCKS_PLL_MUL(284U, 50U), ///< PLL multiplier of 284.50 + CGC_PLL_MUL_284_66 = BSP_CLOCKS_PLL_MUL(284U, 66U), ///< PLL multiplier of 284.66 + CGC_PLL_MUL_285_0 = BSP_CLOCKS_PLL_MUL(285U, 0U), ///< PLL multiplier of 285.00 + CGC_PLL_MUL_285_33 = BSP_CLOCKS_PLL_MUL(285U, 33U), ///< PLL multiplier of 285.33 + CGC_PLL_MUL_285_5 = BSP_CLOCKS_PLL_MUL(285U, 50U), ///< PLL multiplier of 285.50 + CGC_PLL_MUL_285_66 = BSP_CLOCKS_PLL_MUL(285U, 66U), ///< PLL multiplier of 285.66 + CGC_PLL_MUL_286_0 = BSP_CLOCKS_PLL_MUL(286U, 0U), ///< PLL multiplier of 286.00 + CGC_PLL_MUL_286_33 = BSP_CLOCKS_PLL_MUL(286U, 33U), ///< PLL multiplier of 286.33 + CGC_PLL_MUL_286_5 = BSP_CLOCKS_PLL_MUL(286U, 50U), ///< PLL multiplier of 286.50 + CGC_PLL_MUL_286_66 = BSP_CLOCKS_PLL_MUL(286U, 66U), ///< PLL multiplier of 286.66 + CGC_PLL_MUL_287_0 = BSP_CLOCKS_PLL_MUL(287U, 0U), ///< PLL multiplier of 287.00 + CGC_PLL_MUL_287_33 = BSP_CLOCKS_PLL_MUL(287U, 33U), ///< PLL multiplier of 287.33 + CGC_PLL_MUL_287_5 = BSP_CLOCKS_PLL_MUL(287U, 50U), ///< PLL multiplier of 287.50 + CGC_PLL_MUL_287_66 = BSP_CLOCKS_PLL_MUL(287U, 66U), ///< PLL multiplier of 287.66 + CGC_PLL_MUL_288_0 = BSP_CLOCKS_PLL_MUL(288U, 0U), ///< PLL multiplier of 288.00 + CGC_PLL_MUL_288_33 = BSP_CLOCKS_PLL_MUL(288U, 33U), ///< PLL multiplier of 288.33 + CGC_PLL_MUL_288_5 = BSP_CLOCKS_PLL_MUL(288U, 50U), ///< PLL multiplier of 288.50 + CGC_PLL_MUL_288_66 = BSP_CLOCKS_PLL_MUL(288U, 66U), ///< PLL multiplier of 288.66 + CGC_PLL_MUL_289_0 = BSP_CLOCKS_PLL_MUL(289U, 0U), ///< PLL multiplier of 289.00 + CGC_PLL_MUL_289_33 = BSP_CLOCKS_PLL_MUL(289U, 33U), ///< PLL multiplier of 289.33 + CGC_PLL_MUL_289_5 = BSP_CLOCKS_PLL_MUL(289U, 50U), ///< PLL multiplier of 289.50 + CGC_PLL_MUL_289_66 = BSP_CLOCKS_PLL_MUL(289U, 66U), ///< PLL multiplier of 289.66 + CGC_PLL_MUL_290_0 = BSP_CLOCKS_PLL_MUL(290U, 0U), ///< PLL multiplier of 290.00 + CGC_PLL_MUL_290_33 = BSP_CLOCKS_PLL_MUL(290U, 33U), ///< PLL multiplier of 290.33 + CGC_PLL_MUL_290_5 = BSP_CLOCKS_PLL_MUL(290U, 50U), ///< PLL multiplier of 290.50 + CGC_PLL_MUL_290_66 = BSP_CLOCKS_PLL_MUL(290U, 66U), ///< PLL multiplier of 290.66 + CGC_PLL_MUL_291_0 = BSP_CLOCKS_PLL_MUL(291U, 0U), ///< PLL multiplier of 291.00 + CGC_PLL_MUL_291_33 = BSP_CLOCKS_PLL_MUL(291U, 33U), ///< PLL multiplier of 291.33 + CGC_PLL_MUL_291_5 = BSP_CLOCKS_PLL_MUL(291U, 50U), ///< PLL multiplier of 291.50 + CGC_PLL_MUL_291_66 = BSP_CLOCKS_PLL_MUL(291U, 66U), ///< PLL multiplier of 291.66 + CGC_PLL_MUL_292_0 = BSP_CLOCKS_PLL_MUL(292U, 0U), ///< PLL multiplier of 292.00 + CGC_PLL_MUL_292_33 = BSP_CLOCKS_PLL_MUL(292U, 33U), ///< PLL multiplier of 292.33 + CGC_PLL_MUL_292_5 = BSP_CLOCKS_PLL_MUL(292U, 50U), ///< PLL multiplier of 292.50 + CGC_PLL_MUL_292_66 = BSP_CLOCKS_PLL_MUL(292U, 66U), ///< PLL multiplier of 292.66 + CGC_PLL_MUL_293_0 = BSP_CLOCKS_PLL_MUL(293U, 0U), ///< PLL multiplier of 293.00 + CGC_PLL_MUL_293_33 = BSP_CLOCKS_PLL_MUL(293U, 33U), ///< PLL multiplier of 293.33 + CGC_PLL_MUL_293_5 = BSP_CLOCKS_PLL_MUL(293U, 50U), ///< PLL multiplier of 293.50 + CGC_PLL_MUL_293_66 = BSP_CLOCKS_PLL_MUL(293U, 66U), ///< PLL multiplier of 293.66 + CGC_PLL_MUL_294_0 = BSP_CLOCKS_PLL_MUL(294U, 0U), ///< PLL multiplier of 294.00 + CGC_PLL_MUL_294_33 = BSP_CLOCKS_PLL_MUL(294U, 33U), ///< PLL multiplier of 294.33 + CGC_PLL_MUL_294_5 = BSP_CLOCKS_PLL_MUL(294U, 50U), ///< PLL multiplier of 294.50 + CGC_PLL_MUL_294_66 = BSP_CLOCKS_PLL_MUL(294U, 66U), ///< PLL multiplier of 294.66 + CGC_PLL_MUL_295_0 = BSP_CLOCKS_PLL_MUL(295U, 0U), ///< PLL multiplier of 295.00 + CGC_PLL_MUL_295_33 = BSP_CLOCKS_PLL_MUL(295U, 33U), ///< PLL multiplier of 295.33 + CGC_PLL_MUL_295_5 = BSP_CLOCKS_PLL_MUL(295U, 50U), ///< PLL multiplier of 295.50 + CGC_PLL_MUL_295_66 = BSP_CLOCKS_PLL_MUL(295U, 66U), ///< PLL multiplier of 295.66 + CGC_PLL_MUL_296_0 = BSP_CLOCKS_PLL_MUL(296U, 0U), ///< PLL multiplier of 296.00 + CGC_PLL_MUL_296_33 = BSP_CLOCKS_PLL_MUL(296U, 33U), ///< PLL multiplier of 296.33 + CGC_PLL_MUL_296_5 = BSP_CLOCKS_PLL_MUL(296U, 50U), ///< PLL multiplier of 296.50 + CGC_PLL_MUL_296_66 = BSP_CLOCKS_PLL_MUL(296U, 66U), ///< PLL multiplier of 296.66 + CGC_PLL_MUL_297_0 = BSP_CLOCKS_PLL_MUL(297U, 0U), ///< PLL multiplier of 297.00 + CGC_PLL_MUL_297_33 = BSP_CLOCKS_PLL_MUL(297U, 33U), ///< PLL multiplier of 297.33 + CGC_PLL_MUL_297_5 = BSP_CLOCKS_PLL_MUL(297U, 50U), ///< PLL multiplier of 297.50 + CGC_PLL_MUL_297_66 = BSP_CLOCKS_PLL_MUL(297U, 66U), ///< PLL multiplier of 297.66 + CGC_PLL_MUL_298_0 = BSP_CLOCKS_PLL_MUL(298U, 0U), ///< PLL multiplier of 298.00 + CGC_PLL_MUL_298_33 = BSP_CLOCKS_PLL_MUL(298U, 33U), ///< PLL multiplier of 298.33 + CGC_PLL_MUL_298_5 = BSP_CLOCKS_PLL_MUL(298U, 50U), ///< PLL multiplier of 298.50 + CGC_PLL_MUL_298_66 = BSP_CLOCKS_PLL_MUL(298U, 66U), ///< PLL multiplier of 298.66 + CGC_PLL_MUL_299_0 = BSP_CLOCKS_PLL_MUL(299U, 0U), ///< PLL multiplier of 299.00 + CGC_PLL_MUL_299_33 = BSP_CLOCKS_PLL_MUL(299U, 33U), ///< PLL multiplier of 299.33 + CGC_PLL_MUL_299_5 = BSP_CLOCKS_PLL_MUL(299U, 50U), ///< PLL multiplier of 299.50 + CGC_PLL_MUL_299_66 = BSP_CLOCKS_PLL_MUL(299U, 66U), ///< PLL multiplier of 299.66 + CGC_PLL_MUL_300_0 = BSP_CLOCKS_PLL_MUL(300U, 0U), ///< PLL multiplier of 300.00 + CGC_PLL_MUL_300_33 = BSP_CLOCKS_PLL_MUL(300U, 33U), ///< PLL multiplier of 300.33 + CGC_PLL_MUL_300_5 = BSP_CLOCKS_PLL_MUL(300U, 50U), ///< PLL multiplier of 300.50 + CGC_PLL_MUL_300_66 = BSP_CLOCKS_PLL_MUL(300U, 66U), ///< PLL multiplier of 300.66 CGC_PLL_MUL_732_0 = BSP_CLOCKS_PLL_MUL(732U, 0U), ///< PLL multiplier of 732.00 CGC_PLL_MUL_781_0 = BSP_CLOCKS_PLL_MUL(781U, 0U), ///< PLL multiplier of 781.00 } cgc_pll_mul_t; @@ -1128,7 +1652,7 @@ typedef enum e_cgc_pll_mul /* Public functions defined in bsp.h */ void bsp_clock_init(void); // Used internally by BSP -#if BSP_TZ_NONSECURE_BUILD +#if BSP_TZ_NONSECURE_BUILD || BSP_ALT_BUILD void bsp_clock_freq_var_init(void); // Used internally by BSP #endif @@ -1155,7 +1679,7 @@ void bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask); void bsp_prv_prepare_pll(uint32_t clock, uint32_t const * const p_pll_hz); #if !BSP_FEATURE_CGC_REGISTER_SET_B -void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2); +void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr, uint16_t sckdivcr2); #else void bsp_prv_clock_set(uint32_t clock, uint8_t hocodiv, uint8_t mocodiv, uint8_t moscdiv); @@ -1169,6 +1693,11 @@ void R_BSP_Init_RTC(void); #endif +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE +bool bsp_prv_rtc_register_clock_set(bool enable); + +#endif + #if BSP_CFG_SLEEP_MODE_DELAY_ENABLE || BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE bool bsp_prv_clock_prepare_pre_sleep(void); void bsp_prv_clock_prepare_post_sleep(bool cpuclk_slowed); diff --git a/ra/fsp/src/bsp/mcu/all/bsp_common.h b/ra/fsp/src/bsp/mcu/all/bsp_common.h index d1c1f61ad..10c548788 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_common.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_common.h @@ -25,6 +25,8 @@ /* BSP TFU Includes. */ #include "../../src/bsp/mcu/all/bsp_tfu.h" +#include "../../src/bsp/mcu/all/bsp_sdram.h" + #include "bsp_cfg.h" /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ @@ -129,12 +131,11 @@ FSP_HEADER * The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so * the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */ -#if (defined(__IAR_SYSTEMS_ICC__) && ((__CORE__ == __ARM7EM__) || (__CORE__ == __ARM_ARCH_8M_BASE__))) || \ - defined(__ARM_ARCH_7EM__) // CM4 +#if (defined(__IICARM__) && defined(RENESAS_CORTEX_M23)) || defined(RENESAS_CORTEX_M4) #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) #endif -#else // CM23 +#else #ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION #undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION #endif @@ -432,9 +433,25 @@ __STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr) /* Clock Divided by 3 */ return 3U; } + else if (6U == ckdivcr) + { + + /* Clock Divided by 5 */ + return 5; + } + else if (7U == ckdivcr) + { + + /* Clock Divided by 10 */ + return 10; + } + else + { + /* The remaining case is ckdivcr = 8 which divides the clock by 16. */ + } - /* Clock Divided by 5 */ - return 5U; + /* Clock Divided by 16 */ + return 16U; } #if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK @@ -520,10 +537,26 @@ __STATIC_INLINE void R_BSP_FlashCacheDisable (void) R_FCACHE->FCACHEE = 0U; #endif -#if BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE +#ifdef R_CACHE + #if BSP_FEATURE_BSP_CODE_CACHE_VERSION == 2 + + /* Writeback and flush cache when disabling + * MREF_INTERNAL_12 */ + if (R_CACHE->CCAWTA_b.WT) + { + R_CACHE->CCACTL = R_CACHE_CCACTL_FC_Msk; + } + else + { + R_CACHE->CCACTL = R_CACHE_CCACTL_FC_Msk | R_CACHE_CCACTL_WB_Msk; + } + + FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); + #else /* Disable the C-Cache. */ R_CACHE->CCACTL = 0U; + #endif #endif } @@ -543,10 +576,17 @@ __STATIC_INLINE void R_BSP_FlashCacheEnable (void) R_FCACHE->FCACHEE = 1U; #endif -#if BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE +#ifdef R_CACHE + #if BSP_FEATURE_BSP_CODE_CACHE_VERSION == 1 /* Configure the C-Cache line size. */ R_CACHE->CCALCF = BSP_CFG_C_CACHE_LINE_SIZE; + #else + + /* Check that no flush or writeback are ongoing before enabling + * MREF_INTERNAL_13 */ + FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); + #endif /* Enable the C-Cache. */ R_CACHE->CCACTL = 1U; diff --git a/ra/fsp/src/bsp/mcu/all/bsp_delay.c b/ra/fsp/src/bsp/mcu/all/bsp_delay.c index 540482b38..a46545c56 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_delay.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_delay.c @@ -14,6 +14,7 @@ * Macro definitions **********************************************************************************************************************/ #define BSP_DELAY_NS_PER_SECOND (1000000000) +#define BSP_DELAY_US_PER_SECOND (1000000) #define BSP_DELAY_NS_PER_US (1000) /*********************************************************************************************************************** @@ -86,48 +87,75 @@ BSP_SECTION_FLASH_GAP void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units) { uint32_t iclk_hz; - uint32_t cycles_requested; - uint32_t ns_per_cycle; uint32_t loops_required = 0; - uint32_t total_us = (delay * units); /** Convert the requested time to microseconds. */ - uint64_t ns_64bits; + uint32_t total_us = (delay * units); /** Convert the requested time to microseconds. */ - iclk_hz = SystemCoreClock; /** Get the system clock frequency in Hz. */ + iclk_hz = SystemCoreClock; /** Get the system clock frequency in Hz. */ - /* Running on the Sub-clock (32768 Hz) there are 30517 ns/cycle. This means one cycle takes 31 us. One execution - * loop of the delay_loop takes 6 cycles which at 32768 Hz is 180 us. That does not include the overhead below prior to even getting - * to the delay loop. Given this, at this frequency anything less then a delay request of 122 us will not even generate a single - * pass through the delay loop. For this reason small delays (<=~200 us) at this slow clock rate will not be possible and such a request - * will generate a minimum delay of ~200 us.*/ - ns_per_cycle = BSP_DELAY_NS_PER_SECOND / iclk_hz; /** Get the # of nanoseconds/cycle. */ +#if (BSP_CFG_MCU_PART_SERIES == 8) + if (iclk_hz >= BSP_MOCO_HZ) + { + /* For larger system clock values the below calculation in the else causes inaccurate delays due to rounding errors: + * + * ns_per_cycle = BSP_DELAY_NS_PER_SECOND / iclk_hz + * + * For system clock values greater than the MOCO speed the following delay calculation is used instead. + */ + uint32_t cycles_per_us = iclk_hz / (BSP_DELAY_US_PER_SECOND * BSP_DELAY_LOOP_CYCLES); - /* We want to get the time in total nanoseconds but need to be conscious of overflowing 32 bits. We also do not want to do 64 bit */ - /* division as that pulls in a division library. */ - ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns. + uint64_t loops_required_u64 = ((uint64_t) total_us) * cycles_per_us; - /* Have we overflowed 32 bits? */ - if (ns_64bits <= UINT32_MAX) - { - /* No, we will not overflow. */ - cycles_requested = ((uint32_t) ns_64bits / ns_per_cycle); - loops_required = cycles_requested / BSP_DELAY_LOOP_CYCLES; + if (loops_required_u64 > UINT32_MAX) + { + loops_required = UINT32_MAX; + } + else + { + loops_required = (uint32_t) loops_required_u64; + } } else +#endif { - /* We did overflow. Try dividing down first. */ - total_us = (total_us / (ns_per_cycle * BSP_DELAY_LOOP_CYCLES)); + uint32_t cycles_requested; + uint32_t ns_per_cycle; + uint64_t ns_64bits; + + /* Running on the Sub-clock (32768 Hz) there are 30517 ns/cycle. This means one cycle takes 31 us. One execution + * loop of the delay_loop takes 6 cycles which at 32768 Hz is 180 us. That does not include the overhead below prior to even getting + * to the delay loop. Given this, at this frequency anything less then a delay request of 122 us will not even generate a single + * pass through the delay loop. For this reason small delays (<=~200 us) at this slow clock rate will not be possible and such a request + * will generate a minimum delay of ~200 us.*/ + ns_per_cycle = BSP_DELAY_NS_PER_SECOND / iclk_hz; /** Get the # of nanoseconds/cycle. */ + + /* We want to get the time in total nanoseconds but need to be conscious of overflowing 32 bits. We also do not want to do 64 bit */ + /* division as that pulls in a division library. */ ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns. /* Have we overflowed 32 bits? */ if (ns_64bits <= UINT32_MAX) { /* No, we will not overflow. */ - loops_required = (uint32_t) ns_64bits; + cycles_requested = ((uint32_t) ns_64bits / ns_per_cycle); + loops_required = cycles_requested / BSP_DELAY_LOOP_CYCLES; } else { - /* We still overflowed, use the max count for cycles */ - loops_required = UINT32_MAX; + /* We did overflow. Try dividing down first. */ + total_us = (total_us / (ns_per_cycle * BSP_DELAY_LOOP_CYCLES)); + ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns. + + /* Have we overflowed 32 bits? */ + if (ns_64bits <= UINT32_MAX) + { + /* No, we will not overflow. */ + loops_required = (uint32_t) ns_64bits; + } + else + { + /* We still overflowed, use the max count for cycles */ + loops_required = UINT32_MAX; + } } } diff --git a/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c b/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c index 539e1a087..54e727c97 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c @@ -12,7 +12,12 @@ /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define BSP_GRP_IRQ_TOTAL_ITEMS (16U) + +#if (BSP_FEATURE_ICU_NMIER_MAX_INDEX > 15U) + #define BSP_PRV_NMIER_T uint32_t +#else + #define BSP_PRV_NMIER_T uint16_t +#endif /*********************************************************************************************************************** * Typedef definitions @@ -27,7 +32,7 @@ **********************************************************************************************************************/ /** This array holds callback functions. */ -bsp_grp_irq_cb_t g_bsp_group_irq_sources[BSP_GRP_IRQ_TOTAL_ITEMS] BSP_SECTION_EARLY_INIT; +bsp_grp_irq_cb_t g_bsp_group_irq_sources[BSP_FEATURE_ICU_NMIER_MAX_INDEX + 1] BSP_SECTION_EARLY_INIT; void NMI_Handler(void); static void bsp_group_irq_call(bsp_grp_irq_t irq); @@ -89,11 +94,11 @@ BSP_SECTION_FLASH_GAP fsp_err_t R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void (* BSP_SECTION_FLASH_GAP void NMI_Handler (void) { /* NMISR is masked by NMIER to prevent iterating over NMI status flags that are not enabled. */ - uint16_t nmier = R_ICU->NMIER; - uint16_t nmisr = R_ICU->NMISR & nmier; + BSP_PRV_NMIER_T nmier = R_ICU->NMIER; + BSP_PRV_NMIER_T nmisr = R_ICU->NMISR & nmier; /* Loop over all NMI status flags */ - for (bsp_grp_irq_t irq = BSP_GRP_IRQ_IWDT_ERROR; irq <= (bsp_grp_irq_t) (BSP_GRP_IRQ_TOTAL_ITEMS - 1); irq++) + for (bsp_grp_irq_t irq = BSP_GRP_IRQ_IWDT_ERROR; irq <= (bsp_grp_irq_t) (BSP_FEATURE_ICU_NMIER_MAX_INDEX); irq++) { /* If the current irq status register is set call the irq callback. */ if (0U != (nmisr & (1U << irq))) diff --git a/ra/fsp/src/bsp/mcu/all/bsp_irq.c b/ra/fsp/src/bsp/mcu/all/bsp_irq.c index f37fcd7a1..a4ca62a48 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_irq.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_irq.c @@ -17,6 +17,11 @@ #define BSP_IRQ_UINT32_MAX (0xFFFFFFFFU) #define BSP_PRV_BITS_PER_WORD (32) +#if BSP_ALT_BUILD + #define BSP_EVENT_NUM_TO_INTSELR(x) (x >> 5) // Convert event number to INTSELR register number + #define BSP_EVENT_NUM_TO_INTSELR_MASK(x) (1 << (x % 32)) // Convert event number to INTSELR bit mask +#endif + /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ @@ -253,6 +258,16 @@ BSP_SECTION_FLASH_GAP void bsp_irq_cfg (void) if (0U != g_interrupt_event_link_select[i]) { R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i]; + + #if BSP_ALT_BUILD + + /* Set INTSELR for selected events. */ + uint32_t intselr_num = BSP_EVENT_NUM_TO_INTSELR((uint32_t) g_interrupt_event_link_select[i]); + uint32_t intselr = R_ICU->INTSELR[intselr_num]; + + intselr |= BSP_EVENT_NUM_TO_INTSELR_MASK((uint32_t) g_interrupt_event_link_select[i]); + R_ICU->INTSELR[intselr_num] = intselr; + #endif } } #endif diff --git a/ra/fsp/src/bsp/mcu/all/bsp_irq.h b/ra/fsp/src/bsp/mcu/all/bsp_irq.h index 0350319d4..fa3abcc71 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_irq.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_irq.h @@ -122,7 +122,7 @@ __STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions * every time a priority is configured in the NVIC. */ #if (4U == __CORTEX_M) - NVIC->IP[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); + NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); #elif (33 == __CORTEX_M) NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); #elif (23 == __CORTEX_M) diff --git a/ra/fsp/src/bsp/mcu/all/bsp_macl.c b/ra/fsp/src/bsp/mcu/all/bsp_macl.c index e8de116e4..baf513d80 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_macl.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_macl.c @@ -16,6 +16,13 @@ * Macro definitions **********************************************************************************************************************/ + #ifndef INDEX_MASK + +/* This used to be defined in CMSIS DSP. But they have added an undef of the macro in utils.h and therefore it is no longer + * in scope for the uses of this file. */ + #define INDEX_MASK 0x0000003F + #endif + /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h index d3841c43a..9e092a4d8 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h @@ -73,12 +73,15 @@ FSP_HEADER /** @} (end addtogroup BSP_MCU) */ #if 0U == BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ - channel) ? (1U << 5U) : (1U << 6U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ + channel) ? (1U << 5U) : (1U << 6U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD #if BSP_MCU_GROUP_RA2A2 @@ -88,240 +91,271 @@ FSP_HEADER * Ch 4-5: MSTPD[ 1: 0] (AGT2, AGT3) * Ch 6-9: MSTPD[10: 7] (AGT4, AGT5, AGT6, AGT7) */ - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << \ - ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ - ? (3U - channel) \ - : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 2U) \ - ? (19U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ - : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 4U) \ - ? (1U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 2U) \ - : (10U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ - 4U))))); + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << \ + ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ + ? (3U - channel) \ + : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 2U) \ + ? (19U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ + : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 4U) \ + ? (1U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ + 2U) \ + : (10U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ + 4U))))); #else - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t + #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t #else #if (2U == BSP_FEATURE_ELC_VERSION) #if BSP_MCU_GROUP_RA6T2 - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t + #elif BSP_MCU_GROUP_NEPTUNE + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - ((channel >= 4U && channel <= 9U) ? 4U : channel))) // GPT Channels 4-9 share stop bits on this MCU + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (6U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t #else - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t #endif - #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); - #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_ULPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); + #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_ULPT(channel) uint32_t #else - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ - channel) ? (1U << (3U - channel)) : (1U << \ - (15U - (channel - 4U)))); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ + channel) ? (1U << (3U - channel)) : (1U << \ + (15U - (channel - 4U)))); + #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t #endif #endif -#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA -#define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DMAC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_EXTRA(channel) R_BSP_MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_EXTRA(channel) (1U << (16U)); + +#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U + channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_DMAC(channel) uint32_t + +#if BSP_FEATURE_CGC_REGISTER_SET_B + #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA + #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (6U)) + #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint16_t +#else + #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA + #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint32_t +#endif +#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_CAN(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_CEC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_I3C(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_I3C(channel) (1U << (BSP_FEATURE_I3C_MSTP_OFFSET - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_I3C(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_IRDA(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_QSPI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SAU(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_SAU(channel) (1U << (6U + channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SAU(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_IIC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_IICA(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IICA(channel) (1U << (10U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_IICA(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_USBFS(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_USBHS(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_EPTPC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_USBCC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBCC(channel) (1U << (14U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_USBCC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_ETHER(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_UARTA(channel) R_MSTP->MSTPCRB #if BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (6U)) - #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint16_t + #define BSP_MSTP_BIT_FSP_IP_UARTA(channel) (1U << (15U)); #else - #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint32_t + #define BSP_MSTP_BIT_FSP_IP_UARTA(channel) (1U << (0U)); #endif -#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CAN(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CEC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_I3C(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_I3C(channel) (1U << (BSP_FEATURE_I3C_MSTP_OFFSET - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_I3C(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IRDA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_QSPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SAU(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_SAU(channel) (1U << (6U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SAU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IIC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IICA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IICA(channel) (1U << (10U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IICA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBFS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBHS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_EPTPC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ETHER(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_UARTA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_UARTA(channel) (1U << (15U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_UARTA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_OSPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_REG_TYPE_FSP_IP_SCI(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CAC(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); -#define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CRC(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); -#define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_PDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CTSU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SLCDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_GLCDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_JPEG(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DRW(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SSI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SRC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_MIPI_DSI(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_MIPI_DSI(channel) (1U << (10U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_MIPI_DSI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SDHIMMC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DOC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ELC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_MACL(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_MACL(channel) (1U << (15U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_MACL(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CEU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CEU(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CEU(channel) (1U << (16U - channel)); -#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TFU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IIRFA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CANFD(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TRNG(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SCE(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_AES(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TAU(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TAU(channel) (1U << (0U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TAU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TML(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TML(channel) (1U << (4U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TML(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ADC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SDADC(channel) uint32_t +#define BSP_MSTP_REG_TYPE_FSP_IP_UARTA(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_OSPI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SPI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_REG_TYPE_FSP_IP_SCI(channel) uint32_t +#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_REG_TYPE_FSP_IP_CAC(channel) uint32_t +#define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); +#define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_REG_TYPE_FSP_IP_CRC(channel) uint32_t +#define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); +#define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_PDC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_CTSU(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SLCDC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_GLCDC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_JPEG(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_DRW(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SSI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SRC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_MIPI_DSI(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_MIPI_DSI(channel) (1U << (10U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_MIPI_DSI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SDHIMMC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_DOC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_ELC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_MACL(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_MACL(channel) (1U << (15U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_MACL(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_CEU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_REG_TYPE_FSP_IP_CEU(channel) uint32_t +#define BSP_MSTP_BIT_FSP_IP_CEU(channel) (1U << (16U - channel)); +#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_TFU(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_IIRFA(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_CANFD(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_TRNG(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SCE(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_AES(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_TAU(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_TAU(channel) (1U << (0U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_TAU(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_TML(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_TML(channel) (1U << (4U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_TML(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_ADC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SDADC(channel) uint32_t #if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U) - #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_DAC(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_DAC(channel) uint32_t #else - #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_DAC8(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_DAC(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_DAC8(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_DAC(channel) uint32_t #endif -#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TSN(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_RTC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_RTC(channel) (1U << (23U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_RTC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPHS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); -#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPLP(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_OPAMP(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_TSN(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_RTC(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_RTC(channel) (1U << (23U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_RTC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPHS(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); +#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPLP(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_OPAMP(channel) uint32_t #if (1U == BSP_FEATURE_CGC_HAS_OSTDCSE) - #define BSP_MSTP_REG_FSP_IP_SOSTD(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_SOSTD(channel) (1U << (16U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_SOSTD(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_MOSTD(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_MOSTD(channel) (1U << (17U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_MOSTD(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_SOSTD(channel) R_BSP_MSTPCRA + #define BSP_MSTP_BIT_FSP_IP_SOSTD(channel) (1U << (16U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_SOSTD(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_MOSTD(channel) R_BSP_MSTPCRA + #define BSP_MSTP_BIT_FSP_IP_MOSTD(channel) (1U << (17U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_MOSTD(channel) uint32_t #endif /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c b/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c index bcac583b7..a11cfc85e 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c @@ -112,7 +112,9 @@ BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps BSP_CFG_ROM_REG_PBPS0; #endif + #elif BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS +/* OFS NOT YET SUPPORTED FOR THIS PART */ #else /* CM33 & CM85 parts */ #if !BSP_TZ_NONSECURE_BUILD diff --git a/ra/fsp/src/bsp/mcu/all/bsp_sdram.c b/ra/fsp/src/bsp/mcu/all/bsp_sdram.c new file mode 100644 index 000000000..3e53af9ee --- /dev/null +++ b/ra/fsp/src/bsp/mcu/all/bsp_sdram.c @@ -0,0 +1,199 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_SDRAM + * @brief SDRAM initialization + * + * This file contains code that the initializes SDRAMC and SDR SDRAM device memory. + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Due to hardware limitations of the SDRAM peripheral, + * it is not expected any of these need to be changable by end user. + * Only sequential, single access at a time is supported. */ +#define BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC (1U) /* MR.M9 : Single Location Access */ +#define BSP_PRV_SDRAM_MR_OP_MODE (0U) /* MR.M8:M7 : Standard Operation */ +#define BSP_PRV_SDRAM_MR_BT_SEQUENTIAL (0U) /* MR.M3 Burst Type : Sequential */ +#define BSP_PRV_SDRAM_MR_BURST_LENGTH (0U) /* MR.M2:M0 Burst Length: 0(1 burst) */ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +#if 0 != BSP_FEATURE_SDRAM_START_ADDRESS + +/*******************************************************************************************************************//** + * @brief Initializes SDRAM. + * @param init_memory If true, this function will execute the initialization of the external modules. + * Otherwise, it will only initialize the SDRAMC and leave the memory in self-refresh mode. + * + * This function initializes SDRAMC and SDR SDRAM device. + * + * @note This function must only be called once after reset. + **********************************************************************************************************************/ +void R_BSP_SdramInit (bool init_memory) +{ + /** Setting for SDRAM initialization sequence */ + while (R_BUS->SDRAM.SDSR) + { + /* According to h/w manual, need to confirm that all the status bits in SDSR are 0 before SDICR modification. */ + } + + /* Must only write to SDIR once after reset. */ + R_BUS->SDRAM.SDIR = ((BSP_CFG_SDRAM_INIT_ARFI - 3U) << R_BUS_SDRAM_SDIR_ARFI_Pos) | + (BSP_CFG_SDRAM_INIT_ARFC << R_BUS_SDRAM_SDIR_ARFC_Pos) | + ((BSP_CFG_SDRAM_INIT_PRC - 3U) << R_BUS_SDRAM_SDIR_PRC_Pos); + + R_BUS->SDRAM.SDCCR = (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos); /* set SDRAM bus width */ + + if (init_memory) + { + /* Enable the SDCLK output. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + R_SYSTEM->SDCKOCR = 1; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + + /** If requested, start SDRAM initialization sequence. */ + R_BUS->SDRAM.SDICR = 1U; + while (R_BUS->SDRAM.SDSR_b.INIST) + { + /* Wait the end of initialization sequence. */ + } + } + + /** Setting for SDRAM controller */ + R_BUS->SDRAM.SDAMOD = BSP_CFG_SDRAM_ACCESS_MODE; /* enable continuous access */ + R_BUS->SDRAM.SDCMOD = BSP_CFG_SDRAM_ENDIAN_MODE; /* set endian mode for SDRAM address space */ + + while (R_BUS->SDRAM.SDSR) + { + /* According to h/w manual, need to confirm that all the status bits in SDSR are 0 before SDMOD modification. */ + } + + if (init_memory) + { + /** Using LMR command, program the mode register */ + R_BUS->SDRAM.SDMOD = (BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC << 9) | + (BSP_PRV_SDRAM_MR_OP_MODE << 7) | + (BSP_CFG_SDRAM_TCL << 4) | + (BSP_PRV_SDRAM_MR_BT_SEQUENTIAL << 3) | + (BSP_PRV_SDRAM_MR_BURST_LENGTH << 0); + + /** wait at least tMRD time */ + while (R_BUS->SDRAM.SDSR_b.MRSST) + { + /* Wait until Mode Register setting done. */ + } + } + + /** Set timing parameters for SDRAM. Must do in single write. */ + R_BUS->SDRAM.SDTR = ((BSP_CFG_SDRAM_TRAS - 1U) << R_BUS_SDRAM_SDTR_RAS_Pos) | + ((BSP_CFG_SDRAM_TRCD - 1U) << R_BUS_SDRAM_SDTR_RCD_Pos) | + ((BSP_CFG_SDRAM_TRP - 1U) << R_BUS_SDRAM_SDTR_RP_Pos) | + ((BSP_CFG_SDRAM_TWR - 1U) << R_BUS_SDRAM_SDTR_WR_Pos) | + (BSP_CFG_SDRAM_TCL << R_BUS_SDRAM_SDTR_CL_Pos); + + /** Set row address offset for target SDRAM */ + R_BUS->SDRAM.SDADR = BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT; + + /* Set Auto-Refresh timings. */ + R_BUS->SDRAM.SDRFCR = ((BSP_CFG_SDRAM_TREFW - 1U) << R_BUS_SDRAM_SDRFCR_REFW_Pos) | + ((BSP_CFG_SDRAM_TRFC - 1U) << R_BUS_SDRAM_SDRFCR_RFC_Pos); + + /** Start Auto-refresh */ + R_BUS->SDRAM.SDRFEN = 1U; + + if (init_memory) + { + /** Enable SDRAM access */ + R_BUS->SDRAM.SDCCR = R_BUS_SDRAM_SDCCR_EXENB_Msk | (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos); + } + else + { + /* If not initializing memory modules, start in self-refresh mode. */ + while (R_BUS->SDRAM.SDCCR_b.EXENB || (0U != R_BUS->SDRAM.SDSR)) + { + /* Wait for access to be disabled and no status bits set. */ + } + + /* Enable the self-refresh mode. */ + R_BUS->SDRAM.SDSELF = 1U; + } +} + +/*******************************************************************************************************************//** + * @brief Changes SDRAM from Auto-refresh to Self-refresh + * + * This function allows Software Standby and Deep Software Standby modes to be entered without data loss. + * + * @note SDRAM cannot be accessed after calling this function. Use @ref R_BSP_SdramSelfRefreshDisable to resume normal + * SDRAM operation. + **********************************************************************************************************************/ +void R_BSP_SdramSelfRefreshEnable (void) +{ + R_BUS->SDRAM.SDCCR = (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos); + while (R_BUS->SDRAM.SDCCR_b.EXENB || (0U != R_BUS->SDRAM.SDSR)) + { + /* Wait for access to be disabled and no status bits set. */ + } + + /* Enable the self-refresh mode. */ + R_BUS->SDRAM.SDSELF = 1U; +} + +/*******************************************************************************************************************//** + * @brief Changes SDRAM from Self-refresh to Auto-refresh + * + * This function changes back to Auto-refresh and allows normal SDRAM operation to resume. + * + **********************************************************************************************************************/ +void R_BSP_SdramSelfRefreshDisable (void) +{ + if (0 == R_SYSTEM->SDCKOCR) + { + /* Enable the SDCLK output. It may not already be enabled here if recovering from Deep Software Standby. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + R_SYSTEM->SDCKOCR = 1; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + } + + while (0U != R_BUS->SDRAM.SDSR) + { + /* Wait for all status bits to be cleared. */ + } + + /* Disable the self-refresh mode. */ + R_BUS->SDRAM.SDSELF = 0U; + + /* Reenable SDRAM bus access. */ + R_BUS->SDRAM.SDCCR = R_BUS_SDRAM_SDCCR_EXENB_Msk | (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos); +} + +#endif + +/** @} (end addtogroup BSP_SDRAM) */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_sdram.h b/ra/fsp/src/bsp/mcu/all/bsp_sdram.h new file mode 100644 index 000000000..6d84b6ca0 --- /dev/null +++ b/ra/fsp/src/bsp/mcu/all/bsp_sdram.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_SDRAM_H +#define BSP_SDRAM_H + +#if 0 != BSP_FEATURE_SDRAM_START_ADDRESS + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_SdramInit(bool init_memory); +void R_BSP_SdramSelfRefreshEnable(void); +void R_BSP_SdramSelfRefreshDisable(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif +#endif diff --git a/ra/fsp/src/bsp/mcu/all/bsp_security.c b/ra/fsp/src/bsp/mcu/all/bsp_security.c index 2306facdd..795eec179 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_security.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_security.c @@ -35,6 +35,13 @@ #define BSP_PRV_SAU_NS_REGION_3_BASE_ADDRESS (0x50000000U) #define BSP_PRV_SAU_NS_REGION_3_LIMIT_ADDRESS (0xDFFFFFFFU) +/* Protect DMAST from nonsecure write access. */ + #if (1U == BSP_CFG_CPU_CORE) + #define DMACX_REGISTER_SHIFT (16) + #else + #define DMACX_REGISTER_SHIFT (0) + #endif + /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ @@ -59,6 +66,7 @@ typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void); #if defined(__IAR_SYSTEMS_ICC__) && BSP_TZ_SECURE_BUILD +extern const uint32_t FLASH_NS_IMAGE_START; #pragma section=".tz_flash_ns_start" BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = (uint32_t *) __section_begin(".tz_flash_ns_start"); #pragma section="Veneer$$CMSE" @@ -489,7 +497,7 @@ void R_BSP_SecurityInit (void) #if BSP_FEATURE_BSP_HAS_TZFSAR /* Set TrustZone filter to Secure. */ - R_TZF->TZFSAR = ~R_TZF_TZFSAR_TZFSA0_Msk; + R_CPSCU->TZFSAR = ~R_CPSCU_TZFSAR_TZFSA0_Msk; #endif /* Set TrustZone filter exception response. */ @@ -506,51 +514,54 @@ void R_BSP_SecurityInit (void) /* Initialize Type 2 SARs. */ #ifdef BSP_TZ_CFG_CSAR - R_CPSCU->CSAR = BSP_TZ_CFG_CSAR; /* Cache Security Attribution. */ + R_CPSCU->CSAR = BSP_TZ_CFG_CSAR; /* Cache Security Attribution. */ #endif - R_SYSTEM->RSTSAR = BSP_TZ_CFG_RSTSAR; /* RSTSRn Security Attribution. */ - R_SYSTEM->LVDSAR = BSP_TZ_CFG_LVDSAR; /* LVD Security Attribution. */ - R_SYSTEM->CGFSAR = BSP_TZ_CFG_CGFSAR; /* CGC Security Attribution. */ - R_SYSTEM->LPMSAR = BSP_TZ_CFG_LPMSAR; /* LPM Security Attribution. */ - R_SYSTEM->DPFSAR = BSP_TZ_CFG_DPFSAR; /* Deep Standby Interrupt Factor Security Attribution. */ + R_SYSTEM->RSTSAR = BSP_TZ_CFG_RSTSAR; /* RSTSRn Security Attribution. */ + R_SYSTEM->LVDSAR = BSP_TZ_CFG_LVDSAR; /* LVD Security Attribution. */ + R_SYSTEM->CGFSAR = BSP_TZ_CFG_CGFSAR; /* CGC Security Attribution. */ + R_SYSTEM->LPMSAR = BSP_TZ_CFG_LPMSAR; /* LPM Security Attribution. */ + R_SYSTEM->DPFSAR = BSP_TZ_CFG_DPFSAR; /* Deep Standby Interrupt Factor Security Attribution. */ #ifdef BSP_TZ_CFG_RSCSAR - R_SYSTEM->RSCSAR = BSP_TZ_CFG_RSCSAR; /* RAM Standby Control Security Attribution. */ + R_SYSTEM->RSCSAR = BSP_TZ_CFG_RSCSAR; /* RAM Standby Control Security Attribution. */ #endif #ifdef BSP_TZ_CFG_PGCSAR - R_SYSTEM->PGCSAR = BSP_TZ_CFG_PGCSAR; /* Power Gating Control Security Attribution. */ + R_SYSTEM->PGCSAR = BSP_TZ_CFG_PGCSAR; /* Power Gating Control Security Attribution. */ #endif #ifdef BSP_TZ_CFG_BBFSAR - R_SYSTEM->BBFSAR = BSP_TZ_CFG_BBFSAR; /* Battery Backup Security Attribution. */ + R_SYSTEM->BBFSAR = BSP_TZ_CFG_BBFSAR; /* Battery Backup Security Attribution. */ #endif - R_CPSCU->ICUSARA = BSP_TZ_CFG_ICUSARA; /* External IRQ Security Attribution. */ - R_CPSCU->ICUSARB = BSP_TZ_CFG_ICUSARB; /* NMI Security Attribution. */ + R_CPSCU->ICUSARA = BSP_TZ_CFG_ICUSARA; /* External IRQ Security Attribution. */ + R_CPSCU->ICUSARB = BSP_TZ_CFG_ICUSARB; /* NMI Security Attribution. */ #ifdef BSP_TZ_CFG_ICUSARC - R_CPSCU->ICUSARC = BSP_TZ_CFG_ICUSARC; /* DMAC Channel Security Attribution. */ + R_CPSCU->ICUSARC = BSP_TZ_CFG_ICUSARC; /* DMAC Channel Security Attribution. */ #endif #ifdef BSP_TZ_CFG_DMACCHSAR - R_CPSCU->DMACCHSAR = BSP_TZ_CFG_DMACCHSAR; /* DMAC Channel Security Attribution. */ + R_CPSCU->DMACCHSAR |= (BSP_TZ_CFG_DMACCHSAR << DMACX_REGISTER_SHIFT); /* DMAC Channel Security Attribution. */ #endif #ifdef BSP_TZ_CFG_ICUSARD - R_CPSCU->ICUSARD = BSP_TZ_CFG_ICUSARD; /* SELSR0 Security Attribution. */ + R_CPSCU->ICUSARD = BSP_TZ_CFG_ICUSARD; /* SELSR0 Security Attribution. */ #endif - R_CPSCU->ICUSARE = BSP_TZ_CFG_ICUSARE; /* WUPEN0 Security Attribution. */ + R_CPSCU->ICUSARE = BSP_TZ_CFG_ICUSARE; /* WUPEN0 Security Attribution. */ #ifdef BSP_TZ_CFG_ICUSARF - R_CPSCU->ICUSARF = BSP_TZ_CFG_ICUSARF; /* WUPEN1 Security Attribution. */ + R_CPSCU->ICUSARF = BSP_TZ_CFG_ICUSARF; /* WUPEN1 Security Attribution. */ #endif #ifdef BSP_TZ_CFG_TEVTRCR - R_CPSCU->TEVTRCR = BSP_TZ_CFG_TEVTRCR; /* Trusted Event Route Enable. */ + R_CPSCU->TEVTRCR = BSP_TZ_CFG_TEVTRCR; /* Trusted Event Route Enable. */ #endif #ifdef BSP_TZ_CFG_ELCSARA - R_ELC->ELCSARA = BSP_TZ_CFG_ELCSARA; /* ELCR, ELSEGR0, ELSEGR1 Security Attribution. */ + R_ELC->ELCSARA = BSP_TZ_CFG_ELCSARA; /* ELCR, ELSEGR0, ELSEGR1 Security Attribution. */ #endif - R_FCACHE->FSAR = BSP_TZ_CFG_FSAR; /* FLWT and FCKMHZ Security Attribution. */ - R_CPSCU->SRAMSAR = BSP_TZ_CFG_SRAMSAR; /* SRAM Security Attribution. */ + R_FCACHE->FSAR = BSP_TZ_CFG_FSAR; /* FLWT and FCKMHZ Security Attribution. */ + R_CPSCU->SRAMSAR = BSP_TZ_CFG_SRAMSAR; /* SRAM Security Attribution. */ #ifdef BSP_TZ_CFG_STBRAMSAR - R_CPSCU->STBRAMSAR = BSP_TZ_CFG_STBRAMSAR; /* Standby RAM Security Attribution. */ + R_CPSCU->STBRAMSAR = BSP_TZ_CFG_STBRAMSAR; /* Standby RAM Security Attribution. */ + #endif + R_CPSCU->MMPUSARA = BSP_TZ_CFG_MMPUSARA; /* Security Attribution for the DMAC Bus Master MPU. */ + R_CPSCU->BUSSARA = BSP_TZ_CFG_BUSSARA; /* Security Attribution Register A for the BUS Control Registers. */ + R_CPSCU->BUSSARB = BSP_TZ_CFG_BUSSARB; /* Security Attribution Register B for the BUS Control Registers. */ + #ifdef BSP_TZ_CFG_BUSSARC + R_CPSCU->BUSSARC = BSP_TZ_CFG_BUSSARC; /* Security Attribution Register C for the BUS Control Registers. */ #endif - R_CPSCU->MMPUSARA = BSP_TZ_CFG_MMPUSARA; /* Security Attribution for the DMAC Bus Master MPU. */ - R_CPSCU->BUSSARA = BSP_TZ_CFG_BUSSARA; /* Security Attribution Register A for the BUS Control Registers. */ - R_CPSCU->BUSSARB = BSP_TZ_CFG_BUSSARB; /* Security Attribution Register B for the BUS Control Registers. */ #if (defined(BSP_TZ_CFG_ICUSARC) && (BSP_TZ_CFG_ICUSARC != UINT32_MAX)) || \ (defined(BSP_TZ_CFG_DMACCHSAR) && \ @@ -565,7 +576,7 @@ void R_BSP_SecurityInit (void) /* If any DMAC channels are required by secure program, disable nonsecure write access to DMAST * in order to prevent the nonsecure program from disabling all DMAC channels. */ - R_CPSCU->DMACSAR = ~1U; /* Protect DMAST from nonsecure write access. */ + R_CPSCU->DMACSAR &= ~(1U << DMACX_REGISTER_SHIFT); /* Protect DMAST from nonsecure write access. */ #endif /* Ensure that DMAST is set so that the nonsecure program can use DMA. */ diff --git a/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature.h index 8c6c8038e..3d47f1c08 100644 --- a/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature.h @@ -78,13 +78,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (0) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -103,7 +103,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0) // Feature not available on this MCU @@ -188,6 +188,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL #define BSP_FEATURE_CGC_REGISTER_SET_B (1) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x06U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (0) @@ -238,11 +239,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU #define BSP_FEATURE_DOC_VERSION (0U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (0U) #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x1F800000U) // Deprecated (Removing in FSP v6.0) @@ -279,24 +283,24 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x1) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (0U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0U) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0U) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (0U) #define BSP_FEATURE_ICU_HAS_IELSR (0U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) -#define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x3FU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (8U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x00000000U) #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0x3838C1404FFULL) @@ -332,15 +336,16 @@ #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) -#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_STCONR (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (1) #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (1) #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (1) -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (1) +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (1) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0U) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) @@ -390,6 +395,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x0U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (0U) #define BSP_FEATURE_SCI_VERSION (0U) +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -435,4 +441,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature_gen.h index 18e41b9e5..57320ed0c 100644 --- a/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (0) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_OPS_SUPPORTED (0) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_PRESENT (0) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_D_PRESENT (1) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGT_PRESENT (0) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_PRESENT (0) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_PRESENT (0) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC12_PRESENT (0) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC_PRESENT (0) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_PRESENT (0) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_PRESENT (0) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (1) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_PRESENT (0) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0x3F) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IICA_PRESENT (1) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_PRESENT (0) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (1) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PORGA_PRESENT (1) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x21F) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_PRESENT (0) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_C_PRESENT (1) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SAU_PRESENT (1) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0x100801) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (1) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0x100801) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0x7) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (1) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_TAU_PRESENT (1) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TML_PRESENT (1) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TRNG_PRESENT (1) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_PRESENT (0) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_PRESENT (0) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_PRESENT (0) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_UARTA_PRESENT (1) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_PRESENT (0) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_FS_PRESENT (0) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_PRESENT (0) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_elc.h index 046a00345..f4e69c55b 100644 --- a/ra/fsp/src/bsp/mcu/ra2a1/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra2a1/bsp_elc.h @@ -59,7 +59,7 @@ typedef enum e_elc_event_ra2a1 ELC_EVENT_AGT1_COMPARE_A = (0x015), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x016), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x017), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x018), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x018), // WDT underflow ELC_EVENT_RTC_ALARM = (0x019), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x01A), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x01B), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h index 0ff47a65a..8014ae1df 100644 --- a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h @@ -78,13 +78,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -103,7 +103,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. @@ -185,11 +185,13 @@ #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU + #define BSP_FEATURE_CGC_PLLCCR_TYPE (0U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (0U) #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -240,11 +242,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (1U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (0U) #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x005CD30FU) // Deprecated (Removing in FSP v6.0) @@ -281,25 +286,25 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x1) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x7F) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB8F00FFU) #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -340,7 +345,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) @@ -395,6 +401,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -440,4 +447,18 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (1U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (1U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (1U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (1U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (1U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_HAS_NOT_HOST (1U) + #endif diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature_gen.h index 18e41b9e5..7210f1ef2 100644 --- a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x7F) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x7F) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_OPS_SUPPORTED (0) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ACMP_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (1) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_AES_PRESENT (1) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_PRESENT (0) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CTSU_PRESENT (1) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC8_PRESENT (1) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_PRESENT (0) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (1) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x7F) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_KINT_PRESENT (1) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MMF_PRESENT (1) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0x7) +#define BSP_PERIPHERAL_OPAMP_PRESENT (1) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PMISC_PRESENT (1) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x23F) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x203) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0x1000001) +#define BSP_PERIPHERAL_SDADC_PRESENT (1) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SPMON_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TRNG_PRESENT (1) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_PRESENT (0) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_PRESENT (0) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra2a2/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra2a2/bsp_elc.h index e5947bf03..dbfe16727 100644 --- a/ra/fsp/src/bsp/mcu/ra2a2/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra2a2/bsp_elc.h @@ -59,7 +59,7 @@ typedef enum e_elc_event_ra2a2 ELC_EVENT_AGTW1_COMPARE_A = (0x015), // Compare match A ELC_EVENT_AGTW1_COMPARE_B = (0x016), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x017), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x018), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x018), // WDT underflow ELC_EVENT_RTC_ALARM_0 = (0x019), // Alarm 0 interrupt ELC_EVENT_RTC_PERIOD = (0x01A), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x01B), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature.h index 0b11ee9bd..c4b695418 100644 --- a/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature.h @@ -78,12 +78,12 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (0) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (1U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,7 +107,7 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x000FFFFFU) #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (3U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. @@ -187,6 +187,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -236,11 +237,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (0U) #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0000C30FU) // Deprecated (Removing in FSP v6.0) @@ -277,18 +281,17 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3F0) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) @@ -296,6 +299,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x1FFFBFD0FFFULL) // Note there is another WUPEN1 register #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (36U) @@ -336,7 +340,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (1U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x73800FFFU) @@ -394,6 +399,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -439,4 +445,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature_gen.h index 18e41b9e5..b96ac490d 100644 --- a/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3F0) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3F0) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_OPS_SUPPORTED (0) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ACMP_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_AES_PRESENT (1) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGTW_PRESENT (1) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_PRESENT (0) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC12_PRESENT (0) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC_PRESENT (0) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_PRESENT (0) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (1) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3F0) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IRTC_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MACL_PRESENT (1) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MMF_PRESENT (1) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x7F) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_PRESENT (0) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x20F) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SLCDC_PRESENT (1) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TRNG_PRESENT (1) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_PRESENT (0) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_PRESENT (0) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_PRESENT (0) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_PRESENT (0) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_FS_PRESENT (0) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra2e1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra2e1/bsp_elc.h index 27b346196..99a5b7184 100644 --- a/ra/fsp/src/bsp/mcu/ra2e1/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra2e1/bsp_elc.h @@ -59,7 +59,7 @@ typedef enum e_elc_event_ra2e1 ELC_EVENT_AGT1_COMPARE_A = (0x015), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x016), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x017), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x018), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x018), // WDT underflow ELC_EVENT_RTC_ALARM = (0x019), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x01A), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x01B), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h index 2b1576a23..b187105cf 100644 --- a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h @@ -78,13 +78,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (0) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (1U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -103,7 +103,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0) // Feature not available on this MCU @@ -188,6 +188,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -238,11 +239,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (0U) #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0004C30FU) // Deprecated (Removing in FSP v6.0) @@ -279,24 +283,24 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x1) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3F1) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (1U) -#define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0xF38F00FFU) #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -337,7 +341,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) @@ -392,6 +397,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -437,4 +443,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature_gen.h index 18e41b9e5..290c41b4b 100644 --- a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3F0) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3F0) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_OPS_SUPPORTED (0) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ACMP_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (1) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_AES_PRESENT (1) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_PRESENT (0) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CTSU_PRESENT (1) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC12_PRESENT (0) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC_PRESENT (0) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_PRESENT (0) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (1) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3F1) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_KINT_PRESENT (1) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x23F) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x207) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TRNG_PRESENT (1) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_PRESENT (0) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_PRESENT (0) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_PRESENT (0) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_PRESENT (0) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_FS_PRESENT (0) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra2e2/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra2e2/bsp_elc.h index 07defdc73..21e64c300 100644 --- a/ra/fsp/src/bsp/mcu/ra2e2/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra2e2/bsp_elc.h @@ -58,7 +58,7 @@ typedef enum e_elc_event_ra2e2 ELC_EVENT_AGT1_COMPARE_A = (0x015), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x016), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x017), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x018), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x018), // WDT underflow ELC_EVENT_ADC0_SCAN_END = (0x01C), // End of A/D scanning operation ELC_EVENT_ADC0_SCAN_END_B = (0x01D), // A/D scan end interrupt for group B ELC_EVENT_ADC0_WINDOW_A = (0x01E), // Window A Compare match interrupt diff --git a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h index f9df1a198..d99dc1a6e 100644 --- a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h @@ -78,13 +78,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (0) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (1U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -103,7 +103,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0) // Feature not available on this MCU @@ -188,6 +188,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -238,11 +239,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (0U) #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0000C30FU) // Deprecated (Removing in FSP v6.0) @@ -279,25 +283,25 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3F0) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (4U) #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (2U) #define BSP_FEATURE_I3C_NUM_CHANNELS (1U) #define BSP_FEATURE_I3C_MSTP_OFFSET (9U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (1U) -#define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x0FU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x700F00FFU) #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -338,7 +342,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000001FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x700200FFU) @@ -393,6 +398,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (0U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -438,4 +444,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature_gen.h index 18e41b9e5..ed45f36d6 100644 --- a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3F0) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3F0) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_OPS_SUPPORTED (0) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_AES_PRESENT (1) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGTW_PRESENT (1) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_PRESENT (0) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC12_PRESENT (0) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC_PRESENT (0) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_PRESENT (0) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (1) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3F0) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_I3C_PRESENT (1) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC_B_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_KINT_PRESENT (1) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x21F) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_PRESENT (0) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x200) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TRNG_PRESENT (1) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_PRESENT (0) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_PRESENT (0) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_PRESENT (0) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_PRESENT (0) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_FS_PRESENT (0) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra2e3/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra2e3/bsp_elc.h index 16b09755c..afe61dd9c 100644 --- a/ra/fsp/src/bsp/mcu/ra2e3/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra2e3/bsp_elc.h @@ -59,7 +59,7 @@ typedef enum e_elc_event_ra2e3 ELC_EVENT_AGT1_COMPARE_A = (0x015), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x016), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x017), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x018), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x018), // WDT underflow ELC_EVENT_RTC_ALARM = (0x019), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x01A), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x01B), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature.h index 349bea4bb..54545e9a0 100644 --- a/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature.h @@ -78,13 +78,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (0) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (1U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -103,7 +103,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0) // Feature not available on this MCU @@ -188,6 +188,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -238,11 +239,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_DELSR (0U) // Feature not available on this MCU +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (0U) #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0004C30FU) // Deprecated (Removing in FSP v6.0) @@ -279,31 +283,31 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x1) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3F1) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (1U) -#define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0xF38F00FFU) -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) // Feature not available on this MCU -#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) // Feature not available on this MCU -#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU -#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) #define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x01) #define BSP_FEATURE_IIC_VERSION (1U) @@ -338,7 +342,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) @@ -391,6 +396,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -436,4 +442,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature_gen.h index 18e41b9e5..afadb8446 100644 --- a/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3F0) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3F0) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_OPS_SUPPORTED (0) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_PRESENT (0) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC12_PRESENT (0) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC_PRESENT (0) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_PRESENT (0) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (1) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3F1) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_KINT_PRESENT (1) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x23F) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x207) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_PRESENT (0) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_PRESENT (0) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_PRESENT (0) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_PRESENT (0) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_FS_PRESENT (0) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h index 4e4914628..192247363 100644 --- a/ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h @@ -59,7 +59,7 @@ typedef enum e_elc_event_ra2l1 ELC_EVENT_AGT1_COMPARE_A = (0x015), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x016), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x017), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x018), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x018), // WDT underflow ELC_EVENT_RTC_ALARM = (0x019), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x01A), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x01B), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h index 2e7e4d157..afc9ae31f 100644 --- a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h @@ -78,13 +78,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (0) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (1U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (1U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -103,7 +103,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. @@ -188,6 +188,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -238,11 +239,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (1U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) -#define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU +#define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (0U) #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0004D30FU) // Deprecated (Removing in FSP v6.0) @@ -279,25 +283,25 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0xF) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FF) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (1U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0xF38F00FFU) #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -338,7 +342,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) @@ -393,6 +398,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -438,4 +444,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature_gen.h index 18e41b9e5..dd53e77cc 100644 --- a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3FF) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3FF) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_OPS_SUPPORTED (0) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ACMP_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (1) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_AES_PRESENT (1) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_PRESENT (0) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CTSU_PRESENT (1) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_PRESENT (0) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (1) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FF) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_KINT_PRESENT (1) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x1FF) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x20F) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TRNG_PRESENT (1) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_PRESENT (0) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_PRESENT (0) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_PRESENT (0) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_PRESENT (0) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_FS_PRESENT (0) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra4e1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra4e1/bsp_elc.h index ecfddd295..93506dadc 100644 --- a/ra/fsp/src/bsp/mcu/ra4e1/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra4e1/bsp_elc.h @@ -81,7 +81,7 @@ typedef enum e_elc_event_ra4e1 ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h index 976c0396e..868349c1f 100644 --- a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h @@ -82,13 +82,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,7 +107,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) @@ -192,6 +192,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -242,11 +243,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (1U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // This MCU has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0003D1FFU) // Deprecated (Removing in FSP v6.0) @@ -283,18 +287,17 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x06U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x36U) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) @@ -302,6 +305,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x23FFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (13U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0D23FFULL) // Note there is another WUPEN1 register #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -342,7 +346,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register @@ -397,6 +402,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0U) // Feature not available on this MCU @@ -442,4 +448,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature_gen.h index 18e41b9e5..92fef1a30 100644 --- a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x36) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x36) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_OPS_SUPPORTED (0) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x2F) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x36) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0x23FF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x3F) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_QSPI_PRESENT (1) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE9_PRESENT (1) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x219) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_PRESENT (0) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_PRESENT (0) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra4e2/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra4e2/bsp_elc.h index 98a087cbb..7c2d49185 100644 --- a/ra/fsp/src/bsp/mcu/ra4e2/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra4e2/bsp_elc.h @@ -75,7 +75,7 @@ typedef enum e_elc_event_ra4e2 ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h index 7374dc21f..79f7c315e 100644 --- a/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h @@ -82,13 +82,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -106,7 +106,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA4E2 there are specific registers for configuring the USB clock. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) @@ -191,6 +191,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -240,11 +241,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (1U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA4E2 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0083F3FFU) // Deprecated (Removing in FSP v6.0) @@ -281,18 +285,17 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x00U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x33U) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) #define BSP_FEATURE_I3C_NUM_CHANNELS (1U) #define BSP_FEATURE_I3C_MSTP_OFFSET (4U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) @@ -300,6 +303,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x7FFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x8007B0D7FFFULL) // Note there is another WUPEN1 register #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -340,7 +344,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x73007FFFU) @@ -395,6 +400,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -440,4 +446,18 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (1U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module +#define BSP_FEATURE_USB_HAS_NOT_HOST (1U) + #endif diff --git a/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature_gen.h index 7a195e621..1b92ef4c3 100644 --- a/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x33) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x33) -#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x33) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x1) -#define BSP_FEATURE_GPT_OPS_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CACHE_PRESENT (1) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CANFD_PRESENT (1) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CEC_PRESENT (1) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x33) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_I3C_PRESENT (1) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0x7FFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC_B_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x13F) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x201) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_elc.h index 2efcd253d..7c9607a6a 100644 --- a/ra/fsp/src/bsp/mcu/ra4m1/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra4m1/bsp_elc.h @@ -71,7 +71,7 @@ typedef enum e_elc_event_ra4m1 ELC_EVENT_AGT1_COMPARE_A = (0x022), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x023), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x024), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x025), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x025), // WDT underflow ELC_EVENT_RTC_ALARM = (0x026), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x027), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x028), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h index b1a1cd538..a4734f38d 100644 --- a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h @@ -78,13 +78,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -103,7 +103,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. @@ -190,6 +190,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (1U) // 1 us wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1U) // RA4M1 requires that bits 16-18 of SCKDIVCR be the same as the bits for PCKB +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -240,11 +241,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (1U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (4U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M1 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007D3FFU) // Deprecated (Removing in FSP v6.0) @@ -281,25 +285,25 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0xFF) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xDFFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB9FDFFFU) #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -340,7 +344,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7382DFFFU) @@ -395,6 +400,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -440,4 +446,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (1U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (1U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature_gen.h index 18e41b9e5..fb798d8ab 100644 --- a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0xFF) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0xFF) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_OPS_SUPPORTED (0) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ACMP_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (1) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_PRESENT (0) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CTSU_PRESENT (1) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC8_PRESENT (1) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (1) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xDFFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_KINT_PRESENT (1) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_OPAMP_PRESENT (1) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PMISC_PRESENT (1) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x3FF) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE5_PRESENT (1) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x207) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SLCDC_PRESENT (1) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SPMON_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_PRESENT (0) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_PRESENT (0) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h index 7821eba7f..e54a525de 100644 --- a/ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h @@ -89,7 +89,7 @@ typedef enum e_elc_event_ra4m2 ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h index cf6db947e..188e03b3d 100644 --- a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h @@ -82,13 +82,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,7 +107,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA4M2 there are specific registers for configuring the USB clock. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) @@ -192,6 +192,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -242,11 +243,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M2 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007F3FFU) // Deprecated (Removing in FSP v6.0) @@ -283,18 +287,17 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FU) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0xFFU) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) @@ -302,6 +305,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (13U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -342,7 +346,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000019FU) // note there is another SNZEDCR1 register #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register @@ -397,6 +402,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -442,4 +448,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature_gen.h index 18e41b9e5..1169bc148 100644 --- a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0xFF) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0xFF) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_OPS_SUPPORTED (0) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3F) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CTSU_PRESENT (1) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_QSPI_PRESENT (1) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE9_PRESENT (1) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x21F) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra4m3/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra4m3/bsp_elc.h index acae0d54b..6f62bf13b 100644 --- a/ra/fsp/src/bsp/mcu/ra4m3/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra4m3/bsp_elc.h @@ -89,7 +89,7 @@ typedef enum e_elc_event_ra4m3 ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h index eed57a46a..906cd9b88 100644 --- a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h @@ -82,13 +82,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,7 +107,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA4M3 there are specific registers for configuring the USB clock. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) @@ -193,6 +193,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -243,11 +244,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M3 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Deprecated (Removing in FSP v6.0) @@ -284,18 +288,17 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FU) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0xFFU) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) @@ -303,6 +306,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -343,7 +347,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register @@ -398,6 +403,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -443,4 +449,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature_gen.h index 18e41b9e5..0fa5716a8 100644 --- a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0xFF) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0xFF) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_OPS_SUPPORTED (0) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3F) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CACHE_PRESENT (1) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CTSU_PRESENT (1) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x1FF) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_QSPI_PRESENT (1) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE9_PRESENT (1) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x21F) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra4t1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra4t1/bsp_elc.h index b24ad1a8a..1489cc18d 100644 --- a/ra/fsp/src/bsp/mcu/ra4t1/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra4t1/bsp_elc.h @@ -75,7 +75,7 @@ typedef enum e_elc_event_ra4t1 ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow ELC_EVENT_CAN_RXF = (0x059), // Global recieve FIFO interrupt ELC_EVENT_CAN_GLERR = (0x05A), // Global error ELC_EVENT_CAN_DMAREQ0 = (0x05B), // RX fifo DMA request 0 diff --git a/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h index b7bfc9958..96ef7ddde 100644 --- a/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h @@ -82,13 +82,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,7 +107,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) // On the RA6M5 there are specific registers for configuring the USB clock. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) @@ -192,6 +192,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -242,11 +243,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA4T1 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0083F3FFU) // Deprecated (Removing in FSP v6.0) @@ -283,18 +287,17 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x00U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FU) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) #define BSP_FEATURE_I3C_NUM_CHANNELS (1U) #define BSP_FEATURE_I3C_MSTP_OFFSET (4U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) @@ -302,6 +305,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x7FFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x800700D7FFFULL) // Note there is another WUPEN1 register #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -342,7 +346,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x70407FFFU) @@ -397,6 +402,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -442,4 +448,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature_gen.h index 9e68fc984..0af368c68 100644 --- a/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3F) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x3F) -#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3F) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x1) -#define BSP_FEATURE_GPT_OPS_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x7) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CACHE_PRESENT (1) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CANFD_PRESENT (1) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3F) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_I3C_PRESENT (1) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0x7FFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC_B_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x13F) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_PRESENT (0) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x201) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_PRESENT (0) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_FS_PRESENT (0) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_elc.h index c7a399058..51ea670c3 100644 --- a/ra/fsp/src/bsp/mcu/ra4w1/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra4w1/bsp_elc.h @@ -67,7 +67,7 @@ typedef enum e_elc_event_ra4w1 ELC_EVENT_AGT1_COMPARE_A = (0x022), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x023), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x024), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x025), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x025), // WDT underflow ELC_EVENT_RTC_ALARM = (0x026), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x027), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x028), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h index 4579d6f9a..a868aebbe 100644 --- a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h @@ -78,13 +78,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1U) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -103,7 +103,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. @@ -190,6 +190,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (1U) // 1 us wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1U) // RA4W1 requires that bits 16-18 of SCKDIVCR be the same as the bits for PCKB +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -240,11 +241,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (1U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (4U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA4W1 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007D3FFU) // Deprecated (Removing in FSP v6.0) @@ -281,25 +285,25 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0xF) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x13F) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xCBDFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB97CADFU) #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -340,7 +344,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7382CADFU) @@ -395,6 +400,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -440,4 +446,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (1U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (1U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature_gen.h index 18e41b9e5..a3e3c8139 100644 --- a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x13F) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) -#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) -#define BSP_FEATURE_GPT_OPS_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x13F) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) +#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ACMP_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (1) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_PRESENT (0) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CTSU_PRESENT (1) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC8_PRESENT (1) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (1) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x13F) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xCBDF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x7) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_KINT_PRESENT (1) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MMF_PRESENT (1) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0x5) +#define BSP_PERIPHERAL_OPAMP_PRESENT (1) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PMISC_PRESENT (1) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x3FF) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RADIO_PRESENT (1) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE5_PRESENT (1) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x213) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SLCDC_PRESENT (1) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SPMON_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_PRESENT (0) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_PRESENT (0) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra6e1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6e1/bsp_elc.h index 3044b2f93..918fe935d 100644 --- a/ra/fsp/src/bsp/mcu/ra6e1/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra6e1/bsp_elc.h @@ -89,7 +89,7 @@ typedef enum e_elc_event_ra6e1 ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h index 453a0ac90..76a5afb11 100644 --- a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h @@ -82,13 +82,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,7 +107,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) @@ -192,6 +192,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -242,11 +243,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (1U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // This MCU has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0003D3FFU) // Deprecated (Removing in FSP v6.0) @@ -283,18 +287,17 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x06U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x0F6U) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) @@ -302,6 +305,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -342,7 +346,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000019FU) // note there is another SNZEDCR1 register #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register @@ -397,6 +402,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -442,4 +448,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature_gen.h index 18e41b9e5..e4e9dc17d 100644 --- a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0xF6) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0xF6) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_OPS_SUPPORTED (0) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3F) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CACHE_PRESENT (1) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0xF6) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_QSPI_PRESENT (1) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE9_PRESENT (1) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x21F) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_PRESENT (0) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_PRESENT (0) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra6e2/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6e2/bsp_elc.h index e67044319..0f200f06c 100644 --- a/ra/fsp/src/bsp/mcu/ra6e2/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra6e2/bsp_elc.h @@ -75,7 +75,7 @@ typedef enum e_elc_event_ra6e2 ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h index b94c5d16b..87ceab996 100644 --- a/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h @@ -82,13 +82,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -106,7 +106,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA6E2 there are specific registers for configuring the USB clock. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) @@ -191,6 +191,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -240,11 +241,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA6E2 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0083F3FFU) // Deprecated (Removing in FSP v6.0) @@ -281,18 +285,17 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x00U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FU) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) #define BSP_FEATURE_I3C_NUM_CHANNELS (1U) #define BSP_FEATURE_I3C_MSTP_OFFSET (4U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) @@ -300,6 +303,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x7FFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x8007B0D7FFFULL) // Note there is another WUPEN1 register #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -340,7 +344,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x73007FFFU) @@ -395,6 +400,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -440,4 +446,18 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (1U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module +#define BSP_FEATURE_USB_HAS_NOT_HOST (1U) + #endif diff --git a/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature_gen.h index 9e68fc984..d7c9e64a0 100644 --- a/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3F) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x3F) -#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3F) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x1) -#define BSP_FEATURE_GPT_OPS_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CACHE_PRESENT (1) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CANFD_PRESENT (1) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CEC_PRESENT (1) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3F) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_I3C_PRESENT (1) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0x7FFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC_B_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x13F) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_QSPI_PRESENT (1) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x201) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_elc.h index 837c5ec6a..dec904987 100644 --- a/ra/fsp/src/bsp/mcu/ra6m1/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra6m1/bsp_elc.h @@ -74,7 +74,7 @@ typedef enum e_elc_event_ra6m1 ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x046), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT underflow ELC_EVENT_RTC_ALARM = (0x048), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x049), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x04A), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h index 86235967e..4ea8d9ee8 100644 --- a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h @@ -82,13 +82,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,7 +107,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. @@ -194,6 +194,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -244,11 +245,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M1 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Deprecated (Removing in FSP v6.0) @@ -285,25 +289,25 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x1FFF) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (120000000U) #define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000U) -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0x0FU) #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x1FFF) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x3FFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB4FFFFFU) #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -344,7 +348,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) @@ -399,6 +404,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -444,4 +450,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (1U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0xEU) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature_gen.h index bb56c5002..2502d074a 100644 --- a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x1FFF) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0xF0) -#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0xF) -#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (1) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x1FFF) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x1) -#define BSP_FEATURE_GPT_OPS_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ACMP_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x3F) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_PRESENT (0) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CTSU_PRESENT (1) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x1FFF) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0x3FFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IRDA_PRESENT (1) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_KINT_PRESENT (1) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MMF_PRESENT (1) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PMISC_PRESENT (1) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_QSPI_PRESENT (1) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE7_PRESENT (1) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x31F) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SPMON_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRC_PRESENT (1) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (1) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_PRESENT (0) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_elc.h index 1276c76b6..ea413b460 100644 --- a/ra/fsp/src/bsp/mcu/ra6m2/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra6m2/bsp_elc.h @@ -76,7 +76,7 @@ typedef enum e_elc_event_ra6m2 ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x046), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT underflow ELC_EVENT_RTC_ALARM = (0x048), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x049), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x04A), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h index 2e601f050..22df2bc48 100644 --- a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h @@ -82,13 +82,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,7 +107,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) @@ -194,6 +194,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -244,11 +245,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M2 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Deprecated (Removing in FSP v6.0) @@ -285,25 +289,25 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3FFF) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (120000000U) #define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000U) -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0x0FU) #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFF) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB4FFFFFU) #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -344,7 +348,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) @@ -399,6 +404,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -444,4 +450,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (1U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0xEU) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature_gen.h index bb56c5002..c38b79d53 100644 --- a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3FFF) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0xF0) -#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0xF) -#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (1) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3FFF) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x1) -#define BSP_FEATURE_GPT_OPS_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ACMP_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x3F) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_AMI_PRESENT (1) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_PRESENT (0) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CTSU_PRESENT (1) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FFF) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x7) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IRDA_PRESENT (1) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_KINT_PRESENT (1) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MMF_PRESENT (1) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PDC_PRESENT (1) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PMISC_PRESENT (1) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0xFFF) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_QSPI_PRESENT (1) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE7_PRESENT (1) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x3FF) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SPMON_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRC_PRESENT (1) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (1) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_PRESENT (0) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_PRESENT (0) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_HS_PRESENT (1) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h index 2fbf48002..58f62ee01 100644 --- a/ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h @@ -76,7 +76,7 @@ typedef enum e_elc_event_ra6m3 ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x046), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT underflow ELC_EVENT_RTC_ALARM = (0x048), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x049), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x04A), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h index 14853b8c1..f312d3a1a 100644 --- a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h @@ -82,13 +82,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,7 +107,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. @@ -194,6 +194,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -244,11 +245,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M3 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Deprecated (Removing in FSP v6.0) @@ -285,25 +289,25 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3FFF) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (120000000U) #define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000U) -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0x0FU) #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFF) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0xFF4FFFFFU) #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -344,7 +348,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) @@ -399,6 +404,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -444,4 +450,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (1U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (1U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0xEU) +#define BSP_FEATURE_USB_HAS_USBHS_BC (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature_gen.h index bb56c5002..b7be761e1 100644 --- a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3FFF) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0xF0) -#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0xF) -#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (1) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3FFF) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x1) -#define BSP_FEATURE_GPT_OPS_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ACMP_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x3F) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_AMI_PRESENT (1) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_PRESENT (0) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CTSU_PRESENT (1) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DRW_PRESENT (1) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GLCDC_PRESENT (1) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FFF) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x7) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IRDA_PRESENT (1) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_JPEG_PRESENT (1) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_KINT_PRESENT (1) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MMF_PRESENT (1) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PDC_PRESENT (1) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PMISC_PRESENT (1) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0xFFF) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (1) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_QSPI_PRESENT (1) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE7_PRESENT (1) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x3FF) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SPMON_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRC_PRESENT (1) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (1) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_PRESENT (0) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_PRESENT (0) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_HS_PRESENT (1) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h index dafab34f5..694433c5c 100644 --- a/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h @@ -89,7 +89,7 @@ typedef enum e_elc_event_ra6m4 ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h index 5aac196fc..ca7f12016 100644 --- a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h @@ -82,13 +82,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,7 +107,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA6M4 there are specific registers for configuring the USB clock. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) @@ -192,6 +192,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -242,11 +243,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M4 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Deprecated (Removing in FSP v6.0) @@ -283,18 +287,17 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FU) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFU) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) @@ -302,6 +305,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -342,7 +346,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register @@ -397,6 +402,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -442,4 +448,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature_gen.h index 18e41b9e5..e2383a632 100644 --- a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3FF) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3FF) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_OPS_SUPPORTED (0) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3F) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CACHE_PRESENT (1) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CTSU_PRESENT (1) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FF) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_OSPI_PRESENT (1) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x1FF) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_QSPI_PRESENT (1) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE9_PRESENT (1) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x3FF) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h index a16812667..c64bb962f 100644 --- a/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h @@ -89,7 +89,7 @@ typedef enum e_elc_event_ra6m5 ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt diff --git a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h index 00ca5ba1e..3ab0ff147 100644 --- a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h @@ -82,13 +82,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,7 +107,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (1U) // Feature available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (1U) // Feature available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA6M5 there are specific registers for configuring the USB clock. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) @@ -192,6 +192,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -242,11 +243,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M5 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Deprecated (Removing in FSP v6.0) @@ -283,18 +287,17 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FU) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFU) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) @@ -302,6 +305,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FF0DFFFFULL) // Note there is another WUPEN1 register #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -342,7 +346,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register @@ -397,6 +402,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -442,4 +448,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (1U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature_gen.h index 18e41b9e5..bf318e4c8 100644 --- a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3FF) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3FF) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_OPS_SUPPORTED (0) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3F) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CACHE_PRESENT (1) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_CANFD_PRESENT (1) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CEC_PRESENT (1) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CTSU_PRESENT (1) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (1) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ECCMB_PRESENT (1) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FF) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x7) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_OSPI_PRESENT (1) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0xFFF) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_QSPI_PRESENT (1) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE9_PRESENT (1) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x3FF) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_HS_PRESENT (1) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra6t1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6t1/bsp_elc.h index 8b2a49046..9b9b54fee 100644 --- a/ra/fsp/src/bsp/mcu/ra6t1/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra6t1/bsp_elc.h @@ -74,7 +74,7 @@ typedef enum e_elc_event_ra6t1 ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x046), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT underflow ELC_EVENT_ADC0_SCAN_END = (0x04B), // End of A/D scanning operation ELC_EVENT_ADC0_SCAN_END_B = (0x04C), // A/D scan end interrupt for group B ELC_EVENT_ADC0_WINDOW_A = (0x04D), // Window A Compare match interrupt diff --git a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h index f0f8be1ed..7744d738a 100644 --- a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h @@ -82,13 +82,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,7 +107,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. @@ -194,6 +194,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1U) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -244,11 +245,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M1 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0003FFFFU) // Deprecated (Removing in FSP v6.0) @@ -285,25 +289,25 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x1FFF) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (120000000U) #define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000U) -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0x0FU) #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x1FFF) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x3FFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0xF04F3FFFU) #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -344,7 +348,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x70423FFFU) @@ -399,6 +404,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -444,4 +450,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature_gen.h index bb56c5002..caabdaeb4 100644 --- a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x1FFF) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0xF0) -#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0xF) -#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (1) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x1FFF) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x1) -#define BSP_FEATURE_GPT_OPS_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ACMP_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x3F) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_PRESENT (0) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x1FFF) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0x3FFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IRDA_PRESENT (1) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_KINT_PRESENT (1) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MMF_PRESENT (1) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PMISC_PRESENT (1) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_PRESENT (0) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE7_PRESENT (1) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SCE_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x31F) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SPMON_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRC_PRESENT (1) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (1) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_PRESENT (0) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_PRESENT (0) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_FS_PRESENT (0) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra6t2/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6t2/bsp_elc.h index a0d14cc7b..c9c81ce04 100644 --- a/ra/fsp/src/bsp/mcu/ra6t2/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra6t2/bsp_elc.h @@ -86,7 +86,7 @@ typedef enum e_elc_event_ra6t2 ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow ELC_EVENT_CAN_RXF = (0x059), // Global recieve FIFO interrupt ELC_EVENT_CAN_GLERR = (0x05A), // Global error ELC_EVENT_CAN_DMAREQ0 = (0x05B), // RX fifo DMA request 0 diff --git a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h index 491d3a0a4..d69be6898 100644 --- a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h @@ -82,17 +82,17 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1U) -#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) -#define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (1U) // Mutually exclusive with USB60 Clock +#define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (1U) -#define BSP_FEATURE_BSP_HAS_ITCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_ITCM (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_LCD_CLOCK (0) #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) #define BSP_FEATURE_BSP_HAS_OFS2 (0) @@ -107,7 +107,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) @@ -193,6 +193,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -243,11 +244,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (4U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (2U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M5 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x31FBF0FFU) // Deprecated (Removing in FSP v6.0) @@ -284,18 +288,18 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3FFU) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (1U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x00FU) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (115000000U) +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) \ + ((BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN >= gpt_frequency) ? 0x1 : 0) // Set to 1 if configured gpt frequency is _below_ FRANGE threshold #define BSP_FEATURE_GPT_ODC_FREQ_MAX (200000000U) #define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000U) -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0x0FU) #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFU) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0) // Feature not available on this MCU #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) @@ -303,6 +307,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (0) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0xF00FFFFFU) // Note there is another WUPEN1 register #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -343,7 +348,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000AFU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7002FFFFU) @@ -399,6 +405,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (2U) #define BSP_FEATURE_SCI_LIN_CHANNELS (BSP_FEATURE_SCI_CHANNELS) +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -444,4 +451,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature_gen.h index 0d91714b7..571a8cf84 100644 --- a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0xF) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x3FF) -#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0x1) -#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0x3FF) -#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0x1) -#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0) -#define BSP_FEATURE_GPT_OPS_SUPPORTED (0) +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (1) +#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0xF) +#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (1) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3FF) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) +#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_PRESENT (0) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_B_PRESENT (1) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGTW_PRESENT (1) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CACHE_PRESENT (1) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CANFD_PRESENT (1) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_B_PRESENT (1) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ECCMB_PRESENT (1) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_PRESENT (0) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_B_PRESENT (1) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FF) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (1) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_B_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIRFA_PRESENT (1) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_KINT_PRESENT (1) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PDG_PRESENT (1) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_PRESENT (0) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_B_PRESENT (1) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x7C05) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_PRESENT (0) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x21F) +#define BSP_PERIPHERAL_SCI_B_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_B_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TFU_PRESENT (1) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_PRESENT (0) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_FS_PRESENT (0) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra6t3/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6t3/bsp_elc.h index 89ee59d45..6ef6c0d78 100644 --- a/ra/fsp/src/bsp/mcu/ra6t3/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra6t3/bsp_elc.h @@ -75,7 +75,7 @@ typedef enum e_elc_event_ra6t3 ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT0 underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow ELC_EVENT_CAN_RXF = (0x059), // Global recieve FIFO interrupt ELC_EVENT_CAN_GLERR = (0x05A), // Global error ELC_EVENT_CAN_DMAREQ0 = (0x05B), // RX fifo DMA request 0 diff --git a/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h index 2c7b23639..8572cdff3 100644 --- a/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h @@ -82,13 +82,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,7 +107,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA6T3 there are specific registers for configuring the USB clock. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) @@ -192,6 +192,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) @@ -242,11 +243,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_HAS_DELSR (0U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (1U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA6T3 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0083F3FFU) // Deprecated (Removing in FSP v6.0) @@ -283,18 +287,17 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x00U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FU) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) #define BSP_FEATURE_I3C_NUM_CHANNELS (1U) #define BSP_FEATURE_I3C_MSTP_OFFSET (4U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) @@ -302,6 +305,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x7FFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x800780D7FFFULL) // Note there is another WUPEN1 register #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -342,7 +346,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x70407FFFU) @@ -397,6 +402,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -442,4 +448,18 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (1U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module +#define BSP_FEATURE_USB_HAS_NOT_HOST (1U) + #endif diff --git a/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature_gen.h index 9e68fc984..fa5c46235 100644 --- a/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature_gen.h @@ -30,11 +30,374 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3F) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x3F) -#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3F) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x1) -#define BSP_FEATURE_GPT_OPS_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x7) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (0) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CACHE_PRESENT (1) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CANFD_PRESENT (1) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (0) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (0) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (0) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (0) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (0) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3F) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_I3C_PRESENT (1) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (0) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0x7FFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC_B_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (0) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (0) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x13F) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (0) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_PRESENT (0) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x201) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (0) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (0) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (0) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (0) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (0) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (0) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (0) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (0) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h index fc36f18d3..e2cdb5775 100644 --- a/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h @@ -81,13 +81,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1U) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (1U) -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0U) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (1) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -106,7 +106,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (1U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (1U) // Feature available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (1U) // Feature available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) @@ -194,6 +194,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (3U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (8) @@ -245,11 +246,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_HAS_DELSR (1U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (2U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA8D1 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x4003FFFFU) // Deprecated (Removing in FSP v6.0) @@ -286,18 +290,17 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x00FFU) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) -#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (115000000U) -#define BSP_FEATURE_GPT_ODC_FREQ_MAX (200000000U) -#define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000U) -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFFU) #define BSP_FEATURE_I3C_NUM_CHANNELS (1U) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) #define BSP_FEATURE_I3C_MSTP_OFFSET (4U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (1U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) @@ -305,6 +308,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x00007F08FF1DFFFFU) // Note there is another WUPEN1 register #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -345,7 +349,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SNZREQCR_MASK (0U) // Feature not available on this MCU @@ -400,6 +405,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (2U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0x3U) +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -434,7 +440,7 @@ #define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU #define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) #define BSP_FEATURE_TZ_NS_OFFSET (1U << 28U) @@ -445,4 +451,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (2) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (1U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature_gen.h index 383d85302..40061b621 100644 --- a/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature_gen.h @@ -28,13 +28,376 @@ **********************************************************************************************************************/ // *UNCRUSTIFY-OFF* -#define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0x3FFF) -#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0xFF) +#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (1) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3FFF) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3FFF) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x1) -#define BSP_FEATURE_GPT_OPS_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (1) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (1) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_CANFD_PRESENT (1) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CEU_PRESENT (1) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (1) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (1) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (1) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (1) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (1) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (1) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (1) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (1) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (1) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (1) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DRW_PRESENT (1) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (1) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DSILINK_PRESENT (1) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (1) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (1) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ECCMB_PRESENT (1) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (1) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GLCDC_PRESENT (1) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FFF) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (1) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_I3C_PRESENT (1) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (1) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (1) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC_B_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (1) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (1) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (1) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (1) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (1) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_OCD_PRESENT (1) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (1) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (1) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (1) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (1) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x1FFFF) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0x1FFFF) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (1) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (1) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0x800) +#define BSP_PERIPHERAL_SCE_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x21F) +#define BSP_PERIPHERAL_SCI_B_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0x21F) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (1) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (1) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_B_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (1) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (1) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (1) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (1) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (1) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (1) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ULPT_PRESENT (1) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (1) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_HS_PRESENT (1) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (1) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h index a898aa141..97e2b0877 100644 --- a/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h @@ -81,13 +81,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1U) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (1U) -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0U) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -106,7 +106,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (1U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (1U) // Feature available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (1U) // Feature available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) @@ -194,6 +194,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (3U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (8) @@ -245,11 +246,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_HAS_DELSR (1U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) // Feature not available on this MCU #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (2U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA8M1 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x4003FFFFU) // Deprecated (Removing in FSP v6.0) @@ -286,18 +290,17 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x00FFU) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) -#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (115000000U) -#define BSP_FEATURE_GPT_ODC_FREQ_MAX (200000000U) -#define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000U) -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFFU) #define BSP_FEATURE_I3C_NUM_CHANNELS (1U) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) #define BSP_FEATURE_I3C_MSTP_OFFSET (4U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (1U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) @@ -305,6 +308,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x00007F08FF1DFFFFU) // Note there is another WUPEN1 register #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -345,7 +349,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SNZREQCR_MASK (0U) // Feature not available on this MCU @@ -400,6 +405,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (2U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0x3U) +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -434,7 +440,7 @@ #define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU #define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) #define BSP_FEATURE_TZ_NS_OFFSET (1U << 28U) @@ -445,4 +451,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (2) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (1U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature_gen.h index 7aaf8a999..fe7b16ceb 100644 --- a/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature_gen.h @@ -29,12 +29,375 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0xFF) -#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (1) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3FFF) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3FFF) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x1) -#define BSP_FEATURE_GPT_OPS_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (1) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (1) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_CANFD_PRESENT (1) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CEU_PRESENT (1) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (1) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (1) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (1) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (1) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (1) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (1) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (1) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (1) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (1) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (1) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DRW_PRESENT (1) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (1) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (1) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ECCMB_PRESENT (1) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (1) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FFF) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (1) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_I3C_PRESENT (1) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (1) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (1) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC_B_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (1) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (1) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (1) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (1) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_OCD_PRESENT (1) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (1) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (1) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (1) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (1) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x1FFFF) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0x1FFFF) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (1) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (1) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0x800) +#define BSP_PERIPHERAL_SCE_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x21F) +#define BSP_PERIPHERAL_SCI_B_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0x21F) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (1) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (1) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_B_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (1) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (1) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (1) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (1) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (1) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (1) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ULPT_PRESENT (1) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (1) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_HS_PRESENT (1) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (1) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature.h index 6d89bbd45..263847554 100644 --- a/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature.h @@ -81,13 +81,13 @@ #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1U) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (1U) -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0U) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -106,7 +106,7 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (1U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (1U) // Feature available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) @@ -194,6 +194,7 @@ #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP #define BSP_FEATURE_CGC_REGISTER_SET_B (0) #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) #define BSP_FEATURE_CGC_SODRV_MASK (3U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (8) @@ -245,11 +246,14 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_HAS_DELSR (1U) +#define BSP_FEATURE_DMAC_HAS_DMCTL (0U) #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) #define BSP_FEATURE_DOC_VERSION (2U) +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) + #define BSP_FEATURE_DWT_CYCCNT (1U) // RA8T1 has Data Watchpoint Cycle Count Register #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x4003FFFFU) // Deprecated (Removing in FSP v6.0) @@ -285,18 +289,17 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x00FFU) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) -#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (115000000U) -#define BSP_FEATURE_GPT_ODC_FREQ_MAX (200000000U) -#define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000U) -#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFFU) #define BSP_FEATURE_I3C_NUM_CHANNELS (1U) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) #define BSP_FEATURE_I3C_MSTP_OFFSET (4U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (1U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) @@ -304,6 +307,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER #define BSP_FEATURE_ICU_WUPEN_MASK (0x00007F08FF1DFFFFU) // Note there is another WUPEN1 register #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) @@ -344,7 +348,8 @@ #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SNZREQCR_MASK (0U) // Feature not available on this MCU @@ -398,6 +403,7 @@ #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (2U) #define BSP_FEATURE_SCI_LIN_CHANNELS (0x3U) +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -432,7 +438,7 @@ #define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU #define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) #define BSP_FEATURE_TZ_NS_OFFSET (1U << 28U) @@ -443,4 +449,17 @@ #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (2) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBHS (0U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module + #endif diff --git a/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature_gen.h index 7aaf8a999..0c8ea78f5 100644 --- a/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature_gen.h @@ -29,12 +29,375 @@ // *UNCRUSTIFY-OFF* #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0xFF) -#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (1) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3FFF) +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1) #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0) #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0) +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3FFF) +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1) #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x1) -#define BSP_FEATURE_GPT_OPS_SUPPORTED (0x1) +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1) + +#define BSP_PERIPHERAL_ACMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ACMPHS_NS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_AES_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AES_PRESENT (0) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AMI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_BUS_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_BUS_NS_PRESENT (1) +#define BSP_PERIPHERAL_CAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CAC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CAC_NS_PRESENT (1) +#define BSP_PERIPHERAL_CACHE_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_CANFD_PRESENT (1) +#define BSP_PERIPHERAL_CEC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CEU_PRESENT (1) +#define BSP_PERIPHERAL_CEU_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CEU_NS_PRESENT (1) +#define BSP_PERIPHERAL_CGC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPSCU_NS_PRESENT (1) +#define BSP_PERIPHERAL_CPU_CTRL_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CPU_CTRL_NS_PRESENT (1) +#define BSP_PERIPHERAL_CRC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CRC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_CRC_NS_PRESENT (1) +#define BSP_PERIPHERAL_CTSU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DEBUG_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DEBUG_NS_PRESENT (1) +#define BSP_PERIPHERAL_DMA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_NS_CHANNEL_MASK (0xFF) +#define BSP_PERIPHERAL_DMA_DMAC_NS_PRESENT (1) +#define BSP_PERIPHERAL_DMA_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DMA_NS_PRESENT (1) +#define BSP_PERIPHERAL_DOC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DOC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DOC_NS_PRESENT (1) +#define BSP_PERIPHERAL_DPHYCNT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DPHYCNT_PRESENT (1) +#define BSP_PERIPHERAL_DPHYCNT_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DPHYCNT_NS_PRESENT (1) +#define BSP_PERIPHERAL_DRW_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DRW_PRESENT (1) +#define BSP_PERIPHERAL_DRW_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DRW_NS_PRESENT (1) +#define BSP_PERIPHERAL_DSILINK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_PRESENT (0) +#define BSP_PERIPHERAL_DSILINK_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_DSILINK_NS_PRESENT (0) +#define BSP_PERIPHERAL_DTC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_DTC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_DTC_NS_PRESENT (1) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ECCMB_PRESENT (1) +#define BSP_PERIPHERAL_ECCMB_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ECCMB_NS_PRESENT (1) +#define BSP_PERIPHERAL_ELC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ELC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ELC_NS_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_NS_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_NS_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) +#define BSP_PERIPHERAL_FACI_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FACI_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FACI_NS_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FCACHE_NS_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLAD_NS_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GLCDC_NS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FFF) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_GTCLK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_OPS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_OPS_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_OPS_NS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xF) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_GPT_POEG_NS_PRESENT (1) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_I3C_PRESENT (1) +#define BSP_PERIPHERAL_I3C_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_I3C_NS_PRESENT (1) +#define BSP_PERIPHERAL_ICU_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_NS_CHANNEL_MASK (0xFFFF) +#define BSP_PERIPHERAL_ICU_NS_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC0WU_NS_PRESENT (1) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC_B_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IIC_B_NS_PRESENT (1) +#define BSP_PERIPHERAL_IIC_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_IIC_NS_PRESENT (1) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_IWDT_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IWDT_NS_PRESENT (1) +#define BSP_PERIPHERAL_JPEG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_MACL_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MMF_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MPU_NS_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_MSTP_NS_PRESENT (1) +#define BSP_PERIPHERAL_OCD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_OCD_PRESENT (1) +#define BSP_PERIPHERAL_OCD_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_OCD_NS_PRESENT (1) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (1) +#define BSP_PERIPHERAL_OSPI_B_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_OSPI_B_NS_PRESENT (1) +#define BSP_PERIPHERAL_PCLBUZ_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PDG_PRESENT (0) +#define BSP_PERIPHERAL_PFS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PFS_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PFS_NS_PRESENT (1) +#define BSP_PERIPHERAL_PMISC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x1FFFF) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_NS_CHANNEL_MASK (0x1FFFF) +#define BSP_PERIPHERAL_PORT_NS_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PSCU_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_PSCU_NS_PRESENT (1) +#define BSP_PERIPHERAL_PTPEDMAC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RTC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_PRESENT (0) +#define BSP_PERIPHERAL_RTC_C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_RTC_NS_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_RTC_NS_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SCE5_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE5_PRESENT (0) +#define BSP_PERIPHERAL_SCE7_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE7_PRESENT (0) +#define BSP_PERIPHERAL_SCE9_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCE9_PRESENT (0) +#define BSP_PERIPHERAL_SCE_CHANNEL_MASK (0x800) +#define BSP_PERIPHERAL_SCE_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SCI_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x21F) +#define BSP_PERIPHERAL_SCI_B_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_NS_CHANNEL_MASK (0x21F) +#define BSP_PERIPHERAL_SCI_B_NS_PRESENT (1) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SDHI_NS_PRESENT (1) +#define BSP_PERIPHERAL_SLCDC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_B_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SPI_B_NS_PRESENT (1) +#define BSP_PERIPHERAL_SPMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SRAM_NS_PRESENT (1) +#define BSP_PERIPHERAL_SRC_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_SSIE_NS_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_SYSTEM_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_SYSTEM_NS_PRESENT (1) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TFU_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TRNG_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSD_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSD_NS_PRESENT (1) +#define BSP_PERIPHERAL_TSN_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TSN_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TSN_NS_PRESENT (1) +#define BSP_PERIPHERAL_TZF_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_TZF_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_TZF_NS_PRESENT (1) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ULPT_PRESENT (1) +#define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0x3) +#define BSP_PERIPHERAL_ULPT_NS_PRESENT (1) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_FS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_USB_HS_PRESENT (1) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_NS_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_WDT_NS_PRESENT (1) // *UNCRUSTIFY-ON* #endif diff --git a/ra/fsp/src/r_adc/r_adc.c b/ra/fsp/src/r_adc/r_adc.c index 238261bbd..196665e31 100644 --- a/ra/fsp/src/r_adc/r_adc.c +++ b/ra/fsp/src/r_adc/r_adc.c @@ -111,14 +111,14 @@ static fsp_err_t r_adc_scan_cfg_check(adc_instance_ctrl_t * const p_instance static void r_adc_scan_cfg(adc_instance_ctrl_t * const p_instance_ctrl, adc_channel_cfg_t const * const p_channel_cfg); -static void r_adc_sensor_sample_state_calculation(uint32_t * const p_sample_states); -void adc_scan_end_b_isr(void); -void adc_scan_end_isr(void); -void adc_window_compare_isr(void); -static void r_adc_irq_enable(IRQn_Type irq, uint8_t ipl, void * p_context); -static void r_adc_irq_disable(IRQn_Type irq); -static int32_t r_adc_lowest_channel_get(uint32_t adc_mask); -static void r_adc_scan_end_common_isr(adc_event_t event); +static void r_adc_sensor_sample_state_calculation(uint32_t * const p_sample_states); +void adc_scan_end_b_isr(void); +void adc_scan_end_isr(void); +void adc_window_compare_isr(void); +static void r_adc_irq_enable(IRQn_Type irq, uint8_t ipl, void * p_context); +static void r_adc_irq_disable(IRQn_Type irq); +static uint32_t r_adc_lowest_channel_get(uint32_t adc_mask); +static void r_adc_scan_end_common_isr(adc_event_t event); #if ADC_CFG_PARAM_CHECKING_ENABLE @@ -593,11 +593,11 @@ fsp_err_t R_ADC_InfoGet (adc_ctrl_t * p_ctrl, adc_info_t * p_adc_info) uint32_t adc_mask_in_order = adc_mask & ~(uint32_t) ADC_MASK_SENSORS; adc_mask_in_order <<= 3U; adc_mask_in_order |= adc_mask >> ADC_MASK_FIRST_SENSOR_BIT; - int32_t lowest_channel = r_adc_lowest_channel_get(adc_mask_in_order); + uint32_t lowest_channel = r_adc_lowest_channel_get(adc_mask_in_order); p_adc_info->p_address = &p_instance_ctrl->p_reg->ADDR[lowest_channel - 3]; /* Determine the highest channel that is configured. */ - int32_t highest_channel = 31 - __CLZ(adc_mask_in_order); + uint32_t highest_channel = 31 - __CLZ(adc_mask_in_order); /* Determine the size of data that must be read to read all the channels between and including the * highest and lowest channels.*/ @@ -1557,7 +1557,7 @@ static void r_adc_irq_disable (IRQn_Type irq) * * @retval adc_mask_count index value of lowest channel **********************************************************************************************************************/ -static int32_t r_adc_lowest_channel_get (uint32_t adc_mask) +static uint32_t r_adc_lowest_channel_get (uint32_t adc_mask) { /* Initialize the mask result */ uint32_t adc_mask_result = 0U; @@ -1569,7 +1569,7 @@ static int32_t r_adc_lowest_channel_get (uint32_t adc_mask) adc_mask_result = (uint32_t) (adc_mask & (1U << adc_mask_count)); } - return adc_mask_count; + return (uint32_t) adc_mask_count; } /*******************************************************************************************************************//** diff --git a/ra/fsp/src/r_adc_b/r_adc_b.c b/ra/fsp/src/r_adc_b/r_adc_b.c index 2ae25d8fa..de34db444 100644 --- a/ra/fsp/src/r_adc_b/r_adc_b.c +++ b/ra/fsp/src/r_adc_b/r_adc_b.c @@ -769,7 +769,7 @@ fsp_err_t R_ADC_B_Read32 (adc_ctrl_t * p_ctrl, adc_channel_t const channel_id, u **********************************************************************************************************************/ fsp_err_t R_ADC_B_FifoRead (adc_ctrl_t * p_ctrl, adc_group_mask_t const group_mask, adc_b_fifo_read_t * const p_data) { - uint8_t group_id = __CLZ(__RBIT(group_mask)); + uint8_t group_id = (uint8_t) __CLZ(__RBIT(group_mask)); #if ADC_B_CFG_PARAM_CHECKING_ENABLE adc_b_instance_ctrl_t * p_instance_ctrl = (adc_b_instance_ctrl_t *) p_ctrl; FSP_ASSERT(NULL != p_instance_ctrl); @@ -787,11 +787,12 @@ fsp_err_t R_ADC_B_FifoRead (adc_ctrl_t * p_ctrl, adc_group_mask_t const group_ma uint32_t remaining_count = *p_fifo_status & (R_ADC_B0_ADFIFOSR0_FIFOST0_Msk | R_ADC_B0_ADFIFOSR0_FIFOST1_Msk); remaining_count >>= ((group_id % 2) ? R_ADC_B0_ADFIFOSR0_FIFOST1_Pos : R_ADC_B0_ADFIFOSR0_FIFOST0_Pos); - uint8_t count = (uint8_t) (ADC_B_FIFO_STAGE_COUNT - remaining_count); + uint8_t count = (ADC_B_FIFO_STAGE_COUNT - (uint8_t) remaining_count); p_data->count = count; + volatile adc_b_fifo_data_t * p_data_dest = &p_data->fifo_data[0]; for (uint8_t i = 0; i < count; i++) { - p_data->fifo_data[i] = *(adc_b_fifo_data_t *) p_fifo_data; + p_data_dest[i] = *(adc_b_fifo_data_t *) p_fifo_data; } fsp_err_t err = (count ? FSP_SUCCESS : FSP_ERR_UNDERFLOW); @@ -1623,7 +1624,7 @@ void adc_b_adi5678_isr (void) /* Save context if RTOS is used */ FSP_CONTEXT_SAVE - uint8_t group_id = __CLZ(__RBIT(ADC_B_GROUP_MASK_5678 & R_ADC_B->ADSCANENDSR)); + uint8_t group_id = (uint8_t) __CLZ(__RBIT(ADC_B_GROUP_MASK_5678 & R_ADC_B->ADSCANENDSR)); adc_group_mask_t group_mask = (adc_group_mask_t) ((group_id > 31) ? ADC_GROUP_MASK_NONE : (1U << group_id)); diff --git a/ra/fsp/src/r_adc_d/r_adc_d.c b/ra/fsp/src/r_adc_d/r_adc_d.c index 875b49121..2192486ec 100644 --- a/ra/fsp/src/r_adc_d/r_adc_d.c +++ b/ra/fsp/src/r_adc_d/r_adc_d.c @@ -604,6 +604,90 @@ fsp_err_t R_ADC_D_OffsetSet (adc_ctrl_t * const p_ctrl, adc_channel_t const reg_ return FSP_ERR_UNSUPPORTED; } +/*******************************************************************************************************************//** + * Prepare ADC_D to enter snooze mode via a hardware trigger. + * This function must be called immediately before entering software standby mode in order to allow the configured + * hardware trigger to transition the MCU from software standby mode to snooze mode and perform an ADC conversion. + * + * Supported modes for requesting snooze mode via hardware trigger: + * - channel_mode = ADC_D_CHANNEL_MODE_SELECT, conversion_operation = ADC_D_CONVERSION_MODE_ONESHOT + * - channel_mode = ADC_D_CHANNEL_MODE_SCAN, conversion_operation = ADC_D_CONVERSION_MODE_ONESHOT + * + * @param[in] p_ctrl Pointer to the ADC control block + * + * @retval FSP_SUCCESS ADC is configured to request Snooze mode. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN ADC_D is not open. + * @retval FSP_ERR_INVALID_MODE ADC is in an invalid mode for requesting Snooze mode. + **********************************************************************************************************************/ +fsp_err_t R_ADC_D_SnoozeModePrepare (adc_ctrl_t * const p_ctrl) +{ +#if ADC_D_CFG_SNOOZE_SUPPORT_ENABLE + #if ADC_D_CFG_PARAM_CHECKING_ENABLE + adc_d_instance_ctrl_t * p_instance_ctrl = (adc_d_instance_ctrl_t *) p_ctrl; + + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(ADC_D_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + + /* Verify that the ADC instance is in the correct mode for requesting snooze mode via hardware trigger. */ + adc_d_extended_cfg_t const * p_extend = (adc_d_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend; + FSP_ERROR_RETURN(ADC_D_TRIGGER_SOURCE_SOFTWARE != p_extend->trigger_source, FSP_ERR_INVALID_MODE); + FSP_ERROR_RETURN(ADC_D_CONVERSION_MODE_ONESHOT == p_extend->conversion_operation, FSP_ERR_INVALID_MODE); + FSP_ERROR_RETURN(ADC_D_TRIGGER_MODE_WAIT == p_extend->operation_trigger, FSP_ERR_INVALID_MODE); + + /* The peripheral clock source must be set to HOCO or MOCO. */ + FSP_ERROR_RETURN(0 == R_SYSTEM->ICLKSCR_b.CKST, FSP_ERR_INVALID_MODE); + FSP_ERROR_RETURN(0 == R_SYSTEM->FMAINSCR_b.CKST, FSP_ERR_INVALID_MODE); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + /* Set AWC prior to entering software standby mode. + * See section 25.7.2 A/D "Conversion by Inputting a Hardware Trigger" in the RA0E1 user manual R01UH1040EJ0100. */ + R_ADC_D->ADM2_b.AWC = 1; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * After exiting snooze mode, if the ADC_D module was in snooze mode, then this function must be called in order to + * restore ADC operation to normal mode. + * + * @param[in] p_ctrl Pointer to the ADC control block + * + * @retval FSP_SUCCESS ADC is configured to request Snooze mode. + * @retval FSP_ERR_INVALID_MODE ADC is in an invalid mode for requesting Snooze mode. + **********************************************************************************************************************/ +fsp_err_t R_ADC_D_SnoozeModeExit (adc_ctrl_t * const p_ctrl) +{ +#if ADC_D_CFG_SNOOZE_SUPPORT_ENABLE + #if ADC_D_CFG_PARAM_CHECKING_ENABLE + adc_d_instance_ctrl_t * p_instance_ctrl = (adc_d_instance_ctrl_t *) p_ctrl; + + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(ADC_D_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(1 == R_ADC_D->ADM2_b.AWC, FSP_ERR_INVALID_MODE); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + /* Clear AWC after exiting software standby mode. + * See section 25.7.2 A/D "Conversion by Inputting a Hardware Trigger" in the RA0E1 user manual R01UH1040EJ0100. */ + R_ADC_D->ADM2_b.AWC = 0; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + + return FSP_ERR_UNSUPPORTED; +#endif +} + /*******************************************************************************************************************//** * @} (end addtogroup ADC_D) **********************************************************************************************************************/ @@ -794,7 +878,7 @@ static void r_adc_d_open_sub (adc_d_instance_ctrl_t * const p_ctrl) R_ADC_D->ADM2 = adcadm2; /* Setting reference voltage source - * See Table 25.15 "Register settings for ADREFP[1:0] rewrite" in RA0E1 User's Manual (R01UH1040EJ0100) */ + * See Table 25.11 "Register settings for ADREFP[1:0] rewrite" in RA0E1 User's Manual (R01UH1040EJ0100) */ if (ADC_D_POSITIVE_VREF_IVREF == p_extend->positive_vref) { /* Discharge */ diff --git a/ra/fsp/src/r_canfd/r_canfd.c b/ra/fsp/src/r_canfd/r_canfd.c index 91dacd755..02b94a65b 100644 --- a/ra/fsp/src/r_canfd/r_canfd.c +++ b/ra/fsp/src/r_canfd/r_canfd.c @@ -883,8 +883,11 @@ fsp_err_t R_CANFD_InfoGet (can_ctrl_t * const p_api_ctrl, can_info_t * const p_i p_info->rx_fifo_status = (~p_ctrl->p_reg->CFDFESTS) & (R_CANFD_CFDFESTS_RFXEMP_Msk | R_CANFD_CFDFESTS_CFXEMP_Msk); - /* Clear error flags */ - p_ctrl->p_reg->CFDC[interlaced_channel].ERFL &= ~((uint32_t) UINT16_MAX); + /* Clear error flags if the error IRQ is not enabled. */ + if (p_ctrl->p_cfg->error_irq < 0) + { + p_ctrl->p_reg->CFDC[interlaced_channel].ERFL = 0; + } return FSP_SUCCESS; } diff --git a/ra/fsp/src/r_cgc/r_cgc.c b/ra/fsp/src/r_cgc/r_cgc.c index 6562fd9a2..bb389861c 100644 --- a/ra/fsp/src/r_cgc/r_cgc.c +++ b/ra/fsp/src/r_cgc/r_cgc.c @@ -21,7 +21,7 @@ #define CGC_PRV_OSTDCR_OSC_STOP_ENABLE (0x81U) -#if 3U == BSP_FEATURE_CGC_PLLCCR_TYPE +#if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) /* PLLMUL starts at bit 8, but PLLMULNF at bits 7:6 which can be treated as part of PLLMUL when setting it. */ #define CGC_PRV_PLLCCR_PLLMUL_BIT (6U) @@ -45,7 +45,7 @@ #define CGC_PRV_PLLCCR_PLLMUL_MASK (0x3FU) #endif -#if 3U != BSP_FEATURE_CGC_PLLCCR_TYPE +#if (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (6U != BSP_FEATURE_CGC_PLLCCR_TYPE) /* PLLMUL in PLLCCR starts at bit 8. */ #define CGC_PRV_PLLCCR_PLLMUL_BIT (8U) @@ -210,7 +210,7 @@ static fsp_err_t r_cgc_pll_parameter_check(cgc_pll_cfg_t const * const p_pll_cfg #if BSP_PRV_PLL_SUPPORTED || BSP_PRV_PLL2_SUPPORTED static uint32_t r_cgc_pllccr_calculate(cgc_pll_cfg_t const * const p_pll_cfg); - #if 3U == BSP_FEATURE_CGC_PLLCCR_TYPE + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) static uint16_t r_cgc_pllccr2_calculate(cgc_pll_cfg_t const * const p_pll_cfg); #endif @@ -791,7 +791,7 @@ fsp_err_t R_CGC_ClockStart (cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, #if BSP_PRV_PLL_SUPPORTED uint32_t pll_hz[CGC_PRV_MAX_PLL_OUTPUTS]; - uint32_t pllccr; + uint32_t pllccr = 0; if ((CGC_CLOCK_PLL == clock_source) #if BSP_PRV_PLL2_SUPPORTED || (CGC_CLOCK_PLL2 == clock_source) @@ -1349,7 +1349,8 @@ fsp_err_t R_CGC_OscStopStatusClear (cgc_ctrl_t * const p_ctrl) cgc_clock_t current_clock = (cgc_clock_t) R_SYSTEM->SCKSCR; #if BSP_PRV_PLL_SUPPORTED - #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE || 3U == BSP_FEATURE_CGC_PLLCCR_TYPE || 5U == BSP_FEATURE_CGC_PLLCCR_TYPE + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || \ + (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) /* Oscillation stop status cannot be cleared if PLL is the current source clock and main oscillator is the * source of the PLL. */ @@ -1972,7 +1973,7 @@ static fsp_err_t r_cgc_pll_parameter_check (cgc_pll_cfg_t const * const p_pll_cf } } #endif - #elif 3U == BSP_FEATURE_CGC_PLLCCR_TYPE + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) /* Ensure PLL configuration is supported on this MCU, * see Section 8.2.6 "PLL Clock Control Register (PLLCCR)" in the RA8M1 manual R01UH0994EJ0100 */ @@ -1985,9 +1986,17 @@ static fsp_err_t r_cgc_pll_parameter_check (cgc_pll_cfg_t const * const p_pll_cf FSP_ASSERT(CGC_PLL_OUT_DIV_9 >= p_pll_cfg->out_div_q); FSP_ASSERT(CGC_PLL_OUT_DIV_9 >= p_pll_cfg->out_div_r); + #if (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + + /* PLLCCR multiplier must be between 40.00 and 300.00. */ + FSP_ASSERT(p_pll_cfg->multiplier >= CGC_PLL_MUL_40_0); + FSP_ASSERT(p_pll_cfg->multiplier <= CGC_PLL_MUL_300_0); + #else + /* PLLCCR multiplier must be between 53.00 and 180.00. */ FSP_ASSERT(p_pll_cfg->multiplier >= CGC_PLL_MUL_53_0); FSP_ASSERT(p_pll_cfg->multiplier <= CGC_PLL_MUL_180_0); + #endif #elif 4U == BSP_FEATURE_CGC_PLLCCR_TYPE /* Ensure PLL configuration is supported on this MCU (MREF_INTERNAL_006). */ @@ -2087,7 +2096,7 @@ static fsp_err_t r_cgc_pll_hz_calculate (cgc_pll_cfg_t const * const p_pll_cfg, /* Store the calculated frequency in the provided pointer if there are no violations. */ p_pll_hz[0] = pll_hz; - #elif 3U == BSP_FEATURE_CGC_PLLCCR_TYPE + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) FSP_PARAMETER_NOT_USED(pll); if (CGC_CLOCK_HOCO == p_pll_cfg->source_clock) { @@ -2206,7 +2215,8 @@ static fsp_err_t r_cgc_pll_hz_calculate (cgc_pll_cfg_t const * const p_pll_cfg, static uint32_t r_cgc_pllccr_calculate (cgc_pll_cfg_t const * const p_pll_cfg) { /* Set the PLL control register. */ - #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE || 3U == BSP_FEATURE_CGC_PLLCCR_TYPE || 5U == BSP_FEATURE_CGC_PLLCCR_TYPE + #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE || 3U == BSP_FEATURE_CGC_PLLCCR_TYPE || 5U == BSP_FEATURE_CGC_PLLCCR_TYPE || \ + 6U == BSP_FEATURE_CGC_PLLCCR_TYPE uint16_t plsrcsel = 0U; if (CGC_CLOCK_HOCO == p_pll_cfg->source_clock) { @@ -2247,7 +2257,7 @@ static uint32_t r_cgc_pllccr_calculate (cgc_pll_cfg_t const * const p_pll_cfg) #endif } - #if 3U == BSP_FEATURE_CGC_PLLCCR_TYPE + #if 3U == BSP_FEATURE_CGC_PLLCCR_TYPE || 6U == BSP_FEATURE_CGC_PLLCCR_TYPE /*******************************************************************************************************************//** * Calculate PLL registers for PLL clock start @@ -2279,7 +2289,8 @@ static inline cgc_clock_t r_cgc_pll_clocksource_get (void) { /* PLL source selection only available on PLLCCR */ cgc_clock_t pll_src = CGC_CLOCK_MAIN_OSC; - #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE || 3U == BSP_FEATURE_CGC_PLLCCR_TYPE || 5U == BSP_FEATURE_CGC_PLLCCR_TYPE + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || \ + (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) /* Get the PLL clock source */ if (R_SYSTEM->PLLCCR_b.PLSRCSEL == 1U) @@ -2336,9 +2347,11 @@ static fsp_err_t r_cgc_pllccr_pll_hz_calculate (cgc_pll_cfg_t const * const p_pl /* Calculate the PLLCCR register. */ uint32_t pllccr = r_cgc_pllccr_calculate(p_pll_cfg); - #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE || 3U == BSP_FEATURE_CGC_PLLCCR_TYPE || 4U == BSP_FEATURE_CGC_PLLCCR_TYPE || \ - 5U == BSP_FEATURE_CGC_PLLCCR_TYPE + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || \ + (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) volatile uint16_t * p_pllccr_reg; + #elif (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + volatile uint32_t * p_pllccr_reg; #else volatile uint8_t * p_pllccr_reg; #endif @@ -2347,8 +2360,10 @@ static fsp_err_t r_cgc_pllccr_pll_hz_calculate (cgc_pll_cfg_t const * const p_pl if (CGC_CLOCK_PLL == pll) #endif { - #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE || 3U == BSP_FEATURE_CGC_PLLCCR_TYPE || 4U == BSP_FEATURE_CGC_PLLCCR_TYPE || \ - 5U == BSP_FEATURE_CGC_PLLCCR_TYPE + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || \ + (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) || \ + (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + p_pllccr_reg = &(R_SYSTEM->PLLCCR); #else p_pllccr_reg = &(R_SYSTEM->PLLCCR2); @@ -2394,7 +2409,7 @@ static void r_cgc_pll_cfg (cgc_pll_cfg_t const * const p_pll_cfg, uint32_t const * const pll_hz, uint32_t pllccr) { - #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE || 5U == BSP_FEATURE_CGC_PLLCCR_TYPE + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) #if BSP_PRV_PLL2_SUPPORTED if (CGC_CLOCK_PLL == pll) #endif @@ -2412,7 +2427,7 @@ static void r_cgc_pll_cfg (cgc_pll_cfg_t const * const p_pll_cfg, #elif 2U == BSP_FEATURE_CGC_PLLCCR_TYPE R_SYSTEM->PLLCCR2 = (uint8_t) pllccr; FSP_PARAMETER_NOT_USED(p_pll_cfg); - #elif 3U == BSP_FEATURE_CGC_PLLCCR_TYPE + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) uint16_t pllccr2 = r_cgc_pllccr2_calculate(p_pll_cfg); #if BSP_PRV_PLL2_SUPPORTED if (CGC_CLOCK_PLL == pll) diff --git a/ra/fsp/src/r_crc/r_crc.c b/ra/fsp/src/r_crc/r_crc.c index cbc9e1422..4b6c28407 100644 --- a/ra/fsp/src/r_crc/r_crc.c +++ b/ra/fsp/src/r_crc/r_crc.c @@ -167,7 +167,7 @@ fsp_err_t R_CRC_Close (crc_ctrl_t * const p_ctrl) * * @retval FSP_SUCCESS Calculation successful. * @retval FSP_ERR_ASSERTION Either p_ctrl, inputBuffer, or calculatedValue is NULL. - * @retval FSP_ERR_INVALID_ARGUMENT length value is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT length value is NULL, or not 4-byte aligned when 32-bit CRC polynomial function is configured. * @retval FSP_ERR_NOT_OPEN The driver is not opened. **********************************************************************************************************************/ fsp_err_t R_CRC_Calculate (crc_ctrl_t * const p_ctrl, crc_input_t * const p_crc_input, uint32_t * calculatedValue) @@ -179,6 +179,11 @@ fsp_err_t R_CRC_Calculate (crc_ctrl_t * const p_ctrl, crc_input_t * const p_crc_ FSP_ASSERT(calculatedValue); FSP_ERROR_RETURN((0UL != p_crc_input->num_bytes), FSP_ERR_INVALID_ARGUMENT); FSP_ERROR_RETURN(CRC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + if ((p_instance_ctrl->p_cfg->polynomial == CRC_POLYNOMIAL_CRC_32) || + (p_instance_ctrl->p_cfg->polynomial == CRC_POLYNOMIAL_CRC_32C)) + { + FSP_ERROR_RETURN((p_crc_input->num_bytes & 0x03) == 0, FSP_ERR_INVALID_ARGUMENT); + } #endif /* Calculate CRC value for the input buffer */ @@ -400,10 +405,10 @@ static void crc_calculate_polynomial (crc_instance_ctrl_t * const p_instance_ctr crc_input_t * const p_crc_input, uint32_t * calculatedValue) { - uint32_t i; - void * inputBuffer = p_crc_input->p_input_buffer; - uint32_t length = p_crc_input->num_bytes; - uint32_t crc_seed = p_crc_input->crc_seed; + uint32_t i; + const void * inputBuffer = p_crc_input->p_input_buffer; + uint32_t length = p_crc_input->num_bytes; + uint32_t crc_seed = p_crc_input->crc_seed; crc_seed_value_update(p_instance_ctrl, crc_seed); /* Write each element of the inputBuffer to the CRC Data Input Register. Each write to the @@ -414,7 +419,7 @@ static void crc_calculate_polynomial (crc_instance_ctrl_t * const p_instance_ctr case CRC_POLYNOMIAL_CRC_16: case CRC_POLYNOMIAL_CRC_CCITT: { - uint8_t * p_data = (uint8_t *) inputBuffer; + const uint8_t * p_data = inputBuffer; for (i = (uint32_t) 0; i < length; i++) { /* CRCDIR is a 32-bit read/write register to write data to for CRC-32 or CRC-32C calculation. @@ -430,7 +435,7 @@ static void crc_calculate_polynomial (crc_instance_ctrl_t * const p_instance_ctr default: { - uint32_t * p_data = (uint32_t *) inputBuffer; + const uint32_t * p_data = inputBuffer; for (i = (uint32_t) 0; i < (length / 4); i++) { diff --git a/ra/fsp/src/r_dmac/r_dmac.c b/ra/fsp/src/r_dmac/r_dmac.c index f47500a11..b87910bea 100644 --- a/ra/fsp/src/r_dmac/r_dmac.c +++ b/ra/fsp/src/r_dmac/r_dmac.c @@ -30,48 +30,56 @@ (uint32_t) R_DMAC0)) /* Transfer Count Register A Bit Field Definitions */ -#define DMAC_PRV_DMCRA_LOW_OFFSET (0U) -#define DMAC_PRV_DMCRA_LOW_MASK (0x3FFU << DMAC_PRV_DMCRA_LOW_OFFSET) -#define DMAC_PRV_DMCRA_HIGH_OFFSET (16U) -#define DMAC_PRV_DMCRA_HIGH_MASK (0x3FFU << DMAC_PRV_DMCRA_HIGH_OFFSET) +#define DMAC_PRV_DMCRA_LOW_OFFSET (0U) +#define DMAC_PRV_DMCRA_LOW_MASK (0x3FFU << DMAC_PRV_DMCRA_LOW_OFFSET) +#define DMAC_PRV_DMCRA_HIGH_OFFSET (16U) +#define DMAC_PRV_DMCRA_HIGH_MASK (0x3FFU << DMAC_PRV_DMCRA_HIGH_OFFSET) /* Transfer Mode Register Bit Field Definitions */ -#define DMAC_PRV_DMTMD_DCTG_OFFSET (0U) -#define DMAC_PRV_DMTMD_DCTG_MASK (3U << DMAC_PRV_DMTMD_DCTG_OFFSET) -#define DMAC_PRV_DMTMD_SZ_OFFSET (8U) -#define DMAC_PRV_DMTMD_SZ_MASK (3U << DMAC_PRV_DMTMD_SZ_OFFSET) -#define DMAC_PRV_DMTMD_DTS_OFFSET (12U) -#define DMAC_PRV_DMTMD_DTS_MASK (3U << DMAC_PRV_DMTMD_DTS_OFFSET) -#define DMAC_PRV_DMTMD_MD_OFFSET (14U) -#define DMAC_PRV_DMTMD_MD_MASK (3U << DMAC_PRV_DMTMD_MD_OFFSET) +#define DMAC_PRV_DMTMD_DCTG_OFFSET (0U) +#define DMAC_PRV_DMTMD_DCTG_MASK (3U << DMAC_PRV_DMTMD_DCTG_OFFSET) +#define DMAC_PRV_DMTMD_SZ_OFFSET (8U) +#define DMAC_PRV_DMTMD_SZ_MASK (3U << DMAC_PRV_DMTMD_SZ_OFFSET) +#define DMAC_PRV_DMTMD_DTS_OFFSET (12U) +#define DMAC_PRV_DMTMD_DTS_MASK (3U << DMAC_PRV_DMTMD_DTS_OFFSET) +#define DMAC_PRV_DMTMD_MD_OFFSET (14U) +#define DMAC_PRV_DMTMD_MD_MASK (3U << DMAC_PRV_DMTMD_MD_OFFSET) /* Interrupt Setting Register Bit Field Definitions */ -#define DMAC_PRV_DMINT_DARIE_OFFSET (0U) -#define DMAC_PRV_DMINT_DARIE_MASK (1U << DMAC_PRV_DMINT_DARIE_OFFSET) -#define DMAC_PRV_DMINT_SARIE_OFFSET (1U) -#define DMAC_PRV_DMINT_SARIE_MASK (1U << DMAC_PRV_DMINT_SARIE_OFFSET) -#define DMAC_PRV_DMINT_RPTIE_OFFSET (2U) -#define DMAC_PRV_DMINT_RPTIE_MASK (1U << DMAC_PRV_DMINT_RPTIE_OFFSET) -#define DMAC_PRV_DMINT_ESIE_OFFSET (3U) -#define DMAC_PRV_DMINT_ESIE_MASK (1U << DMAC_PRV_DMINT_ESIE_OFFSET) -#define DMAC_PRV_DMINT_DTIE_OFFSET (4U) -#define DMAC_PRV_DMINT_DTIE_MASK (1U << DMAC_PRV_DMINT_DTIE_OFFSET) +#define DMAC_PRV_DMINT_DARIE_OFFSET (0U) +#define DMAC_PRV_DMINT_DARIE_MASK (1U << DMAC_PRV_DMINT_DARIE_OFFSET) +#define DMAC_PRV_DMINT_SARIE_OFFSET (1U) +#define DMAC_PRV_DMINT_SARIE_MASK (1U << DMAC_PRV_DMINT_SARIE_OFFSET) +#define DMAC_PRV_DMINT_RPTIE_OFFSET (2U) +#define DMAC_PRV_DMINT_RPTIE_MASK (1U << DMAC_PRV_DMINT_RPTIE_OFFSET) +#define DMAC_PRV_DMINT_ESIE_OFFSET (3U) +#define DMAC_PRV_DMINT_ESIE_MASK (1U << DMAC_PRV_DMINT_ESIE_OFFSET) +#define DMAC_PRV_DMINT_DTIE_OFFSET (4U) +#define DMAC_PRV_DMINT_DTIE_MASK (1U << DMAC_PRV_DMINT_DTIE_OFFSET) /* Address Mode Register Bit Field Definitions */ -#define DMAC_PRV_DMAMD_DARA_OFFSET (0U) -#define DMAC_PRV_DMAMD_DARA_MASK (0x1FU << DMAC_PRV_DMAMD_DARA_OFFSET) -#define DMAC_PRV_DMAMD_DM_OFFSET (6U) -#define DMAC_PRV_DMAMD_DM_MASK (3U << DMAC_PRV_DMAMD_DM_OFFSET) -#define DMAC_PRV_DMAMD_SARA_OFFSET (8U) -#define DMAC_PRV_DMAMD_SARA_MASK (0x1FU << DMAC_PRV_DMAMD_SARA_OFFSET) -#define DMAC_PRV_DMAMD_SM_OFFSET (14U) -#define DMAC_PRV_DMAMD_SM_MASK (3U << DMAC_PRV_DMAMD_SM_OFFSET) +#define DMAC_PRV_DMAMD_DARA_OFFSET (0U) +#define DMAC_PRV_DMAMD_DARA_MASK (0x1FU << DMAC_PRV_DMAMD_DARA_OFFSET) +#define DMAC_PRV_DMAMD_DM_OFFSET (6U) +#define DMAC_PRV_DMAMD_DM_MASK (3U << DMAC_PRV_DMAMD_DM_OFFSET) +#define DMAC_PRV_DMAMD_SARA_OFFSET (8U) +#define DMAC_PRV_DMAMD_SARA_MASK (0x1FU << DMAC_PRV_DMAMD_SARA_OFFSET) +#define DMAC_PRV_DMAMD_SM_OFFSET (14U) +#define DMAC_PRV_DMAMD_SM_MASK (3U << DMAC_PRV_DMAMD_SM_OFFSET) /* Software Start Register Bit Field Definitions */ -#define DMAC_PRV_DMREQ_SWREQ_OFFSET (0U) -#define DMAC_PRV_DMREQ_SWREQ_MASK (1U << DMAC_PRV_DMREQ_SWREQ_OFFSET) -#define DMAC_PRV_DMREQ_CLRS_OFFSET (4U) -#define DMAC_PRV_DMREQ_CLRS_MASK (1U << DMAC_PRV_DMREQ_CLRS_OFFSET) +#define DMAC_PRV_DMREQ_SWREQ_OFFSET (0U) +#define DMAC_PRV_DMREQ_SWREQ_MASK (1U << DMAC_PRV_DMREQ_SWREQ_OFFSET) +#define DMAC_PRV_DMREQ_CLRS_OFFSET (4U) +#define DMAC_PRV_DMREQ_CLRS_MASK (1U << DMAC_PRV_DMREQ_CLRS_OFFSET) + +#ifndef DMAC_CFG_ERROR_CHANNEL_CLEAR + #define DMAC_CFG_ERROR_CHANNEL_CLEAR (0) +#endif + +#ifndef DMAC_CFG_PRIORITY_MODE + #define DMAC_CFG_PRIORITY_MODE (0) +#endif /*********************************************************************************************************************** * Typedef definitions @@ -169,6 +177,11 @@ fsp_err_t R_DMAC_Open (transfer_ctrl_t * const p_api_ctrl, transfer_cfg_t const R_DMA->DMAST = 1; +#if BSP_FEATURE_DMAC_HAS_DMCTL + R_DMA->DMCTL = (DMAC_CFG_PRIORITY_MODE << R_DMA_DMCTL_PR_Pos) | + (DMAC_CFG_ERROR_CHANNEL_CLEAR << R_DMA_DMCTL_ERCH_Pos); +#endif + /* Configure the transfer settings. */ r_dmac_config_transfer_info(p_ctrl, p_cfg->p_info); @@ -404,10 +417,10 @@ fsp_err_t R_DMAC_Reload (transfer_ctrl_t * const p_api_ctrl, * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. **********************************************************************************************************************/ -fsp_err_t R_DMAC_CallbackSet (transfer_ctrl_t * const p_api_ctrl, - void ( * p_callback)(dmac_callback_args_t *), - void const * const p_context, - dmac_callback_args_t * const p_callback_memory) +fsp_err_t R_DMAC_CallbackSet (transfer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(dmac_callback_args_t *), + void const * const p_context, + dmac_callback_args_t * const p_callback_memory) { FSP_PARAMETER_NOT_USED(p_callback_memory); @@ -419,13 +432,12 @@ fsp_err_t R_DMAC_CallbackSet (transfer_ctrl_t * const p_api_ctrl, FSP_ERROR_RETURN(p_ctrl->open == DMAC_ID, FSP_ERR_NOT_OPEN); #endif - p_ctrl->p_callback = p_callback; - p_ctrl->p_context = p_context; + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; return FSP_SUCCESS; } - /*******************************************************************************************************************//** * Disable transfer and clean up internal data. Implements @ref transfer_api_t::close. * @@ -766,7 +778,7 @@ void dmac_int_isr (void) /* Clear IRQ to make sure it doesn't fire again after exiting */ R_BSP_IrqStatusClear(irq); - dmac_instance_ctrl_t * p_ctrl = (dmac_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + dmac_instance_ctrl_t * p_ctrl = (dmac_instance_ctrl_t *) R_FSP_IsrContextGet(irq); /* Call the callback routine if one is available */ dmac_callback_args_t args; diff --git a/ra/fsp/src/r_dtc/r_dtc.c b/ra/fsp/src/r_dtc/r_dtc.c index ad11f2c1d..64a7cf485 100644 --- a/ra/fsp/src/r_dtc/r_dtc.c +++ b/ra/fsp/src/r_dtc/r_dtc.c @@ -429,10 +429,10 @@ fsp_err_t R_DTC_Reload (transfer_ctrl_t * const p_api_ctrl, * * @retval FSP_ERR_UNSUPPORTED DTC does not support direct callbacks. **********************************************************************************************************************/ -fsp_err_t R_DTC_CallbackSet (transfer_ctrl_t * const p_api_ctrl, - void ( * p_callback)(transfer_callback_args_t *), - void const * const p_context, - transfer_callback_args_t * const p_callback_memory) +fsp_err_t R_DTC_CallbackSet (transfer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(transfer_callback_args_t *), + void const * const p_context, + transfer_callback_args_t * const p_callback_memory) { /* This function isn't supported. It is defined only to implement a required function of transfer_api_t. * Mark the input parameter as unused since this function isn't supported. */ diff --git a/ra/fsp/src/r_elc/r_elc.c b/ra/fsp/src/r_elc/r_elc.c index a9a2d545a..58246d8d6 100644 --- a/ra/fsp/src/r_elc/r_elc.c +++ b/ra/fsp/src/r_elc/r_elc.c @@ -84,7 +84,7 @@ const elc_api_t g_elc_on_elc = fsp_err_t R_ELC_Open (elc_ctrl_t * const p_ctrl, elc_cfg_t const * const p_cfg) { uint32_t i; - uint32_t i_shift = 1; + uint64_t i_shift = 1; elc_instance_ctrl_t * p_instance_ctrl = (elc_instance_ctrl_t *) p_ctrl; @@ -223,7 +223,6 @@ fsp_err_t R_ELC_LinkSet (elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral, /* Configure security attribution for ELSRn */ /* Devices that only have ELCSARB */ #if BSP_FEATURE_ELC_VERSION == 2 - R_ELC->ELCSARB &= (uint32_t) ~(1 << peripheral); /* Devices that have ELCSARB and ELCSARC */ @@ -240,7 +239,6 @@ fsp_err_t R_ELC_LinkSet (elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral, /* Restore write protection to SAR registers */ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); - #endif /* Set the event link register for the corresponding peripheral to the given signal */ diff --git a/ra/fsp/src/r_ether/r_ether.c b/ra/fsp/src/r_ether/r_ether.c index 7ad57825f..491324ef9 100644 --- a/ra/fsp/src/r_ether/r_ether.c +++ b/ra/fsp/src/r_ether/r_ether.c @@ -130,6 +130,29 @@ /* PAUSE link mask and shift values */ +#define ETHER_NO_DATA (0) + +/* Event mask for EESR register. */ +#define ETHER_EESR_ERR_GLOBAL_MASK (ETHER_EESR_EVENT_MASK_CERF | ETHER_EESR_EVENT_MASK_PRE | \ + ETHER_EESR_EVENT_MASK_RTSF | ETHER_EESR_EVENT_MASK_RTLF | \ + ETHER_EESR_EVENT_MASK_RRF | ETHER_EESR_EVENT_MASK_RMAF | \ + ETHER_EESR_EVENT_MASK_TRO | ETHER_EESR_EVENT_MASK_CD | \ + ETHER_EESR_EVENT_MASK_DLC | ETHER_EESR_EVENT_MASK_CND | \ + ETHER_EESR_EVENT_MASK_ADE | ETHER_EESR_EVENT_MASK_RFCOF | \ + ETHER_EESR_EVENT_MASK_RABT | ETHER_EESR_EVENT_MASK_TWB) +#define ETHER_EESR_RX_COMPLETE_MASK (ETHER_EESR_EVENT_MASK_FR) +#define ETHER_EESR_RX_MESSAGE_LOST_MASK (ETHER_EESR_EVENT_MASK_RFOF | ETHER_EESR_EVENT_MASK_RDE) +#define ETHER_EESR_TX_ABORTED_MASK (ETHER_EESR_EVENT_MASK_TABT) +#define ETHER_EESR_TX_BUFFER_EMPTY_MASK (ETHER_EESR_EVENT_MASK_TFUF | ETHER_EESR_EVENT_MASK_TDE) +#define ETHER_EESR_TX_COMPLETE_MASK (ETHER_EESR_EVENT_MASK_TC) + +/* Event mask for ECSR register. */ +#define ETHER_ECSR_ERR_GLOBAL_MASK (ETHER_ECSR_EVENT_MASK_ICD) +#define ETHER_ECSR_WAKEON_LAN_MASK (ETHER_ECSR_EVENT_MASK_MPD) + +#define ETHER_EESR_EVENT_NUM (6) +#define ETHER_ECSR_EVENT_NUM (2) + /*********************************************************************************************************************** * Typedef definitions ***********************************************************************************************************************/ @@ -139,6 +162,12 @@ typedef void (BSP_CMSE_NONSECURE_CALL * ether_prv_ns_callback)(ether_callback_ar typedef BSP_CMSE_NONSECURE_CALL void (*volatile ether_prv_ns_callback)(ether_callback_args_t * p_args); #endif +typedef struct st_ether_event_mask +{ + ether_event_t event; // Event code which is passed to user callback + uint32_t mask; // Mask to determine whether to call callback +} ether_event_mask_t; + /*********************************************************************************************************************** * Exported global functions (to be accessed by other files) ***********************************************************************************************************************/ @@ -229,6 +258,25 @@ static const ether_pause_resolution_t pause_resolution[ETHER_PAUSE_TABLE_ENTRIES {ETHER_PAUSE_MASKF, ETHER_PAUSE_VALD, ETHER_PAUSE_XMIT_OFF, ETHER_PAUSE_RECV_ON } }; +#if (!ETHER_CFG_KEEP_INTERRUPT_EVENT_BACKWORD_COMPATIBILITY) + +static const ether_event_mask_t ether_eesr_event_mask[ETHER_EESR_EVENT_NUM] = +{ + {.event = ETHER_EVENT_RX_COMPLETE, .mask = ETHER_EESR_RX_COMPLETE_MASK }, + {.event = ETHER_EVENT_RX_MESSAGE_LOST, .mask = ETHER_EESR_RX_MESSAGE_LOST_MASK}, + {.event = ETHER_EVENT_TX_COMPLETE, .mask = ETHER_EESR_TX_COMPLETE_MASK }, + {.event = ETHER_EVENT_TX_BUFFER_EMPTY, .mask = ETHER_EESR_TX_BUFFER_EMPTY_MASK}, + {.event = ETHER_EVENT_TX_ABORTED, .mask = ETHER_EESR_TX_ABORTED_MASK }, + {.event = ETHER_EVENT_ERR_GLOBAL, .mask = ETHER_EESR_ERR_GLOBAL_MASK }, +}; + +static const ether_event_mask_t ether_ecsr_event_mask[ETHER_ECSR_EVENT_NUM] = +{ + {.event = ETHER_EVENT_WAKEON_LAN, .mask = ETHER_ECSR_WAKEON_LAN_MASK}, + {.event = ETHER_EVENT_ERR_GLOBAL, .mask = ETHER_EESR_ERR_GLOBAL_MASK}, +}; +#endif + /*******************************************************************************************************************//** * @addtogroup ETHER * @{ @@ -1851,11 +1899,13 @@ static void ether_call_callback (ether_instance_ctrl_t * p_instance_ctrl, ether_ args = *p_args; } - p_args->event = p_callback_args->event; + p_args->event = p_callback_args->event; + p_args->channel = p_instance_ctrl->p_ether_cfg->channel; + p_args->p_context = p_instance_ctrl->p_context; +#if (ETHER_CFG_KEEP_INTERRUPT_EVENT_BACKWORD_COMPATIBILITY) p_args->status_ecsr = p_callback_args->status_ecsr; p_args->status_eesr = p_callback_args->status_eesr; - p_args->channel = p_instance_ctrl->p_ether_cfg->channel; - p_args->p_context = p_instance_ctrl->p_context; +#endif #if BSP_TZ_SECURE_BUILD && BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE @@ -1905,6 +1955,9 @@ void ether_eint_isr (void) IRQn_Type irq = R_FSP_CurrentIrqGet(); ether_instance_ctrl_t * p_instance_ctrl = (ether_instance_ctrl_t *) R_FSP_IsrContextGet(irq); +#if (!ETHER_CFG_KEEP_INTERRUPT_EVENT_BACKWORD_COMPATIBILITY) + ether_extended_cfg_t * p_ether_extended_cfg = (ether_extended_cfg_t *) p_instance_ctrl->p_ether_cfg->p_extend; +#endif p_reg_etherc = (R_ETHERC0_Type *) p_instance_ctrl->p_reg_etherc; p_reg_edmac = (R_ETHERC_EDMAC_Type *) p_instance_ctrl->p_reg_edmac; @@ -1956,12 +2009,38 @@ void ether_eint_isr (void) /* If a callback is provided, then call it with callback argument. */ if (NULL != p_instance_ctrl->p_callback) { - callback_arg.channel = p_instance_ctrl->p_ether_cfg->channel; + callback_arg.channel = p_instance_ctrl->p_ether_cfg->channel; + callback_arg.p_context = p_instance_ctrl->p_ether_cfg->p_context; +#if (ETHER_CFG_KEEP_INTERRUPT_EVENT_BACKWORD_COMPATIBILITY) callback_arg.event = ETHER_EVENT_INTERRUPT; callback_arg.status_ecsr = status_ecsr; callback_arg.status_eesr = status_eesr; - callback_arg.p_context = p_instance_ctrl->p_ether_cfg->p_context; ether_call_callback(p_instance_ctrl, &callback_arg); +#else + + /* Callbacks for events related to EESR. */ + for (int i = 0; i < ETHER_EESR_EVENT_NUM; i++) + { + if (status_eesr & ether_eesr_event_mask[i].mask & p_ether_extended_cfg->eesr_event_filter) + { + callback_arg.event = ether_eesr_event_mask[i].event; + ether_call_callback(p_instance_ctrl, &callback_arg); + } + } + + /* Callbacks for events related to ECSR. */ + if (status_eesr & ETHER_EDMAC_INTERRUPT_FACTOR_ECI) + { + for (int i = 0; i < ETHER_ECSR_EVENT_NUM; i++) + { + if (status_ecsr & ether_ecsr_event_mask[i].mask & p_ether_extended_cfg->ecsr_event_filter) + { + callback_arg.event = ether_ecsr_event_mask[i].event; + ether_call_callback(p_instance_ctrl, &callback_arg); + } + } + } +#endif } /* Clear pending interrupt flag to make sure it doesn't fire again diff --git a/ra/fsp/src/r_flash_hp/r_flash_hp.c b/ra/fsp/src/r_flash_hp/r_flash_hp.c index 0d4590f56..0b24992f4 100644 --- a/ra/fsp/src/r_flash_hp/r_flash_hp.c +++ b/ra/fsp/src/r_flash_hp/r_flash_hp.c @@ -2028,7 +2028,7 @@ static fsp_err_t flash_hp_pe_mode_exit (void) #endif } -#if BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE +#ifdef R_CACHE else if (FLASH_HP_FENTRYR_DF_PE_MODE == pe_mode) { /* Flush the C-CACHE. */ @@ -2704,7 +2704,7 @@ static fsp_err_t flash_hp_enter_pe_cf_mode (flash_hp_instance_ctrl_t * const p_c /* While the Flash API is in use we will disable the flash cache. */ #if BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM R_BSP_FlashCacheDisable(); - #elif BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE + #elif defined(R_CACHE) /* Disable the C-Cache. */ R_CACHE->CCACTL = 0U; diff --git a/ra/fsp/src/r_flash_lp/r_flash_lp.c b/ra/fsp/src/r_flash_lp/r_flash_lp.c index 984ec8410..8ef6aedcf 100644 --- a/ra/fsp/src/r_flash_lp/r_flash_lp.c +++ b/ra/fsp/src/r_flash_lp/r_flash_lp.c @@ -193,12 +193,11 @@ static void r_flash_lp_df_enter_pe_mode(flash_lp_instance_ctrl_t * const p_ctrl) #if (FLASH_LP_CFG_DATA_FLASH_BGO_SUPPORT_ENABLE == 1) -static inline bool r_flash_lp_frdyi_df_bgo_blankcheck(flash_lp_instance_ctrl_t * p_ctrl, - flash_callback_args_t * p_cb_data); +static bool r_flash_lp_frdyi_df_bgo_blankcheck(flash_lp_instance_ctrl_t * p_ctrl, flash_callback_args_t * p_cb_data); -static inline bool r_flash_lp_frdyi_df_bgo_erase(flash_lp_instance_ctrl_t * p_ctrl, flash_callback_args_t * p_cb_data); +static bool r_flash_lp_frdyi_df_bgo_erase(flash_lp_instance_ctrl_t * p_ctrl, flash_callback_args_t * p_cb_data); -static inline bool r_flash_lp_frdyi_df_bgo_write(flash_lp_instance_ctrl_t * p_ctrl, flash_callback_args_t * p_cb_data); +static bool r_flash_lp_frdyi_df_bgo_write(flash_lp_instance_ctrl_t * p_ctrl, flash_callback_args_t * p_cb_data); #endif static fsp_err_t r_flash_lp_df_write_monitor(flash_lp_instance_ctrl_t * const p_ctrl); @@ -1909,7 +1908,8 @@ static void r_flash_lp_reset (flash_lp_instance_ctrl_t * const p_ctrl) * * @retval true When operation is completed or error has occurred. **********************************************************************************************************************/ -static inline bool r_flash_lp_frdyi_df_bgo_write (flash_lp_instance_ctrl_t * p_ctrl, flash_callback_args_t * p_cb_data) +__STATIC_INLINE bool r_flash_lp_frdyi_df_bgo_write (flash_lp_instance_ctrl_t * p_ctrl, + flash_callback_args_t * p_cb_data) { bool operation_complete = false; fsp_err_t result = FSP_SUCCESS; @@ -1945,7 +1945,8 @@ static inline bool r_flash_lp_frdyi_df_bgo_write (flash_lp_instance_ctrl_t * p_c * * @retval true When operation is completed or error has occurred. **********************************************************************************************************************/ -static inline bool r_flash_lp_frdyi_df_bgo_erase (flash_lp_instance_ctrl_t * p_ctrl, flash_callback_args_t * p_cb_data) +__STATIC_INLINE bool r_flash_lp_frdyi_df_bgo_erase (flash_lp_instance_ctrl_t * p_ctrl, + flash_callback_args_t * p_cb_data) { fsp_err_t result = FSP_SUCCESS; @@ -1977,8 +1978,8 @@ static inline bool r_flash_lp_frdyi_df_bgo_erase (flash_lp_instance_ctrl_t * p_c * * @retval true When operation is completed or error has occurred. **********************************************************************************************************************/ -static inline bool r_flash_lp_frdyi_df_bgo_blankcheck (flash_lp_instance_ctrl_t * p_ctrl, - flash_callback_args_t * p_cb_data) +__STATIC_INLINE bool r_flash_lp_frdyi_df_bgo_blankcheck (flash_lp_instance_ctrl_t * p_ctrl, + flash_callback_args_t * p_cb_data) { fsp_err_t result = FSP_SUCCESS; diff --git a/ra/fsp/src/r_gpt/r_gpt.c b/ra/fsp/src/r_gpt/r_gpt.c index e7b3f778c..c5ffbeda2 100644 --- a/ra/fsp/src/r_gpt/r_gpt.c +++ b/ra/fsp/src/r_gpt/r_gpt.c @@ -17,12 +17,19 @@ /* "GPT" in ASCII, used to determine if channel is open. */ #define GPT_OPEN (0x00475054ULL) +#define GPT_PRV_GPTE_OR_GPTEH_SUPPORTED (BSP_FEATURE_GPT_GPTEH_SUPPORTED | \ + BSP_FEATURE_GPT_GPTE_SUPPORTED) #define GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK (BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK | \ BSP_FEATURE_GPT_GPTE_CHANNEL_MASK) - -#define GPT_PRV_ADC_TRIGGER_CHANNEL_MASK (GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK | \ - BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK) - +#define GPT_PRV_ADC_DIRECT_START_SUPPORTED (BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED) +#define GPT_PRV_ADC_DIRECT_START_CHANNEL_MASK (BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK) +#define GPT_PRV_ADC_ELC_START_SUPPORTED (GPT_PRV_GPTE_OR_GPTEH_SUPPORTED && \ + !GPT_PRV_ADC_DIRECT_START_SUPPORTED) // ELC-start is 'default' and exists if direct-start is not present +#define GPT_PRV_ADC_ELC_START_CHANNEL_MASK (GPT_PRV_ADC_DIRECT_START_SUPPORTED ? \ + 0x0 : GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK) // No ELC-start present if direct start is supported. + +#define GPT_PRV_ODC_SUPPORTED (BSP_FEATURE_GPT_GPTEH_SUPPORTED) +#define GPT_PRV_ODC_CHANNEL_MASK (BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK) #define GPT_PRV_GTWP_RESET_VALUE (0xA500U) #define GPT_PRV_GTWP_WRITE_PROTECT (0xA501U) @@ -219,8 +226,7 @@ fsp_err_t R_GPT_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_c p_instance_ctrl->channel_mask = 1U << p_cfg->channel; #if GPT_CFG_PARAM_CHECKING_ENABLE - FSP_ERROR_RETURN((p_instance_ctrl->channel_mask & BSP_FEATURE_GPT_VALID_CHANNEL_MASK), - FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN((p_instance_ctrl->channel_mask & BSP_PERIPHERAL_GPT_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); if ((p_cfg->p_callback) || (TIMER_MODE_ONE_SHOT == p_cfg->mode)) { FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); @@ -856,14 +862,13 @@ fsp_err_t R_GPT_PwmOutputDelaySet (timer_ctrl_t * const p_ctrl, gpt_pwm_output_delay_setting_t delay_setting, uint32_t const pin) { -#if 0U != BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK && GPT_CFG_OUTPUT_SUPPORT_ENABLE +#if 0U != GPT_PRV_ODC_SUPPORTED && GPT_CFG_OUTPUT_SUPPORT_ENABLE gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; #if GPT_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_instance_ctrl); FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); - FSP_ERROR_RETURN(0U != (BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK & p_instance_ctrl->channel_mask), - FSP_ERR_INVALID_CHANNEL); + FSP_ERROR_RETURN(0U != (GPT_PRV_ODC_CHANNEL_MASK & p_instance_ctrl->channel_mask), FSP_ERR_INVALID_CHANNEL); FSP_ERROR_RETURN(0U != (R_GPT_ODC->GTDLYCR1 & R_GPT_ODC_GTDLYCR1_DLLEN_Msk), FSP_ERR_NOT_INITIALIZED); if (TIMER_MODE_PWM == p_instance_ctrl->p_cfg->mode) @@ -937,6 +942,10 @@ fsp_err_t R_GPT_PwmOutputDelaySet (timer_ctrl_t * const p_ctrl, uint16_t * p_gtdlyfnx = (uint16_t *) ((uint32_t) &R_GPT_ODC->GTDLYR[0].A + channel_offset + pin_offset + edge_offset); + #if BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED + delay_setting *= 4; // Delay count is out of 32, per the API. Convert provided 32-count resolution into 128-count register setting. + #endif + /* Unprotect the delay setting register. */ uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl); @@ -1091,14 +1100,14 @@ fsp_err_t R_GPT_Close (timer_ctrl_t * const p_ctrl) * @retval FSP_ERR_INVALID_STATE The source clock frequnecy is out of the required range for the PDG. * @retval FSP_ERR_UNSUPPORTED This feature is not supported. **********************************************************************************************************************/ -fsp_err_t R_GPT_PwmOutputDelayInitialize (void) +fsp_err_t R_GPT_PwmOutputDelayInitialize () { -#if 0U != BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK && GPT_CFG_OUTPUT_SUPPORT_ENABLE - #if BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN > 0 || GPT_CFG_PARAM_CHECKING_ENABLE - #if BSP_FEATURE_BSP_HAS_GPT_CLOCK && GPT_CFG_GPTCLK_BYPASS == 0 +#if (BSP_FEATURE_GPT_GPTEH_SUPPORTED && GPT_CFG_OUTPUT_SUPPORT_ENABLE) + #if ((BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN > 0) || GPT_CFG_PARAM_CHECKING_ENABLE) + #if (BSP_PERIPHERAL_GPT_GTCLK_PRESENT && (GPT_CFG_GPTCLK_BYPASS == 0)) /* Calculate the GPTCK Divider. */ - uint32_t divider = R_SYSTEM->GPTCKDIVCR; + uint8_t divider = R_SYSTEM->GPTCKDIVCR; if (0U == divider) { @@ -1126,20 +1135,17 @@ fsp_err_t R_GPT_PwmOutputDelayInitialize (void) uint32_t gtdlycr1 = R_GPT_ODC_GTDLYCR1_DLYRST_Msk; #if BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN > 0 - if (BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN >= gpt_frequency) - { - gtdlycr1 |= R_GPT_ODC_GTDLYCR1_FRANGE_Msk; - } + gtdlycr1 |= BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency); #endif - #if BSP_FEATURE_BSP_HAS_GPT_CLOCK && GPT_CFG_GPTCLK_BYPASS + #if BSP_PERIPHERAL_GPT_GTCLK_PRESENT && GPT_CFG_GPTCLK_BYPASS /* Bypass the GPTCLK. GPT instances will use PCLKD as the GPT Core clock. */ R_GPT_GTCLK->GTCLKCR = 1U; #endif /* Cancel the module-stop state for the PDG. */ - R_BSP_MODULE_START(FSP_IP_GPT, 0); + R_BSP_MODULE_START(FSP_IP_GPT_PDG, 0); #if GPT_CFG_WRITE_PROTECT_ENABLE @@ -1258,7 +1264,7 @@ static void gpt_hardware_initialize (gpt_instance_ctrl_t * const p_instance_ctrl /* Save pointer to extended configuration structure. */ gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_cfg->p_extend; -#if BSP_FEATURE_BSP_HAS_GPT_CLOCK && GPT_CFG_GPTCLK_BYPASS +#if BSP_PERIPHERAL_GPT_GTCLK_PRESENT && GPT_CFG_GPTCLK_BYPASS /* Bypass the GPTCLK. GPT instances will use PCLKD as the GPT Core clock. */ R_GPT_GTCLK->GTCLKCR = 1U; @@ -1268,8 +1274,8 @@ static void gpt_hardware_initialize (gpt_instance_ctrl_t * const p_instance_ctrl * register, PCLK divisor register, and counter register. */ R_BSP_MODULE_START(FSP_IP_GPT, p_cfg->channel); -#if GPT_CFG_OUTPUT_SUPPORT_ENABLE && BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK - if (0U != (BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK & p_instance_ctrl->channel_mask)) +#if (GPT_CFG_OUTPUT_SUPPORT_ENABLE && BSP_FEATURE_GPT_GPTEH_SUPPORTED) + if (0U != (BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK & p_instance_ctrl->channel_mask)) { /* Enter a critical section in order to ensure that multiple GPT channels don't access the common * register simultaneously. */ @@ -1409,7 +1415,7 @@ static void gpt_hardware_initialize (gpt_instance_ctrl_t * const p_instance_ctrl r_gpt_init_compare_match_channel(p_instance_ctrl); -#if GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK +#if GPT_PRV_GPTE_OR_GPTEH_SUPPORTED if ((1U << p_cfg->channel) & GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK) { /* This register is available on GPTE and GPTEH only. It must be cleared before setting. When modifying the @@ -1418,41 +1424,54 @@ static void gpt_hardware_initialize (gpt_instance_ctrl_t * const p_instance_ctrl p_instance_ctrl->p_reg->GTITC = 0U; } #endif - uint32_t gtintad = 0; - uint32_t gtdtcr = 0; + #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg; if (NULL != p_pwm_cfg) { - gtintad |= ((uint32_t) p_pwm_cfg->output_disable << R_GPT0_GTINTAD_GRPDTE_Pos) | - ((uint32_t) p_pwm_cfg->poeg_link << R_GPT0_GTINTAD_GRP_Pos); - p_instance_ctrl->p_reg->GTDVU = p_pwm_cfg->dead_time_count_up; + uint32_t gtintad = ((uint32_t) p_pwm_cfg->output_disable << R_GPT0_GTINTAD_GRPDTE_Pos) | + ((uint32_t) p_pwm_cfg->poeg_link << R_GPT0_GTINTAD_GRP_Pos); - /* Set GTDTCR.TDE only if one of the dead time values is non-zero. */ - gtdtcr |= ((p_pwm_cfg->dead_time_count_up > 0) || (p_pwm_cfg->dead_time_count_down > 0)); + /* Configure PWM Dead-time. + * GTDVU is available on most timers, while GTDVD is only available on a subset of timers (GPTE/GPTEH) */ + #if BSP_FEATURE_GPT_GTDVU_SUPPORTED + if ((1U << p_cfg->channel) & (BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK | GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK)) + { + /* Enable Dead-time nagative-phase waveform + * Set GTDTCR.TDE only if one of the dead time values is non-zero. */ + p_instance_ctrl->p_reg->GTDTCR = + ((p_pwm_cfg->dead_time_count_up > 0) || (p_pwm_cfg->dead_time_count_down > 0)); + + /* Dead time value register GTDVU */ + p_instance_ctrl->p_reg->GTDVU = p_pwm_cfg->dead_time_count_up; + } + #endif - #if GPT_PRV_ADC_TRIGGER_CHANNEL_MASK - if ((1 << p_cfg->channel) & GPT_PRV_ADC_TRIGGER_CHANNEL_MASK) + #if (GPT_PRV_ADC_DIRECT_START_SUPPORTED || GPT_PRV_ADC_ELC_START_SUPPORTED) + if ((1U << p_cfg->channel) & (GPT_PRV_ADC_DIRECT_START_CHANNEL_MASK | + GPT_PRV_ADC_ELC_START_CHANNEL_MASK)) { - #if GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK + #if (GPT_PRV_GPTE_OR_GPTEH_SUPPORTED) - /* These registers are only available on MCUs with GPTE, GPTEH, or GPT with A/D Converter Start. */ + /* Dead time value register GTDVD */ + p_instance_ctrl->p_reg->GTDVD = p_pwm_cfg->dead_time_count_down; + + /* GTITC is always present for GPTE and GPTEH timers */ p_instance_ctrl->p_reg->GTITC = ((uint32_t) p_pwm_cfg->interrupt_skip_source << R_GPT0_GTITC_IVTC_Pos) | ((uint32_t) p_pwm_cfg->interrupt_skip_count << R_GPT0_GTITC_IVTT_Pos) | ((uint32_t) p_pwm_cfg->interrupt_skip_adc << R_GPT0_GTITC_ADTAL_Pos); - p_instance_ctrl->p_reg->GTDVD = p_pwm_cfg->dead_time_count_down; #endif - /* Set A/D Conversion Start Request counts */ + /* Configure AD Compare match behavior */ + gtintad |= ((uint32_t) p_pwm_cfg->adc_trigger << R_GPT0_GTINTAD_ADTRAUEN_Pos); p_instance_ctrl->p_reg->GTADTRA = p_pwm_cfg->adc_a_compare_match; p_instance_ctrl->p_reg->GTADTRB = p_pwm_cfg->adc_b_compare_match; - - gtintad |= ((uint32_t) p_pwm_cfg->adc_trigger << R_GPT0_GTINTAD_ADTRAUEN_Pos); } #endif + p_instance_ctrl->p_reg->GTINTAD = gtintad; - /* Check if custom GTIOR settings are provided. */ + /* Check if custom GTIOR (Input/Output) settings are provided. */ if (0 == p_extend->gtior_setting.gtior) { /* If custom GTIOR settings are not provided, set gtioca_disable_settings and gtiocb_disable_settings. */ @@ -1460,13 +1479,16 @@ static void gpt_hardware_initialize (gpt_instance_ctrl_t * const p_instance_ctrl gtior |= (uint32_t) (p_pwm_cfg->gtiocb_disable_setting << R_GPT0_GTIOR_OBDF_Pos); } } + else #endif - /* GTADTR* registers are unused if GTINTAD is cleared. */ - p_instance_ctrl->p_reg->GTINTAD = gtintad; - p_instance_ctrl->p_reg->GTDTCR = gtdtcr; + { + /* GTADTR* registers are unused if GTINTAD is cleared. */ + p_instance_ctrl->p_reg->GTINTAD = 0U; - /* GTDVU, GTDVD, GTDBU, GTDBD, and GTSOTR are not used if GTDTCR is cleared. */ + /* GTDVU, GTDVD, GTDBU, GTDBD, and GTSOTR are not used if GTDTCR is cleared. */ + p_instance_ctrl->p_reg->GTDTCR = 0U; + } /* Check if custom GTIOR settings are provided. */ if (0 == p_extend->gtior_setting.gtior) @@ -1501,9 +1523,6 @@ static void gpt_hardware_initialize (gpt_instance_ctrl_t * const p_instance_ctrl } #endif - /* Reset counter to 0. */ - p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask; - /* Set the I/O control register. */ p_instance_ctrl->p_reg->GTIOR = gtior; @@ -1513,6 +1532,9 @@ static void gpt_hardware_initialize (gpt_instance_ctrl_t * const p_instance_ctrl p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc | 3U; p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc | 1U; + /* Reset counter to 0. */ + p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask; + r_gpt_write_protect_enable(p_instance_ctrl, GPT_PRV_GTWP_WRITE_PROTECT); /* Enable CPU interrupts if callback is not null. Also enable interrupts for one shot mode. @@ -1577,7 +1599,7 @@ static void r_gpt_enable_irq (IRQn_Type const irq, uint32_t priority, void * p_c #if GPT_CFG_OUTPUT_SUPPORT_ENABLE /*******************************************************************************************************************//** - * Calculates duty cycle register values. GTPBR must be set before entering this function. + * Calculates duty cycle register values. GTPR must be set before entering this function. * * @param[in] p_instance_ctrl Instance control structure * @param[in] duty_cycle_counts Duty cycle to set diff --git a/ra/fsp/src/r_i3c/r_i3c.c b/ra/fsp/src/r_i3c/r_i3c.c index 53f7fd7ec..536456b39 100644 --- a/ra/fsp/src/r_i3c/r_i3c.c +++ b/ra/fsp/src/r_i3c/r_i3c.c @@ -10,9 +10,12 @@ #include "r_i3c.h" #include "r_i3c_cfg.h" -/* The address of the MCU Version Register on RA2E2 MCUs. Different error recovery procedures are used depending on the - * version of the MCU (This is only used on RA2E2 devices). */ -#define I3C_A2E2_VERSION (*((uint8_t const *) 0x01001C20U)) +/* The address of the MCU Version Register on RA2E2/RA2L2 MCUs. Different error recovery procedures are used depending on the + * version of the MCU (This is only used on RA2E2/RA2L2 devices). */ +#define I3C_A2E2_VERSION (*((uint8_t const *) 0x01001C20U)) + +/* Version of the MCU (This is only used on RA2L2_EK Boards). */ +#define I3C_A2L2_VERSION_1 51U /*********************************************************************************************************************** * Typedef definitions @@ -255,12 +258,12 @@ fsp_err_t R_I3C_Open (i3c_ctrl_t * const p_api_ctrl, i3c_cfg_t const * const p_c /* * Reset the I3C Peripheral so that it is in a known state during initialization (See Figure 25.102 I3C Communication Flow - * in the RA2E2 manual R01UH0919EJ0100). + * in the hardware user manual R01UH0919EJ0100). */ p_ctrl->p_reg->BCTL_b.BUSE = 0; p_ctrl->p_reg->RSTCTL = 1U; - /* The field will be cleared automatically upon reset completion (See section 25.2.5 in the RA2E2 manual R01UH0919EJ0100). */ + /* The field will be cleared automatically upon reset completion (See section 25.2.5 in the hardware user manual R01UH0919EJ0100). */ FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->RSTCTL, 0U); /* Set I3C mode. */ @@ -290,7 +293,7 @@ fsp_err_t R_I3C_Enable (i3c_ctrl_t * const p_api_ctrl) i3c_extended_cfg_t const * p_extend = (i3c_extended_cfg_t const *) p_ctrl->p_cfg->p_extend; /* - * Write all remaining configuration settings (See Figure 25.102 I3C Communication Flow in the RA2E2 + * Write all remaining configuration settings (See Figure 25.102 I3C Communication Flow in the hardware user * manual R01UH0919EJ0100). * * Configure the Normal IBI Data Segment Size used for receiving IBI data. @@ -444,6 +447,12 @@ fsp_err_t R_I3C_Enable (i3c_ctrl_t * const p_api_ctrl) uint32_t cmrlg = (uint32_t) p_extend->slave_command_response_info.read_length; cmrlg |= (uint32_t) p_extend->slave_command_response_info.ibi_payload_length << R_I3C0_CMRLG_IBIPSZ_Pos; + #if BSP_FEATURE_I3C_HAS_HDR_MODE + uint32_t cghdrcap = (uint32_t) p_extend->slave_command_response_info.hdr_ddr_support; + cghdrcap |= (uint32_t) p_extend->slave_command_response_info.hdr_tsp_support << R_I3C0_CGHDRCAP_TSPEN_Pos; + cghdrcap |= (uint32_t) p_extend->slave_command_response_info.hdr_tsp_support << R_I3C0_CGHDRCAP_TSLEN_Pos; + #endif + /* Write Slave Command Response Info. */ p_ctrl->p_reg->CSECMD = csecmd; p_ctrl->p_reg->CEACTST = (1U << p_extend->slave_command_response_info.activity_state); @@ -455,6 +464,10 @@ fsp_err_t R_I3C_Enable (i3c_ctrl_t * const p_api_ctrl) p_ctrl->p_reg->CMDSPR = cmdspr; p_ctrl->p_reg->CMDSPT = cmdspt; p_ctrl->p_reg->CETSM = cetsm; + + #if BSP_FEATURE_I3C_HAS_HDR_MODE + p_ctrl->p_reg->CGHDRCAP = cghdrcap; + #endif #endif /* Enable the I3C Bus. */ @@ -507,7 +520,7 @@ fsp_err_t R_I3C_DeviceCfgSet (i3c_ctrl_t * const p_api_ctrl, i3c_device_cfg_t co { /* * Configure the master dynamic address and set it to valid (See Figure 25.102 I3C Communication Flow - * in the RA2E2 manual R01UH0919EJ0100). + * in the hardware user manual R01UH0919EJ0100). */ uint32_t msdvad = (uint32_t) p_device_cfg->dynamic_address << R_I3C0_MSDVAD_MDYAD_Pos; msdvad |= R_I3C0_MSDVAD_MDYADV_Msk; @@ -523,7 +536,7 @@ fsp_err_t R_I3C_DeviceCfgSet (i3c_ctrl_t * const p_api_ctrl, i3c_device_cfg_t co /* * Configure slave device address table, Device Characteristics, Bus Characteristics, and - * Provisional ID (See Figure 25.102 I3C Communication Flow in the RA2E2 manual R01UH0919EJ0100). + * Provisional ID (See Figure 25.102 I3C Communication Flow in the hardware user manual R01UH0919EJ0100). * * Configure the device static address. */ uint32_t sdatbas0 = (uint32_t) p_device_cfg->static_address & R_I3C0_SDATBAS0_SDSTAD_Msk; @@ -694,7 +707,11 @@ fsp_err_t R_I3C_DeviceSelect (i3c_ctrl_t * const p_api_ctrl, uint32_t device_ind #if I3C_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_api_ctrl); FSP_ERROR_RETURN(I3C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + #if BSP_FEATURE_I3C_HAS_HDR_MODE + FSP_ASSERT(I3C_BITRATE_MODE_I3C_HDR_DDR_STDBR >= bitrate_mode); + #else FSP_ASSERT(I3C_BITRATE_MODE_I3C_SDR4_EXTBR_X4 >= bitrate_mode); + #endif FSP_ERROR_RETURN( I3C_INTERNAL_STATE_SLAVE_IDLE != p_ctrl->internal_state && I3C_INTERNAL_STATE_DISABLED != p_ctrl->internal_state, FSP_ERR_INVALID_MODE); @@ -786,7 +803,7 @@ fsp_err_t R_I3C_DynamicAddressAssignmentStart (i3c_ctrl_t * const p_a /* * Write to the descriptor to the command queue. * Note that the command descriptor is two words. The least significant word must be written first followed by - * the most significant word (See Section 25.3.1.1 in the RA2E2 manual R01UH0919EJ0100). + * the most significant word (See Section 25.3.1.1 in the hardware user manual R01UH0919EJ0100). */ p_ctrl->p_reg->NCMDQP = command_descriptor; p_ctrl->p_reg->NCMDQP = 0U; @@ -818,7 +835,7 @@ fsp_err_t R_I3C_DynamicAddressAssignmentStart (i3c_ctrl_t * const p_a * @retval FSP_ERR_UNSUPPORTED Master support must be enabled to call this function. Slave support must be * enabled when sending the GETACCMST command. **********************************************************************************************************************/ -fsp_err_t R_I3C_CommandSend (i3c_ctrl_t * const p_api_ctrl, i3c_command_descriptor_t * p_command_descriptor) +fsp_err_t R_I3C_CommandSend (i3c_ctrl_t * const p_api_ctrl, i3c_command_descriptor_t const * const p_command_descriptor) { #if I3C_CFG_MASTER_SUPPORT i3c_instance_ctrl_t * p_ctrl = (i3c_instance_ctrl_t *) p_api_ctrl; @@ -841,6 +858,14 @@ fsp_err_t R_I3C_CommandSend (i3c_ctrl_t * const p_api_ctrl, i3c_command_descript /* Verify that the buffer is aligned to 4 bytes. */ FSP_ERROR_RETURN(0U == ((uint32_t) p_command_descriptor->p_buffer & 0x03U), FSP_ERR_INVALID_ALIGNMENT); #endif + + #if BSP_FEATURE_I3C_HAS_HDR_MODE + if (I3C_BITRATE_MODE_I3C_HDR_DDR_STDBR == p_ctrl->device_bitrate_mode) + { + /* Verify that length is a multiple of 2 in HDR modes. */ + FSP_ERROR_RETURN(p_command_descriptor->length % 2 == 0, FSP_ERR_INVALID_ALIGNMENT); + } + #endif #endif /* The driver does not currently support relinquishing mastership to secondary masters. */ @@ -886,7 +911,7 @@ fsp_err_t R_I3C_CommandSend (i3c_ctrl_t * const p_api_ctrl, i3c_command_descript /* Calculate the command descriptor. */ uint32_t cmd1 = 0; cmd1 |= (p_ctrl->device_index << I3C_CMD_DESC_DEV_INDEX_Pos) & I3C_CMD_DESC_DEV_INDEX_Msk; - cmd1 |= (0 << I3C_CMD_DESC_XFER_MODE_Pos) & I3C_CMD_DESC_XFER_MODE_Msk; + cmd1 |= ((uint32_t) p_ctrl->device_bitrate_mode << I3C_CMD_DESC_XFER_MODE_Pos) & I3C_CMD_DESC_XFER_MODE_Msk; cmd1 |= (uint32_t) (p_command_descriptor->rnw << I3C_CMD_DESC_XFER_RNW_Pos); cmd1 |= I3C_CMD_DESC_ROC_Msk; cmd1 |= (uint32_t) (!p_command_descriptor->restart << I3C_CMD_DESC_TOC_Pos) & I3C_CMD_DESC_TOC_Msk; @@ -898,7 +923,7 @@ fsp_err_t R_I3C_CommandSend (i3c_ctrl_t * const p_api_ctrl, i3c_command_descript if ((4 >= p_command_descriptor->length) && !p_command_descriptor->rnw) { /* If the transfer length is less than or equal to 4 bytes, then use "Immediate Data Transfer". - * See section "25.3.1.1.2 Immediate Transfer Command" in the RA2E2 manual R01UH0919EJ0100. */ + * See section "25.3.1.1.2 Immediate Transfer Command" in the hardware user manual R01UH0919EJ0100. */ cmd1 |= I3C_CMD_DESC_CND_ATTR_IMMED_DATA_XFER; cmd1 |= (p_command_descriptor->length << I3C_CMD_DESC_IMMED_DATA_XFER_BYTE_CNT_Pos); cmd2 = i3c_next_data_word_calculate(&p_ctrl->write_buffer_descriptor); @@ -913,7 +938,7 @@ fsp_err_t R_I3C_CommandSend (i3c_ctrl_t * const p_api_ctrl, i3c_command_descript /* * Write the descriptor to the command queue. * Note that the command descriptor is two words. The least significant word must be written first followed by - * the most significant word (See Section 25.3.1.1 in the RA2E2 manual R01UH0919EJ0100). + * the most significant word (See Section 25.3.1.1 in the hardware user manual R01UH0919EJ0100). */ p_ctrl->p_reg->NCMDQP = cmd1; p_ctrl->p_reg->NCMDQP = cmd2; @@ -954,7 +979,7 @@ fsp_err_t R_I3C_CommandSend (i3c_ctrl_t * const p_api_ctrl, i3c_command_descript * @retval FSP_ERR_ASSERTION An argument was NULL. * @retval FSP_ERR_NOT_OPEN This instance has not been opened yet. * @retval FSP_ERR_IN_USE The operation could not be completed because the driver is busy. - * @retval FSP_ERR_INVALID_MODE This driver is disabled. + * @retval FSP_ERR_INVALID_MODE This driver is disabled, or an invalid bitrate mode is selected. * @retval FSP_ERR_INVALID_ALIGNMENT The buffer must be aligned to 4 bytes. **********************************************************************************************************************/ fsp_err_t R_I3C_Write (i3c_ctrl_t * const p_api_ctrl, uint8_t const * const p_data, uint32_t length, bool restart) @@ -975,6 +1000,14 @@ fsp_err_t R_I3C_Write (i3c_ctrl_t * const p_api_ctrl, uint8_t const * const p_da /* Verify that the buffer is aligned to 4 bytes. */ FSP_ERROR_RETURN(0U == ((uint32_t) p_data & 0x03U), FSP_ERR_INVALID_ALIGNMENT); #endif + + #if BSP_FEATURE_I3C_HAS_HDR_MODE + if (I3C_INTERNAL_STATE_MASTER_IDLE == p_ctrl->internal_state) + { + /* In master mode, this function can only be called to start SDR and I2C transfers. */ + FSP_ERROR_RETURN(p_ctrl->device_bitrate_mode < I3C_BITRATE_MODE_I3C_HDR_DDR_STDBR, FSP_ERR_INVALID_MODE); + } + #endif #endif #if I3C_CFG_SLAVE_SUPPORT @@ -1012,7 +1045,7 @@ fsp_err_t R_I3C_Write (i3c_ctrl_t * const p_api_ctrl, uint8_t const * const p_da */ p_ctrl->p_reg->RSTCTL = R_I3C0_RSTCTL_TDBRST_Msk; - /* The field will be cleared automatically upon reset completion (See section 25.2.5 in the RA2E2 manual R01UH0919EJ0100). */ + /* The field will be cleared automatically upon reset completion (See section 25.2.5 in the hardware user manual R01UH0919EJ0100). */ FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->RSTCTL, 0U); } @@ -1043,7 +1076,7 @@ fsp_err_t R_I3C_Write (i3c_ctrl_t * const p_api_ctrl, uint8_t const * const p_da /* * Write the descriptor to the command queue. * Note that the command descriptor is two words. The least significant word must be written first followed by - * the most significant word (See Section 25.3.1.1 in the RA2E2 manual R01UH0919EJ0100). + * the most significant word (See Section 25.3.1.1 in the hardware user manual R01UH0919EJ0100). */ uint32_t cmd1 = i3c_xfer_command_calculate(p_ctrl->device_index, false, p_ctrl->device_bitrate_mode, restart); @@ -1051,7 +1084,7 @@ fsp_err_t R_I3C_Write (i3c_ctrl_t * const p_api_ctrl, uint8_t const * const p_da if (length <= 4) { /* If the transfer length is less than or equal to 4 bytes, then use "Immediate Data Transfer". - * See section "25.3.1.1.2 Immediate Transfer Command" in the RA2E2 manual R01UH0919EJ0100. */ + * See section "25.3.1.1.2 Immediate Transfer Command" in the hardware user manual R01UH0919EJ0100. */ cmd1 |= I3C_CMD_DESC_CND_ATTR_IMMED_DATA_XFER; cmd1 |= (length << I3C_CMD_DESC_IMMED_DATA_XFER_BYTE_CNT_Pos); cmd2 = p_ctrl->next_word; @@ -1081,7 +1114,7 @@ fsp_err_t R_I3C_Write (i3c_ctrl_t * const p_api_ctrl, uint8_t const * const p_da * @retval FSP_ERR_ASSERTION An argument was NULL. * @retval FSP_ERR_NOT_OPEN This instance has not been opened yet. * @retval FSP_ERR_IN_USE The operation could not be completed because the driver is busy. - * @retval FSP_ERR_INVALID_MODE This driver is disabled. + * @retval FSP_ERR_INVALID_MODE This driver is disabled, or an invalid bitrate mode is selected. * @retval FSP_ERR_INVALID_ALIGNMENT The buffer must be aligned to 4 bytes and the length must be a multiple of * 4 bytes. **********************************************************************************************************************/ @@ -1109,6 +1142,14 @@ fsp_err_t R_I3C_Read (i3c_ctrl_t * const p_api_ctrl, uint8_t * const p_data, uin FSP_ERROR_RETURN(0U == ((uint32_t) length & 0x03U), FSP_ERR_INVALID_ALIGNMENT); } #endif + + #if BSP_FEATURE_I3C_HAS_HDR_MODE + if (I3C_INTERNAL_STATE_MASTER_IDLE == p_ctrl->internal_state) + { + /* In master mode, this function can only be called to start SDR and I2C transfers. */ + FSP_ERROR_RETURN(p_ctrl->device_bitrate_mode < I3C_BITRATE_MODE_I3C_HDR_DDR_STDBR, FSP_ERR_INVALID_MODE); + } + #endif #endif /* In Master mode, ensure that driver is in the idle state. */ @@ -1137,7 +1178,7 @@ fsp_err_t R_I3C_Read (i3c_ctrl_t * const p_api_ctrl, uint8_t * const p_data, uin /* * Write the descriptor to the command queue. * Note that the command descriptor is two words. The least significant word must be written first followed by - * the most significant word (See Section 25.3.1.1 in the RA2E2 manual R01UH0919EJ0100). + * the most significant word (See Section 25.3.1.1 in the hardware user manual R01UH0919EJ0100). */ p_ctrl->p_reg->NCMDQP = i3c_xfer_command_calculate(p_ctrl->device_index, true, @@ -1243,7 +1284,7 @@ fsp_err_t R_I3C_IbiWrite (i3c_ctrl_t * const p_api_ctrl, /* * Write the descriptor to the command queue. * Note that the command descriptor is two words. The least significant word must be written first followed by - * the most significant word (See Section 25.3.1.1 in the RA2E2 manual R01UH0919EJ0100). + * the most significant word (See Section 25.3.1.1 in the hardware user manual R01UH0919EJ0100). */ p_ctrl->p_reg->NCMDQP = command_descriptor; p_ctrl->p_reg->NCMDQP = (length << I3C_CMD_DESC_XFER_LENGTH_Pos) & I3C_CMD_DESC_XFER_LENGTH_Msk; @@ -1351,7 +1392,7 @@ fsp_err_t R_I3C_Close (i3c_ctrl_t * const p_api_ctrl) p_ctrl->p_reg->BCTL_b.BUSE = 0; p_ctrl->p_reg->RSTCTL = 1U; - /* The field will be cleared automatically upon reset completion (See section 25.2.5 in the RA2E2 manual R01UH0919EJ0100). */ + /* The field will be cleared automatically upon reset completion (See section 25.2.5 in the hardware user manual R01UH0919EJ0100). */ FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->RSTCTL, 0U); /* Set the I3C Module Stop bit. */ @@ -1557,10 +1598,11 @@ static inline uint32_t i3c_read_bytes_remaining_calculate (i3c_instance_ctrl_t * * then disable the transmit IRQ, and return. * * @param[in] p_ctrl Pointer to an instance's control structure. + * + * Note: this function must be inlined to reduce i3c_tx_isr processing time. **********************************************************************************************************************/ -static inline void i3c_fifo_write (i3c_instance_ctrl_t * p_ctrl) +BSP_FORCE_INLINE static inline void i3c_fifo_write (i3c_instance_ctrl_t * p_ctrl) { - bool transfer_complete = false; do { /* Write data to the transmit FIFO. */ @@ -1572,16 +1614,14 @@ static inline void i3c_fifo_write (i3c_instance_ctrl_t * p_ctrl) p_ctrl->p_reg->NTIE_b.TDBEIE0 = 0; i3c_extended_cfg_t * p_extend = (i3c_extended_cfg_t *) p_ctrl->p_cfg->p_extend; R_BSP_IrqClearPending(p_extend->tx_irq); - transfer_complete = true; - } - else - { - /* Calculate the next word of data to write to the FIFO. */ - p_ctrl->next_word = i3c_next_data_word_calculate(&p_ctrl->write_buffer_descriptor); + break; } + /* Calculate the next word of data to write to the FIFO. */ + p_ctrl->next_word = i3c_next_data_word_calculate(&p_ctrl->write_buffer_descriptor); + /* Continue writing data until the transmit FIFO is full. */ - } while ((p_ctrl->p_reg->NDBSTLV0 & UINT8_MAX) && !transfer_complete); + } while ((p_ctrl->p_reg->NDBSTLV0 & UINT8_MAX)); /* Clear the Transmit Buffer Empty status flag. */ p_ctrl->p_reg->NTST_b.TDBEF0 = 0; @@ -1591,8 +1631,11 @@ static inline void i3c_fifo_write (i3c_instance_ctrl_t * p_ctrl) * Compute the value of the next data word in a write transfer. * * @param[in] p_buffer_descriptor Pointer to a write buffer descriptor. + * + * Note: this function must be inlined to reduce i3c_tx_isr processing time. **********************************************************************************************************************/ -static inline uint32_t i3c_next_data_word_calculate (i3c_write_buffer_descriptor_t * p_buffer_descriptor) +BSP_FORCE_INLINE static inline uint32_t i3c_next_data_word_calculate ( + i3c_write_buffer_descriptor_t * p_buffer_descriptor) { uint32_t data_word = 0; @@ -1714,11 +1757,11 @@ void i3c_resp_isr (void) #if I3C_ERROR_RECOVERY_VERSION_1 == I3C_CFG_ERROR_RECOVERY_SUPPORT || \ I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT #if I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT - if (1U == I3C_A2E2_VERSION) + if ((1U == I3C_A2E2_VERSION) || (I3C_A2L2_VERSION_1 == I3C_A2E2_VERSION)) #endif { /* If the transfer length is less than expected, the driver must perform error recovery defined in - * Figure 25.96 in the RA2E2 manual R01UH0919EJ0100. */ + * Figure 25.96 in the hardware user manual R01UH0919EJ0100. */ if (data_length != p_ctrl->read_buffer_descriptor.buffer_size) { error_recovery_case_2 = true; @@ -1798,7 +1841,7 @@ void i3c_resp_isr (void) p_ctrl->p_reg->BCTL_b.ABT = 0; } - /* If a transfer error occurs, follow the error recovery operation defined in Figure 25.96 and 25.97 in the RA2E2 manual R01UH0919EJ0100. */ + /* If a transfer error occurs, follow the error recovery operation defined in Figure 25.96 and 25.97 in the hardware user manual R01UH0919EJ0100. */ if ((0 != (ntst & R_I3C0_NTST_TEF_Msk)) || error_recovery_case_2) { #if I3C_CFG_SLAVE_SUPPORT @@ -1987,7 +2030,7 @@ void i3c_rcv_isr (void) { /* * Perform dummy read. - * See 25.3.2.1 (2) I3C Slave Operation (b) Dynamic Address Assignment Procedure in the RA2E2 manual R01UH0919EJ0100. + * See 25.3.2.1 (2) I3C Slave Operation (b) Dynamic Address Assignment Procedure in the hardware user manual R01UH0919EJ0100. */ p_ctrl->p_reg->NTDTBP0; } @@ -2059,7 +2102,7 @@ void i3c_rcv_isr (void) uint32_t ntst = p_ctrl->p_reg->NTST; - /* If an error occurred during the transfer, perform the error recovery operation defined in Figure 25.97 in the RA2E2 manual R01UH0919EJ0100. */ + /* If an error occurred during the transfer, perform the error recovery operation defined in Figure 25.97 in the hardware user manual R01UH0919EJ0100. */ if ((0 != (ntst & (R_I3C0_NTST_TEF_Msk | R_I3C0_NTST_TABTF_Msk))) && (0U == p_ctrl->p_reg->NRSQSTLV_b.RSQLV)) { if (I3C_INTERNAL_STATE_SLAVE_IDLE == p_ctrl->internal_state) @@ -2202,7 +2245,7 @@ void i3c_ibi_isr (void) /*******************************************************************************************************************//** * ISR for providing the following events to the application: * - I3C_EVENT_INTERNAL_ERROR: An internal error can occur if too many transfers occur sequenctionally and overflow - * the Receive Status Queue (See 25.2.7 INST: Internal Status Register in the RA2E2 + * the Receive Status Queue (See 25.2.7 INST: Internal Status Register in the hardware user * manual R01UH0919EJ0100). * - I3C_EVENT_TIMEOUT_DETECTED * - I3C_EVENT_HDR_EXIT_PATTERN_DETECTED @@ -2268,7 +2311,7 @@ void i3c_eei_isr (void) #if I3C_CFG_MASTER_SUPPORT /*******************************************************************************************************************//** - * Perform error recovery according to Figure 25.96 in the RA2E2 manual R01UH0919EJ0100 + * Perform error recovery according to Figure 25.96 in the hardware user manual R01UH0919EJ0100 **********************************************************************************************************************/ void i3c_master_error_recovery (i3c_instance_ctrl_t * p_ctrl, bool error_recovery_case_2) { @@ -2277,14 +2320,14 @@ void i3c_master_error_recovery (i3c_instance_ctrl_t * p_ctrl, bool error_recover #if I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT /* For A2E2 version that has not been modified by ECO, the following error recovery procedure must be performed. - * See Figure 25.96 in the RA2E2 manual R01UH0919EJ0100. */ - if (1U == I3C_A2E2_VERSION) + * See Figure 25.96 in the hardware user manual R01UH0919EJ0100. */ + if ((1U == I3C_A2E2_VERSION) || (I3C_A2L2_VERSION_1 == I3C_A2E2_VERSION)) #endif { /* Flush the Command, Rx and Tx Buffers. */ p_ctrl->p_reg->RSTCTL = I3C_RSTCTRL_FIFO_FLUSH_Msk; - /* The field will be cleared automatically upon reset completion (See section 25.2.5 in the RA2E2 manual R01UH0919EJ0100). */ + /* The field will be cleared automatically upon reset completion (See section 25.2.5 in the hardware user manual R01UH0919EJ0100). */ FSP_HARDWARE_REGISTER_WAIT((p_ctrl->p_reg->RSTCTL & I3C_RSTCTRL_FIFO_FLUSH_Msk), 0U); /* Wait for the bus available condition. */ @@ -2413,7 +2456,7 @@ void i3c_master_error_recovery (i3c_instance_ctrl_t * p_ctrl, bool error_recover /* Flush the Command, Rx and Tx Buffers. */ p_ctrl->p_reg->RSTCTL = I3C_RSTCTRL_FIFO_FLUSH_Msk; - /* The field will be cleared automatically upon reset completion (See section 25.2.5 in the RA2E2 manual R01UH0919EJ0100). */ + /* The field will be cleared automatically upon reset completion (See section 25.2.5 in the hardware user manual R01UH0919EJ0100). */ FSP_HARDWARE_REGISTER_WAIT((p_ctrl->p_reg->RSTCTL & I3C_RSTCTRL_FIFO_FLUSH_Msk), 0U); /* Resume I3C operation. */ @@ -2427,7 +2470,7 @@ void i3c_master_error_recovery (i3c_instance_ctrl_t * p_ctrl, bool error_recover #if I3C_CFG_SLAVE_SUPPORT /*******************************************************************************************************************//** - * Perform error recovery according to Figure 25.97 in the RA2E2 manual R01UH0919EJ0100 + * Perform error recovery according to Figure 25.97 in the hardware user manual R01UH0919EJ0100 **********************************************************************************************************************/ void i3c_slave_error_recovery (i3c_instance_ctrl_t * p_ctrl, i3c_slave_error_recovery_type_t recovery_type) { @@ -2460,7 +2503,7 @@ void i3c_slave_error_recovery (i3c_instance_ctrl_t * p_ctrl, i3c_slave_error_rec } } - /* The field will be cleared automatically upon reset completion (See section 25.2.5 in the RA2E2 manual R01UH0919EJ0100). */ + /* The field will be cleared automatically upon reset completion (See section 25.2.5 in the hardware user manual R01UH0919EJ0100). */ FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->RSTCTL, 0U); #if I3C_ERROR_RECOVERY_VERSION_1 == I3C_CFG_ERROR_RECOVERY_SUPPORT || \ @@ -2468,14 +2511,14 @@ void i3c_slave_error_recovery (i3c_instance_ctrl_t * p_ctrl, i3c_slave_error_rec #if I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT /* For A2E2 version that has not been modified by ECO, the following error recovery procedure must be performed. - * See Figure 25.97 in the RA2E2 manual R01UH0919EJ0100. */ - if (1U == I3C_A2E2_VERSION) + * See Figure 25.97 in the hardware user manual R01UH0919EJ0100. */ + if ((1U == I3C_A2E2_VERSION) || (I3C_A2L2_VERSION_1 == I3C_A2E2_VERSION)) #endif { - /* Wait for Bus Available Condition (See Figure 25.97 in the RA2E2 manual R01UH0919EJ0100). */ + /* Wait for Bus Available Condition (See Figure 25.97 in the hardware user manual R01UH0919EJ0100). */ FSP_HARDWARE_REGISTER_WAIT((p_ctrl->p_reg->BCST & R_I3C0_BCST_BAVLF_Msk), R_I3C0_BCST_BAVLF_Msk); - /* Wait for start condition to be cleared (See Figure 25.97 in the RA2E2 manual R01UH0919EJ0100).. */ + /* Wait for start condition to be cleared (See Figure 25.97 in the hardware user manual R01UH0919EJ0100).. */ FSP_HARDWARE_REGISTER_WAIT((p_ctrl->p_reg->BST & R_I3C0_BST_STCNDDF_Msk), 0); /* Read the current value of SDDYAD. */ @@ -2503,7 +2546,7 @@ void i3c_slave_error_recovery (i3c_instance_ctrl_t * p_ctrl, i3c_slave_error_rec /* Perform internal software reset. */ p_ctrl->p_reg->RSTCTL = R_I3C0_RSTCTL_INTLRST_Msk; - /* Wait for Bus Available Condition (See Figure 25.97 in the RA2E2 manual R01UH0919EJ0100).. */ + /* Wait for Bus Available Condition (See Figure 25.97 in the hardware user manual R01UH0919EJ0100).. */ FSP_HARDWARE_REGISTER_WAIT((p_ctrl->p_reg->BCST & R_I3C0_BCST_BAVLF_Msk), R_I3C0_BCST_BAVLF_Msk); p_ctrl->p_reg->RSTCTL = 0; diff --git a/ra/fsp/src/r_icu/r_icu.c b/ra/fsp/src/r_icu/r_icu.c index 43928e36c..40c4082a9 100644 --- a/ra/fsp/src/r_icu/r_icu.c +++ b/ra/fsp/src/r_icu/r_icu.c @@ -24,6 +24,22 @@ #define ICU_FLTEN_OFFSET (7) #endif +/* If the mask is larger than 0xFFFF, then it requires 32-bit values instead of 16-bit */ +#if BSP_FEATURE_ICU_IRQ_CHANNELS_MASK > 0xFFFFU + +/* When mask is over 16-bit, there are actually two registers - R_ICU->IRQCRa and R_ICU->IRQCRb. Between them in memory + * is R_ICU->NMICR and means there is a 4 byte offset between the end of IRQCRa and beginning of IRQCRb. To save some + * instructions, this arithmetic determines if the 4 byte offset should be added to the indexing of IRQCRa to write to + * channels 16-31 */ + #define ICU_IRQCR_CH(c) ((c) + (uint8_t) (((c) >> 4) << 2)) + #define ICU_IRQCR_REG (R_ICU->IRQCRa) + #define ICU_IRQCR_REG_BITFIELD (R_ICU->IRQCRa_b) +#else + #define ICU_IRQCR_CH(c) (c) + #define ICU_IRQCR_REG (R_ICU->IRQCR) + #define ICU_IRQCR_REG_BITFIELD (R_ICU->IRQCR_b) +#endif + /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ @@ -102,7 +118,8 @@ fsp_err_t R_ICU_ExternalIrqOpen (external_irq_ctrl_t * const p_api_ctrl, externa FSP_ERR_UNSUPPORTED); #endif - FSP_ERROR_RETURN(0 != ((1U << p_cfg->channel) & BSP_FEATURE_ICU_IRQ_CHANNELS_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(0 != ((1ULL << p_cfg->channel) & BSP_FEATURE_ICU_IRQ_CHANNELS_MASK), + FSP_ERR_IP_CHANNEL_NOT_PRESENT); /* Callback must be used with a valid interrupt priority otherwise it will never be called. */ if (p_cfg->p_callback) @@ -132,10 +149,12 @@ fsp_err_t R_ICU_ExternalIrqOpen (external_irq_ctrl_t * const p_api_ctrl, externa p_ctrl->p_context = p_cfg->p_context; p_ctrl->channel = p_cfg->channel; + uint8_t channel = ICU_IRQCR_CH(p_ctrl->channel); + #if BSP_FEATURE_ICU_HAS_FILTER /* Disable digital filter */ - R_ICU->IRQCR[p_ctrl->channel] = 0U; + ICU_IRQCR_REG[channel] = 0U; /* Set the digital filter divider. */ uint8_t irqcr = (uint8_t) (p_cfg->clock_source_div << ICU_FCLKSEL_OFFSET); @@ -150,7 +169,7 @@ fsp_err_t R_ICU_ExternalIrqOpen (external_irq_ctrl_t * const p_api_ctrl, externa #endif /* Write IRQCR */ - R_ICU->IRQCR[p_ctrl->channel] = irqcr; + ICU_IRQCR_REG[channel] = irqcr; #if BSP_FEATURE_ICU_HAS_IELSR @@ -319,7 +338,11 @@ void r_icu_isr (void) #if BSP_FEATURE_ICU_HAS_IELSR bool level_irq = false; - if (EXTERNAL_IRQ_TRIG_LEVEL_LOW == R_ICU->IRQCR_b[p_ctrl->channel].IRQMD) + + uint8_t channel = ICU_IRQCR_CH(p_ctrl->channel); + uint8_t mode = ICU_IRQCR_REG_BITFIELD[channel].IRQMD; + + if (EXTERNAL_IRQ_TRIG_LEVEL_LOW == mode) { level_irq = true; } diff --git a/ra/fsp/src/r_iic_b_master/r_iic_b_master.c b/ra/fsp/src/r_iic_b_master/r_iic_b_master.c index 2ecea843b..2d8b3d5fe 100644 --- a/ra/fsp/src/r_iic_b_master/r_iic_b_master.c +++ b/ra/fsp/src/r_iic_b_master/r_iic_b_master.c @@ -773,12 +773,20 @@ static void iic_b_master_open_hw_master (iic_b_master_instance_ctrl_t * const p_ (uint32_t) (((iic_b_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)-> timeout_scl_low << R_I3C0_TMOCTL_TOLCTL_Pos)); - /* 1. Enable FM+ slope circuit if fast mode plus is enabled. + /* 1. Disable FM+ slope circuit * 2. Set Master Arbitration-Lost Detection Enable * 3. Set NACK Transmission Arbitration-Lost Detection Enable + * 4. Enable SMBus mode if requested */ - p_ctrl->p_reg->BFCTL = (((uint32_t) ((I2C_MASTER_RATE_FASTPLUS == p_ctrl->p_cfg->rate) << R_I3C0_BFCTL_FMPE_Pos)) | - R_I3C0_BFCTL_NALE_Msk | R_I3C0_BFCTL_MALE_Msk | R_I3C0_BFCTL_SCSYNE_Msk); + p_ctrl->p_reg->BFCTL = + (((uint32_t) (((iic_b_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->smbus_operation << + R_I3C0_BFCTL_SMBS_Pos)) | + ((uint32_t) ((I2C_MASTER_RATE_FASTPLUS == p_ctrl->p_cfg->rate) << R_I3C0_BFCTL_FMPE_Pos)) | + R_I3C0_BFCTL_NALE_Msk | R_I3C0_BFCTL_MALE_Msk | R_I3C0_BFCTL_SCSYNE_Msk); + + /* If SMBus is used, update OUTCTL to use SDA delay function */ + p_ctrl->p_reg->OUTCTL = (((uint32_t) (p_extend->clock_settings.sdod_value << R_I3C0_OUTCTL_SDOD_Pos)) | + ((uint32_t) (p_extend->clock_settings.sdodcs_value << R_I3C0_OUTCTL_SDODCS_Pos))); /* Enable status for Timeout Detection, Arbitration Loss, NACK Detection, Transmit End * Disable status for Wake-up Condition Detection (Feature not supported by driver), @@ -970,6 +978,11 @@ static void iic_b_master_rxi_master (iic_b_master_instance_ctrl_t * p_ctrl) } #endif + if (((iic_b_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_b_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } + /* Do a dummy read to clock the data into the NTDTBP0. */ dummy_read = p_ctrl->p_reg->NTDTBP0; FSP_PARAMETER_NOT_USED(dummy_read); @@ -990,6 +1003,11 @@ static void iic_b_master_rxi_master (iic_b_master_instance_ctrl_t * p_ctrl) /* NTDTBP0 contains valid received data */ else if (0U < p_ctrl->remain) { + if (((iic_b_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_b_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } + iic_b_master_rxi_read_data(p_ctrl); } else @@ -1014,6 +1032,19 @@ static void iic_b_master_txi_master (iic_b_master_instance_ctrl_t * p_ctrl) } else if (!p_ctrl->read) { + /* If previous event is an error event and this TXI is triggered by ERI, do not invoke SMBus callback. Because + * the internal function which used to issue callback will clear the error flag in the control block and cause + * incorrect behavior at ERI event after this TXI. + * + * Number of loaded byte must larger or equal to 1 because it helps to ensure that SMBus callback only be invoked + * after slave addess already transmitted (omit first 2 TDRE raise event). + */ + if ((((iic_b_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) && + ((!p_ctrl->err) && (0U < p_ctrl->loaded))) + { + iic_b_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } + #if IIC_B_MASTER_CFG_DTC_ENABLE /* If this is the interrupt that got fired after DTC transfer, @@ -1076,6 +1107,11 @@ static void iic_b_master_tei_master (iic_b_master_instance_ctrl_t * p_ctrl) { uint32_t timeout_count = IIC_B_MASTER_PERIPHERAL_REG_MAX_WAIT; + if (((iic_b_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_b_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } + /* This is a 10 bit address read, issue a restart prior to the last address byte transmission */ if ((p_ctrl->read) && (p_ctrl->addr_remain == 1U) && (false == p_ctrl->address_restarted)) { @@ -1250,6 +1286,13 @@ static void iic_b_master_err_master (iic_b_master_instance_ctrl_t * p_ctrl) * This is a request to read, send 3rd byte of 10-bit slave address. */ p_ctrl->p_reg->NTSTE = (uint32_t) IIC_B_MASTER_PRV_NTSTE_INIT_MASK; } + else if (errs_events & (uint8_t) R_I3C0_BST_STCNDDF_Msk) + { + if (((iic_b_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_b_master_notify(p_ctrl, I2C_MASTER_EVENT_START); + } + } else { /* Do nothing */ diff --git a/ra/fsp/src/r_iic_master/r_iic_master.c b/ra/fsp/src/r_iic_master/r_iic_master.c index aedfe234f..620641eb7 100644 --- a/ra/fsp/src/r_iic_master/r_iic_master.c +++ b/ra/fsp/src/r_iic_master/r_iic_master.c @@ -226,9 +226,6 @@ fsp_err_t R_IIC_MASTER_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cf FSP_ASSERT((BSP_FEATURE_IIC_FAST_MODE_PLUS & (1U << p_cfg->channel))); } #endif -#if IIC_MASTER_CFG_DTC_ENABLE - fsp_err_t err = FSP_SUCCESS; -#endif p_ctrl->p_reg = (R_IIC0_Type *) ((uint32_t) R_IIC0 + (p_cfg->channel * ((uint32_t) R_IIC1 - (uint32_t) R_IIC0))); @@ -249,7 +246,7 @@ fsp_err_t R_IIC_MASTER_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cf #if IIC_MASTER_CFG_DTC_ENABLE /* Open the IIC transfer interface if available */ - err = iic_master_transfer_open(p_cfg); + fsp_err_t err = iic_master_transfer_open(p_cfg); if (FSP_SUCCESS != err) { R_BSP_MODULE_STOP(FSP_IP_IIC, p_cfg->channel); @@ -809,8 +806,8 @@ static void iic_master_open_hw_master (iic_master_instance_ctrl_t * const p_ctrl * * @param[in] p_ctrl Pointer to control structure of specific device. * - * @retval FSP_SUCCESS Data transfer success. - * @retval FSP_ERR_IN_USE If data transfer is in progress. + * @retval FSP_SUCCESS Data transfer success. + * @retval FSP_ERR_IN_USE If data transfer is in progress. **********************************************************************************************************************/ static fsp_err_t iic_master_run_hw_master (iic_master_instance_ctrl_t * const p_ctrl) { @@ -863,21 +860,31 @@ static fsp_err_t iic_master_run_hw_master (iic_master_instance_ctrl_t * const p_ /* TMOL 'Timeout L Count Control' and TMOH 'Timeout H Count Control' will be set at the time of I2C reset. * This will enable time out detection for both SCLn high and low. - * Only Set/Clear TMOS here to select long or short mode. + * + * Register configuration: + * - Set/Clear TMOS here to select long or short mode. * (see Section 36.2.4 'I2C Bus Mode Register 2 (ICMR2)' of the RA6M3 manual R01UH0886EJ0100). + * - Set SDDL and DLCS. If SMBus is disabled, assign default value. */ + iic_master_extended_cfg_t * p_extend = (iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + p_ctrl->p_reg->ICMR2 = (uint8_t) (IIC_MASTER_BUS_MODE_REGISTER_2_MASK | - (uint8_t) (IIC_MASTER_TIMEOUT_MODE_SHORT == - ((iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->timeout_mode) + (uint8_t) (IIC_MASTER_TIMEOUT_MODE_SHORT == (p_extend->timeout_mode)) | - (uint8_t) (((iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)-> - timeout_scl_low << R_IIC0_ICMR2_TMOL_Pos)); + (uint8_t) (p_extend->timeout_scl_low << R_IIC0_ICMR2_TMOL_Pos) + | + (uint8_t) (p_extend->clock_settings.sddl_value << R_IIC0_ICMR2_SDDL_Pos) + | + (uint8_t) (p_extend->clock_settings.dlcs_value << R_IIC0_ICMR2_DLCS_Pos)); /* Set the response as ACK */ p_ctrl->p_reg->ICMR3_b.ACKWP = 1; /* Write Enable */ p_ctrl->p_reg->ICMR3_b.ACKBT = 0; /* Write */ p_ctrl->p_reg->ICMR3_b.ACKWP = 0; + /* Enable SMBus communication for I2C module if requested */ + p_ctrl->p_reg->ICMR3_b.SMBS = p_extend->smbus_operation; + /* Enable timeout function */ p_ctrl->p_reg->ICFER_b.TMOE = 1U; @@ -968,6 +975,10 @@ static void iic_master_rxi_master (iic_master_instance_ctrl_t * p_ctrl) p_ctrl->activation_on_rxi = true; } #endif + if (((iic_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } /* Do a dummy read to clock the data into the ICDRR. */ dummy_read = p_ctrl->p_reg->ICDRR; @@ -990,6 +1001,11 @@ static void iic_master_rxi_master (iic_master_instance_ctrl_t * p_ctrl) /* ICDRR contain valid received data */ else if (0U < p_ctrl->remain) { + if (((iic_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } + iic_master_rxi_read_data(p_ctrl); } else @@ -1014,6 +1030,19 @@ static void iic_master_txi_master (iic_master_instance_ctrl_t * p_ctrl) } else if (!p_ctrl->read) { + /* If previous event is an error event and this TXI is triggered by ERI, do not invoke SMBus callback. Because + * the internal function which used to issue callback will clear the error flag in the control block and cause + * incorrect behavior at ERI event after this TXI. + * + * Number of loaded byte must larger or equal to 1 because it helps to ensure that SMBus callback only be invoked + * after slave addess already transmitted (omit first 2 TDRE raise event). + */ + if ((((iic_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) && + ((!p_ctrl->err) && (0U < p_ctrl->loaded))) + { + iic_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } + #if IIC_MASTER_CFG_DTC_ENABLE /* If this is the interrupt that got fired after DTC transfer, @@ -1042,6 +1071,7 @@ static void iic_master_txi_master (iic_master_instance_ctrl_t * p_ctrl) /* We are done loading ICDRT, wait for TEND to send a stop/restart */ if (0U == p_ctrl->remain) { + /* Disable the Transmit Data Empty Interrupt. */ p_ctrl->p_reg->ICIER_b.TIE = 0U; /* Wait for the value to reflect at the peripheral. @@ -1076,6 +1106,11 @@ static void iic_master_tei_master (iic_master_instance_ctrl_t * p_ctrl) { uint32_t timeout_count = IIC_MASTER_PERIPHERAL_REG_MAX_WAIT; + if (((iic_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } + /* This is a 10 bit address read, issue a restart prior to the last address byte transmission */ if ((p_ctrl->read) && (p_ctrl->addr_remain == 1U) && (false == p_ctrl->address_restarted)) { @@ -1116,7 +1151,7 @@ static void iic_master_tei_master (iic_master_instance_ctrl_t * p_ctrl) /* Clear STOP flag and set SP. * It is ok to clear other status' as this transaction is over. */ - p_ctrl->p_reg->ICSR2 &= (uint8_t) ~(IIC_MASTER_ICSR2_STOP_BIT);; + p_ctrl->p_reg->ICSR2 &= (uint8_t) ~(IIC_MASTER_ICSR2_STOP_BIT); /* Request IIC to issue the stop condition */ p_ctrl->p_reg->ICCR2 = (uint8_t) IIC_MASTER_ICCR2_SP_BIT_MASK; /* It is safe to write 0's to other bits. */ @@ -1184,10 +1219,16 @@ static void iic_master_err_master (iic_master_instance_ctrl_t * p_ctrl) /* Request IIC to issue the stop condition */ p_ctrl->p_reg->ICCR2 = (uint8_t) IIC_MASTER_ICCR2_SP_BIT_MASK; /* It is safe to write 0's to other bits. */ - /* Allow timeouts to be generated on the low value of SCL using either long or short mode */ + + /* Allow timeouts to be generated on the low value of SCL using either long or short mode and re-assign value + * of SDDL and DLCS. */ p_ctrl->p_reg->ICMR2 = (uint8_t) 0x02U | - (uint8_t) (IIC_MASTER_TIMEOUT_MODE_SHORT == - ((iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->timeout_mode); + (uint8_t) (((iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->timeout_mode) | + (uint8_t) (((iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)-> + clock_settings.sddl_value << R_IIC0_ICMR2_SDDL_Pos) + | + (uint8_t) (((iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)-> + clock_settings.dlcs_value << R_IIC0_ICMR2_DLCS_Pos); p_ctrl->p_reg->ICFER_b.TMOE = 1; /* This interrupt will be fired again when wither stop condition is sent @@ -1225,6 +1266,13 @@ static void iic_master_err_master (iic_master_instance_ctrl_t * p_ctrl) /* Notify anyone waiting */ iic_master_notify(p_ctrl, event); } + else if (errs_events & (uint8_t) IIC_MASTER_ERR_EVENT_START) + { + if (((iic_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_master_notify(p_ctrl, I2C_MASTER_EVENT_START); + } + } else { /* Do nothing */ @@ -1286,7 +1334,7 @@ static void iic_master_rxi_read_data (iic_master_instance_ctrl_t * const p_ctrl) /* Clear STOP flag and set SP. * It is ok to clear other status' as this transaction is over. */ - p_ctrl->p_reg->ICSR2 &= (uint8_t) ~(IIC_MASTER_ICSR2_STOP_BIT);; + p_ctrl->p_reg->ICSR2 &= (uint8_t) ~(IIC_MASTER_ICSR2_STOP_BIT); /* Request IIC to issue the stop condition */ p_ctrl->p_reg->ICCR2 = (uint8_t) IIC_MASTER_ICCR2_SP_BIT_MASK; /* It is safe to write 0's to other bits. */ diff --git a/ra/fsp/src/r_iica_master/r_iica_master.c b/ra/fsp/src/r_iica_master/r_iica_master.c index 7996cbc02..a67bf84e5 100644 --- a/ra/fsp/src/r_iica_master/r_iica_master.c +++ b/ra/fsp/src/r_iica_master/r_iica_master.c @@ -253,7 +253,7 @@ fsp_err_t R_IICA_MASTER_SlaveAddressSet (i2c_master_ctrl_t * const p_api_ctrl FSP_ERROR_RETURN(IICA_MASTER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); /* Fail if there is already a transfer in progress */ - FSP_ERROR_RETURN(((0 == p_ctrl->loaded) && (0 == p_ctrl->total) && (false == p_ctrl->restart)), FSP_ERR_IN_USE); + FSP_ERROR_RETURN(((p_ctrl->loaded == p_ctrl->total) && (false == p_ctrl->restart)), FSP_ERR_IN_USE); #if !IICA_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE FSP_ERROR_RETURN(p_ctrl->addr_mode != I2C_MASTER_ADDR_MODE_10BIT, FSP_ERR_INVALID_MODE); #endif diff --git a/ra/fsp/src/r_iica_slave/r_iica_slave.c b/ra/fsp/src/r_iica_slave/r_iica_slave.c index afe72a96f..d0eddb380 100644 --- a/ra/fsp/src/r_iica_slave/r_iica_slave.c +++ b/ra/fsp/src/r_iica_slave/r_iica_slave.c @@ -412,7 +412,8 @@ static void r_iica_txrxi_slave (iica_slave_instance_ctrl_t * p_ctrl) if (0U == p_ctrl->communication_dir) { #if IICA_SLAVE_CFG_ADDR_MODE_GENERAL_CALL_ENABLE - r_iica_slave_call_callback(p_ctrl, I2C_SLAVE_EVENT_GENERAL_CALL); + i2c_slave_event_t i2c_event = R_IICA->IICA0 ? I2C_SLAVE_EVENT_RX_REQUEST : I2C_SLAVE_EVENT_GENERAL_CALL; + r_iica_slave_call_callback(p_ctrl, i2c_event); #else r_iica_slave_call_callback(p_ctrl, I2C_SLAVE_EVENT_RX_REQUEST); #endif diff --git a/ra/fsp/src/r_lpm/r_lpm.c b/ra/fsp/src/r_lpm/r_lpm.c index 8e04303a5..d85085285 100644 --- a/ra/fsp/src/r_lpm/r_lpm.c +++ b/ra/fsp/src/r_lpm/r_lpm.c @@ -241,7 +241,7 @@ fsp_err_t R_LPM_LowPowerModeEnter (lpm_ctrl_t * const p_api_ctrl) } #endif #endif -#if BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST == 1 +#if BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST == 1 uint8_t saved_dtcst = 0; #endif @@ -262,24 +262,17 @@ fsp_err_t R_LPM_LowPowerModeEnter (lpm_ctrl_t * const p_api_ctrl) } #endif #endif -#if BSP_FEATURE_LPM_HAS_SNOOZE - if (LPM_MODE_STANDBY_SNOOZE == p_ctrl->p_cfg->low_power_mode) - { - /* Configure Snooze registers */ - #if BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST == 1 - if (!p_ctrl->p_cfg->dtc_state_in_snooze) - { - #if LPM_CFG_PARAM_CHECKING_ENABLE - FSP_ERROR_RETURN(0 == R_MSTP->MSTPCRA_b.MSTPA22, FSP_ERR_INVALID_MODE); - #endif - /* Store the previous state of DTCST. */ - saved_dtcst = R_DTC->DTCST; +#if BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST == 1 + if (((LPM_MODE_STANDBY == p_ctrl->p_cfg->low_power_mode) || + ((LPM_MODE_STANDBY_SNOOZE == p_ctrl->p_cfg->low_power_mode) && !p_ctrl->p_cfg->dtc_state_in_snooze)) && + (0 == R_MSTP->MSTPCRA_b.MSTPA22)) + { + /* Store the previous state of DTCST. */ + saved_dtcst = R_DTC->DTCST; - /* If snooze mode does not use DTC, DTC should be stopped before entering snooze mode. */ - R_DTC->DTCST = 0U; - } - #endif + /* If DTC is not used for requesting snooze mode, it should be stopped before entering standby or snooze mode. */ + R_DTC->DTCST = 0U; } #endif fsp_err_t err = r_lpm_low_power_enter(p_ctrl); @@ -298,16 +291,13 @@ fsp_err_t R_LPM_LowPowerModeEnter (lpm_ctrl_t * const p_api_ctrl) } #endif #endif -#if BSP_FEATURE_LPM_HAS_SNOOZE - if (LPM_MODE_STANDBY_SNOOZE == p_ctrl->p_cfg->low_power_mode) +#if BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST == 1 + if (((LPM_MODE_STANDBY == p_ctrl->p_cfg->low_power_mode) || + ((LPM_MODE_STANDBY_SNOOZE == p_ctrl->p_cfg->low_power_mode) && !p_ctrl->p_cfg->dtc_state_in_snooze)) && + (0 == R_MSTP->MSTPCRA_b.MSTPA22)) { - #if BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST == 1 - if (!p_ctrl->p_cfg->dtc_state_in_snooze) - { - /* If DTC was stopped prior to entering snooze mode, then start it again. */ - R_DTC->DTCST = saved_dtcst; - } - #endif + /* If DTC was stopped prior to entering standby or snooze mode, then start it again. */ + R_DTC->DTCST = saved_dtcst; } #endif @@ -408,7 +398,7 @@ fsp_err_t r_lpm_mcu_specific_low_power_check (lpm_cfg_t const * const p_cfg) if (LPM_MODE_STANDBY_SNOOZE == p_cfg->low_power_mode) { #if BSP_FEATURE_LPM_HAS_SNOOZE - #if BSP_FEATURE_LPM_SNZREQCR_MASK + #if BSP_FEATURE_LPM_SNZREQCR_MASK > 0 FSP_ERROR_RETURN(0U == ((uint64_t) p_cfg->snooze_request_source & (~BSP_FEATURE_LPM_SNZREQCR_MASK)), FSP_ERR_INVALID_ARGUMENT); #endif @@ -449,7 +439,7 @@ fsp_err_t r_lpm_mcu_specific_low_power_check (lpm_cfg_t const * const p_cfg) FSP_ERROR_RETURN(0U == ((uint64_t) p_cfg->standby_wake_sources & ~BSP_FEATURE_ICU_WUPEN_MASK), FSP_ERR_INVALID_MODE); #endif - #if BSP_FEATURE_ICU_SBYEDCR_MASK + #if BSP_FEATURE_ICU_SBYEDCR_MASK > 0 FSP_ERROR_RETURN(0U == ((uint64_t) p_cfg->standby_wake_sources & ~BSP_FEATURE_ICU_SBYEDCR_MASK), FSP_ERR_INVALID_MODE); #endif @@ -1003,6 +993,12 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) } #endif +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + + /* Disable RTC Register Read/Write Clock to reduce power consumption. */ + bool rtc_register_clock_state = bsp_prv_rtc_register_clock_set(false); +#endif + #if BSP_CFG_SLEEP_MODE_DELAY_ENABLE bool clock_slowed = bsp_prv_clock_prepare_pre_sleep(); #endif @@ -1017,6 +1013,12 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) bsp_prv_clock_prepare_post_sleep(clock_slowed); #endif +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + + /* Enable the RTC Register Read/Write clock if it was disabled prior to entering LPM. */ + bsp_prv_rtc_register_clock_set(rtc_register_clock_state); +#endif + #if BSP_FEATURE_LPM_HAS_DEEP_SLEEP if (LPM_MODE_SLEEP != p_instance_ctrl->p_cfg->low_power_mode) { diff --git a/ra/fsp/src/r_lvd/r_lvd.c b/ra/fsp/src/r_lvd/r_lvd.c index 28c041eee..95f628410 100644 --- a/ra/fsp/src/r_lvd/r_lvd.c +++ b/ra/fsp/src/r_lvd/r_lvd.c @@ -524,7 +524,7 @@ fsp_err_t R_LVD_Close (lvd_ctrl_t * const p_api_ctrl) } /*******************************************************************************************************************//** - * @} (end addtogroup LVD) + * @} (end addtogroup LVD-PVD) **********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/inc/api/r_rsip_api.h b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/inc/api/r_rsip_api.h similarity index 92% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/inc/api/r_rsip_api.h rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/inc/api/r_rsip_api.h index a4c7a2685..2c8ae7995 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/inc/api/r_rsip_api.h +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/inc/api/r_rsip_api.h @@ -38,59 +38,50 @@ FSP_HEADER #define RSIP_PRV_KEY_PAIR_TYPE(pub_alg, priv_alg, subtype) (((pub_alg) << 16) + ((priv_alg) << 8) + (subtype)) #define RSIP_PRV_KEY_SIZE(key_value_size) (4U + (key_value_size)) +/* Internal algorithm ID */ +#define RSIP_ALG_INVALID (0x00) +#define RSIP_ALG_AES (0x10) +#define RSIP_ALG_XTS_AES (0x11) +#define RSIP_ALG_CHACHA (0x12) +#define RSIP_ALG_ECC_PUBLIC (0x20) +#define RSIP_ALG_ECC_PRIVATE (0x21) +#define RSIP_ALG_RSA_PUBLIC (0x22) +#define RSIP_ALG_RSA_PRIVATE (0x23) +#define RSIP_ALG_HMAC (0x30) + +/* Internal key ID */ +#define RSIP_KEY_INVALID (0x00) +#define RSIP_KEY_AES_128 (0x00) +#define RSIP_KEY_AES_192 (0x01) +#define RSIP_KEY_AES_256 (0x02) +#define RSIP_KEY_AES_NUM (0x03) +#define RSIP_KEY_CHACHA_CHACHA20 (0x00) +#define RSIP_KEY_CHACHA_NUM (0x01) +#define RSIP_KEY_ECC_SECP256R1 (0x02) +#define RSIP_KEY_ECC_SECP384R1 (0x03) +#define RSIP_KEY_ECC_SECP521R1 (0x04) +#define RSIP_KEY_ECC_SECP256K1 (0x07) +#define RSIP_KEY_ECC_BRAINPOOLP256R1 (0x0a) +#define RSIP_KEY_ECC_BRAINPOOLP384R1 (0x0c) +#define RSIP_KEY_ECC_BRAINPOOLP512R1 (0x0d) +#define RSIP_KEY_ECC_EDWARDS25519 (0x0e) +#define RSIP_KEY_ECC_NUM (0x0f) +#define RSIP_KEY_RSA_1024 (0x00) +#define RSIP_KEY_RSA_2048 (0x01) +#define RSIP_KEY_RSA_3072 (0x02) +#define RSIP_KEY_RSA_4096 (0x03) +#define RSIP_KEY_RSA_NUM (0x04) +#define RSIP_KEY_HMAC_SHA1 (0x00) +#define RSIP_KEY_HMAC_SHA224 (0x01) +#define RSIP_KEY_HMAC_SHA256 (0x02) +#define RSIP_KEY_HMAC_SHA384 (0x03) +#define RSIP_KEY_HMAC_SHA512 (0x04) +#define RSIP_KEY_HMAC_NUM (0x05) + /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ -/** Key algorithms */ -typedef enum e_rsip_alg -{ - RSIP_ALG_INVALID = 0x00, ///< Invalid - RSIP_ALG_AES = 0x10, ///< AES - RSIP_ALG_XTS_AES = 0x11, ///< XTS-AES - RSIP_ALG_CHACHA = 0x12, ///< ChaCha - RSIP_ALG_ECC_PUBLIC = 0x20, ///< ECC public key - RSIP_ALG_ECC_PRIVATE = 0x21, ///< ECC private key - RSIP_ALG_RSA_PUBLIC = 0x22, ///< RSA public key - RSIP_ALG_RSA_PRIVATE = 0x23, ///< RSA private key - RSIP_ALG_HMAC = 0x30, ///< HMAC -} rsip_alg_t; - -/** Key sub type */ -typedef enum e_rsip_key_subtype -{ - RSIP_KEY_INVALID = 0x00, ///< Invalid key - - RSIP_KEY_AES_128 = 0x00, ///< AES-128 - RSIP_KEY_AES_192 = 0x01, ///< AES-192 - RSIP_KEY_AES_256 = 0x02, ///< AES-256 - RSIP_KEY_AES_NUM, // Number of subtypes - - RSIP_KEY_CHACHA_CHACHA20 = 0x00, ///< ChaCha20 - RSIP_KEY_CHACHA_NUM, // Number of subtypes - - RSIP_KEY_ECC_SECP256R1 = 0x02, ///< secp256r1 - RSIP_KEY_ECC_SECP384R1 = 0x03, ///< secp384r1 - RSIP_KEY_ECC_SECP521R1 = 0x04, ///< secp521r1 - RSIP_KEY_ECC_SECP256K1 = 0x07, ///< secp256k1 - RSIP_KEY_ECC_BRAINPOOLP256R1 = 0x0a, ///< brainpoolP256r1 - RSIP_KEY_ECC_BRAINPOOLP384R1 = 0x0c, ///< brainpoolP384r1 - RSIP_KEY_ECC_BRAINPOOLP512R1 = 0x0d, ///< brainpoolP512r1 - RSIP_KEY_ECC_EDWARDS25519 = 0x0e, ///< edwards25519 - RSIP_KEY_ECC_NUM, // Number of subtypes - - RSIP_KEY_RSA_1024 = 0x00, ///< RSA-1024 - RSIP_KEY_RSA_2048 = 0x01, ///< RSA-2048 - RSIP_KEY_RSA_3072 = 0x02, ///< RSA-3072 - RSIP_KEY_RSA_4096 = 0x03, ///< RSA-4096 - RSIP_KEY_RSA_NUM, // Number of subtypes - - RSIP_KEY_HMAC_SHA1 = 0x00, ///< HMAC-SHA1 - RSIP_KEY_HMAC_SHA224 = 0x01, ///< HMAC-SHA224 - RSIP_KEY_HMAC_SHA256 = 0x02, ///< HMAC-SHA256 - RSIP_KEY_HMAC_NUM, // Number of subtypes -} rsip_key_subtype_t; - /** Key types */ typedef enum e_rsip_key_type { @@ -128,6 +119,8 @@ typedef enum e_rsip_key_type RSIP_KEY_TYPE_HMAC_SHA1 = RSIP_PRV_KEY_TYPE(RSIP_ALG_HMAC, RSIP_KEY_HMAC_SHA1), ///< HMAC-SHA1 RSIP_KEY_TYPE_HMAC_SHA224 = RSIP_PRV_KEY_TYPE(RSIP_ALG_HMAC, RSIP_KEY_HMAC_SHA224), ///< HMAC-SHA224 RSIP_KEY_TYPE_HMAC_SHA256 = RSIP_PRV_KEY_TYPE(RSIP_ALG_HMAC, RSIP_KEY_HMAC_SHA256), ///< HMAC-SHA256 + RSIP_KEY_TYPE_HMAC_SHA384 = RSIP_PRV_KEY_TYPE(RSIP_ALG_HMAC, RSIP_KEY_HMAC_SHA384), ///< HMAC-SHA384 + RSIP_KEY_TYPE_HMAC_SHA512 = RSIP_PRV_KEY_TYPE(RSIP_ALG_HMAC, RSIP_KEY_HMAC_SHA512), ///< HMAC-SHA512 } rsip_key_type_t; /** Key pair types */ @@ -227,27 +220,31 @@ typedef enum e_rsip_byte_size_wrapped_key RSIP_PRV_KEY_SIZE(RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_HMAC_SHA224), ///< HMAC-SHA224 private key RSIP_BYTE_SIZE_WRAPPED_KEY_HMAC_SHA256 = RSIP_PRV_KEY_SIZE(RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_HMAC_SHA256), ///< HMAC-SHA256 private key + RSIP_BYTE_SIZE_WRAPPED_KEY_HMAC_SHA384 = + RSIP_PRV_KEY_SIZE(RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_HMAC_SHA384), ///< HMAC-SHA384 private key + RSIP_BYTE_SIZE_WRAPPED_KEY_HMAC_SHA512 = + RSIP_PRV_KEY_SIZE(RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_HMAC_SHA512), ///< HMAC-SHA512 private key } rsip_byte_size_wrapped_key_t; /** Block cipher modes of operation for AES */ typedef enum e_rsip_aes_cipher_mode { - RSIP_AES_CIPHER_MODE_ECB_ENC, ///< Electronic Codebook (ECB) encryption - RSIP_AES_CIPHER_MODE_ECB_DEC, ///< Electronic Codebook (ECB) decryption - RSIP_AES_CIPHER_MODE_CBC_ENC, ///< Cipher Block Chaining (CBC) mode encryption - RSIP_AES_CIPHER_MODE_CBC_DEC, ///< Cipher Block Chaining (CBC) mode decryption - RSIP_AES_CIPHER_MODE_CTR, ///< Counter (CTR) encryption and decryption - RSIP_AES_CIPHER_MODE_XTS_ENC, ///< XEX-based tweaked-codebook mode with ciphertext stealing (XTS) encryption - RSIP_AES_CIPHER_MODE_XTS_DEC, ///< XEX-based tweaked-codebook mode with ciphertext stealing (XTS) decryption + RSIP_AES_CIPHER_MODE_ECB_ENC, ///< Electronic Codebook (ECB) mode encryption + RSIP_AES_CIPHER_MODE_ECB_DEC, ///< Electronic Codebook (ECB) mode decryption + RSIP_AES_CIPHER_MODE_CBC_ENC, ///< Cipher Block Chaining (CBC) mode encryption + RSIP_AES_CIPHER_MODE_CBC_DEC, ///< Cipher Block Chaining (CBC) mode decryption + RSIP_AES_CIPHER_MODE_CTR, ///< Counter (CTR) mode encryption or decryption + RSIP_AES_CIPHER_MODE_XTS_ENC, ///< XEX-based tweaked-codebook mode with ciphertext stealing (XTS) encryption + RSIP_AES_CIPHER_MODE_XTS_DEC, ///< XEX-based tweaked-codebook mode with ciphertext stealing (XTS) decryption } rsip_aes_cipher_mode_t; /** AEAD modes of operation for AES */ typedef enum e_rsip_aes_aead_mode { - RSIP_AES_AEAD_MODE_GCM_ENC, ///< Galois/Counter Mode (GCM) encryption - RSIP_AES_AEAD_MODE_GCM_DEC, ///< Galois/Counter Mode (GCM) decryption - RSIP_AES_AEAD_MODE_CCM_ENC, ///< Counter with CBC-MAC (CCM) encryption - RSIP_AES_AEAD_MODE_CCM_DEC, ///< Counter with CBC-MAC (CCM) decryption + RSIP_AES_AEAD_MODE_GCM_ENC, ///< Galois/Counter Mode (GCM) encryption + RSIP_AES_AEAD_MODE_GCM_DEC, ///< Galois/Counter Mode (GCM) decryption + RSIP_AES_AEAD_MODE_CCM_ENC, ///< Counter with CBC-MAC (CCM) encryption + RSIP_AES_AEAD_MODE_CCM_DEC, ///< Counter with CBC-MAC (CCM) decryption } rsip_aes_aead_mode_t; /** MAC modes of operation for AES */ @@ -305,14 +302,14 @@ typedef enum e_rsip_otf_channel RSIP_OTF_CHANNEL_NUM // Number of OTF channel } rsip_otf_channel_t; -/** Wrapped key structure for all supported algorithms. The struct length of each algorithm is defined by RSIP_BYTE_SIZE_WRAPPED_KEY macro. */ +/** Wrapped key structure for all supported algorithms. The struct length of each algorithm is defined in @ref rsip_byte_size_wrapped_key_t. */ typedef struct st_rsip_wrapped_key { - uint8_t alg; ///< Key algorithm - uint8_t subtype; ///< Key sub type - uint8_t info[2]; ///< Reserved area + uint8_t alg; // Internal algorithm ID + uint8_t subtype; // Internal key type ID + uint8_t info[2]; // Reserved area - uint8_t value[]; ///< Variable length array to store the key value + uint8_t value[]; // Variable length array to store the key value } rsip_wrapped_key_t; /** Key Update Key (KUK) */ @@ -465,10 +462,8 @@ typedef struct st_rsip_api * @param[in] wrapped_key_buffer_length Length of p_wrapped_key destination. * It must be equal to or greater than actual wrapped key. */ - fsp_err_t (* injectedKeyImport)(rsip_key_type_t const key_type, - uint8_t const * const p_injected_key, - rsip_wrapped_key_t * const p_wrapped_key, - uint32_t const wrapped_key_buffer_length); + fsp_err_t (* injectedKeyImport)(rsip_key_type_t const key_type, uint8_t const * const p_injected_key, + rsip_wrapped_key_t * const p_wrapped_key, uint32_t const wrapped_key_buffer_length); /** * Exports public key parameters from a wrapped key. @@ -550,7 +545,7 @@ typedef struct st_rsip_api /** * Inputs test and executes encryption and decryption. - * + * * @param[in,out] p_ctrl Pointer to control block. * @param[in] p_input Pointer to input text. The length is input_length. * @param[in] input_length Byte length of input text (0 or more bytes). @@ -589,7 +584,7 @@ typedef struct st_rsip_api * @param[in,out] p_ctrl Pointer to control block. * @param[out] p_output Pointer to destination of decrypted data. * @param[out] p_output_length Pointer to destination of decrypted data length. - * @param[in] p_tag Pointer to destination of tag for authentication.The length depends on tag_length. + * @param[in] p_tag Pointer to destination of tag for authentication. The length depends on tag_length. * @param[in] tag_length Byte length of tag. Must be 1 to 16. */ fsp_err_t (* aesAeadVerify)(rsip_ctrl_t * const p_ctrl, uint8_t * const p_output, uint32_t * const p_output_length, @@ -652,7 +647,7 @@ typedef struct st_rsip_api * @param[in,out] p_ctrl Pointer to control block. * @param[in] p_wrapped_public_key Pointer to wrapped key of ECC public key. * @param[in] p_hash Pointer to hash value. The length is as same as the key length. - * @param[in] p_signature Pointer to signature (r, s).The length is twice as long as the key length. + * @param[in] p_signature Pointer to signature (r, s). The length is twice as long as the key length. */ fsp_err_t (* ecdsaVerify)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_public_key, uint8_t const * const p_hash, uint8_t const * const p_signature); @@ -829,7 +824,7 @@ typedef struct st_rsip_api /** * Inputs message. - * + * * @param[in,out] p_ctrl Pointer to control block. * @param[in] p_message Pointer to message. The length is message_length. * @param[in] message_length Byte length of message (0 or more bytes). @@ -855,7 +850,7 @@ typedef struct st_rsip_api /** * Resume SHA generation. - * This API allows you to resume a process that has been suspended by R_RSIP_SHA_Suspend() API. + * This API allows you to resume a process that has been suspended by R_RSIP_SHA_Suspend() API. * * @param[in,out] p_ctrl Pointer to control block. * @param[in] p_handle Pointer to SHA control block. diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/common/r_rsip_err.h b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_err.h similarity index 95% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/common/r_rsip_err.h rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_err.h index 4dcfdd238..20722bf9d 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/common/r_rsip_err.h +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_err.h @@ -11,7 +11,7 @@ * Typedef definitions **********************************************************************************************************************/ -/* Return code */ +/** Return code of internal function */ typedef enum e_rsip_ret { /* Success */ diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/common/r_rsip_reg.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_reg.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/common/r_rsip_reg.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_reg.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/common/r_rsip_reg.h b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_reg.h similarity index 99% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/common/r_rsip_reg.h rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_reg.h index cdd1f8774..ff7ccd15a 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/common/r_rsip_reg.h +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_reg.h @@ -12,7 +12,6 @@ **********************************************************************************************************************/ #include #include "r_rsip_addr.h" -#include "r_rsip_util.h" /*********************************************************************************************************************** * Macro definitions @@ -108,6 +107,40 @@ RD1_ADDR((reg), (&(addr)[6])); \ RD1_ADDR((reg), (&(addr)[7])); \ } +#define RD12_ADDR(reg, addr) \ + { \ + RD1_ADDR((reg), (&(addr)[0])); \ + RD1_ADDR((reg), (&(addr)[1])); \ + RD1_ADDR((reg), (&(addr)[2])); \ + RD1_ADDR((reg), (&(addr)[3])); \ + RD1_ADDR((reg), (&(addr)[4])); \ + RD1_ADDR((reg), (&(addr)[5])); \ + RD1_ADDR((reg), (&(addr)[6])); \ + RD1_ADDR((reg), (&(addr)[7])); \ + RD1_ADDR((reg), (&(addr)[8])); \ + RD1_ADDR((reg), (&(addr)[9])); \ + RD1_ADDR((reg), (&(addr)[10])); \ + RD1_ADDR((reg), (&(addr)[11])); \ + } +#define RD16_ADDR(reg, addr) \ + { \ + RD1_ADDR((reg), (&(addr)[0])); \ + RD1_ADDR((reg), (&(addr)[1])); \ + RD1_ADDR((reg), (&(addr)[2])); \ + RD1_ADDR((reg), (&(addr)[3])); \ + RD1_ADDR((reg), (&(addr)[4])); \ + RD1_ADDR((reg), (&(addr)[5])); \ + RD1_ADDR((reg), (&(addr)[6])); \ + RD1_ADDR((reg), (&(addr)[7])); \ + RD1_ADDR((reg), (&(addr)[8])); \ + RD1_ADDR((reg), (&(addr)[9])); \ + RD1_ADDR((reg), (&(addr)[10])); \ + RD1_ADDR((reg), (&(addr)[11])); \ + RD1_ADDR((reg), (&(addr)[12])); \ + RD1_ADDR((reg), (&(addr)[13])); \ + RD1_ADDR((reg), (&(addr)[14])); \ + RD1_ADDR((reg), (&(addr)[15])); \ + } /* register address */ #define REG_0000H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x000U)) diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/common/r_rsip_util.h b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_util.h similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/common/r_rsip_util.h rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_util.h diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.c new file mode 100644 index 000000000..ec6606876 --- /dev/null +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.c @@ -0,0 +1,720 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_private.h" +#include "r_rsip_wrapper.h" +#include "r_rsip_primitive.h" +#include "r_rsip_api.h" +#include "r_rsip_reg.h" +#include "r_rsip_addr.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if RSIP_CFG_AES_128_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_AES_128 RSIP_PRV_FUNC_NAME_KEY_GENERATE_AES_128 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_AES_128 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_AES_128 + #define RSIP_PRV_FUNC_RFC3394_AES_128_KEY_WRAP RSIP_PRV_FUNC_NAME_RFC3394_AES_128_KEY_WRAP + #define RSIP_PRV_FUNC_RFC3394_AES_128_KEY_UNWRAP RSIP_PRV_FUNC_NAME_RFC3394_AES_128_KEY_UNWRAP + #define RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_128 RSIP_PRV_FUNC_NAME_OTF_CHANNEL_0_AES_128 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_AES_128 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_AES_128 NULL + #define RSIP_PRV_FUNC_RFC3394_AES_128_KEY_WRAP NULL + #define RSIP_PRV_FUNC_RFC3394_AES_128_KEY_UNWRAP NULL + #define RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_128 NULL +#endif + +#if RSIP_CFG_AES_128_ENABLE && RSIP_CFG_AES_ECB_CBC_CTR_ENABLE + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_128 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_ENC_128 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_128 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_DEC_128 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_128 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_128 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_128 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_128 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_128 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CTR_128 + #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_128 RSIP_PRV_FUNC_NAME_AES_CIPHER_UPDATE_128 + #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_128 RSIP_PRV_FUNC_NAME_AES_CIPHER_FINAL_128 +#else + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_128 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_128 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_128 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_128 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_128 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_128 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_128 NULL +#endif + +#if RSIP_CFG_AES_128_ENABLE && RSIP_CFG_AES_GCM_ENABLE + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_128 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_128 + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_128 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_AAD_128 + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_128 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_TRANSITION_128 + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_128 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_128 + #define RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_128 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_FINAL_128 + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_128 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_128 + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_128 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_AAD_128 + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_128 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_TRANSITION_128 + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_128 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_128 + #define RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_128 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_FINAL_128 +#else + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_128 NULL +#endif + +#if RSIP_CFG_AES_128_ENABLE && RSIP_CFG_AES_CCM_ENABLE + #define RSIP_PRV_FUNC_AES_CCM_ENC_INIT_128 RSIP_PRV_FUNC_NAME_AES_CCM_ENC_INIT_128 + #define RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_128 RSIP_PRV_FUNC_NAME_AES_CCM_ENC_UPDATE_128 + #define RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_128 RSIP_PRV_FUNC_NAME_AES_CCM_ENC_FINAL_128 + #define RSIP_PRV_FUNC_AES_CCM_DEC_INIT_128 RSIP_PRV_FUNC_NAME_AES_CCM_DEC_INIT_128 + #define RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_128 RSIP_PRV_FUNC_NAME_AES_CCM_DEC_UPDATE_128 + #define RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_128 RSIP_PRV_FUNC_NAME_AES_CCM_DEC_FINAL_128 +#else + #define RSIP_PRV_FUNC_AES_CCM_ENC_INIT_128 NULL + #define RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_128 NULL + #define RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_128 NULL + #define RSIP_PRV_FUNC_AES_CCM_DEC_INIT_128 NULL + #define RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_128 NULL + #define RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_128 NULL +#endif + +#if RSIP_CFG_AES_128_ENABLE && RSIP_CFG_AES_CMAC_ENABLE + #define RSIP_PRV_FUNC_AES_CMAC_INIT_128 RSIP_PRV_FUNC_NAME_AES_CMAC_INIT_128 + #define RSIP_PRV_FUNC_AES_CMAC_UPDATE_128 RSIP_PRV_FUNC_NAME_AES_CMAC_UPDATE_128 + #define RSIP_PRV_FUNC_AES_CMAC_GENERATE_FINAL_128 RSIP_PRV_FUNC_NAME_AES_CMAC_GENERATE_FINAL_128 + #define RSIP_PRV_FUNC_AES_CMAC_VERIFY_FINAL_128 RSIP_PRV_FUNC_NAME_AES_CMAC_VERIFY_FINAL_128 +#else + #define RSIP_PRV_FUNC_AES_CMAC_INIT_128 NULL + #define RSIP_PRV_FUNC_AES_CMAC_UPDATE_128 NULL + #define RSIP_PRV_FUNC_AES_CMAC_GENERATE_FINAL_128 NULL + #define RSIP_PRV_FUNC_AES_CMAC_VERIFY_FINAL_128 NULL +#endif + +#if RSIP_CFG_AES_256_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_AES_256 RSIP_PRV_FUNC_NAME_KEY_GENERATE_AES_256 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_AES_256 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_AES_256 + #define RSIP_PRV_FUNC_RFC3394_AES_256_KEY_WRAP RSIP_PRV_FUNC_NAME_RFC3394_AES_256_KEY_WRAP + #define RSIP_PRV_FUNC_RFC3394_AES_256_KEY_UNWRAP RSIP_PRV_FUNC_NAME_RFC3394_AES_256_KEY_UNWRAP + #define RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_256 RSIP_PRV_FUNC_NAME_OTF_CHANNEL_0_AES_256 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_AES_256 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_AES_256 NULL + #define RSIP_PRV_FUNC_RFC3394_AES_256_KEY_WRAP NULL + #define RSIP_PRV_FUNC_RFC3394_AES_256_KEY_UNWRAP NULL + #define RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_256 NULL +#endif + +#if RSIP_CFG_AES_256_ENABLE && RSIP_CFG_AES_ECB_CBC_CTR_ENABLE + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_256 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_ENC_256 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_256 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_DEC_256 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_256 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_256 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_256 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_256 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_256 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CTR_256 + #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_256 RSIP_PRV_FUNC_NAME_AES_CIPHER_UPDATE_256 + #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_256 RSIP_PRV_FUNC_NAME_AES_CIPHER_FINAL_256 +#else + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_256 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_256 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_256 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_256 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_256 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_256 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_256 NULL +#endif + +#if RSIP_CFG_AES_256_ENABLE && RSIP_CFG_AES_GCM_ENABLE + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_256 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_256 + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_256 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_AAD_256 + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_256 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_TRANSITION_256 + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_256 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_256 + #define RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_256 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_FINAL_256 + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_256 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_256 + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_256 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_AAD_256 + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_256 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_TRANSITION_256 + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_256 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_256 + #define RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_256 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_FINAL_256 +#else + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_256 NULL +#endif + +#if RSIP_CFG_AES_256_ENABLE && RSIP_CFG_AES_CCM_ENABLE + #define RSIP_PRV_FUNC_AES_CCM_ENC_INIT_256 RSIP_PRV_FUNC_NAME_AES_CCM_ENC_INIT_256 + #define RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_256 RSIP_PRV_FUNC_NAME_AES_CCM_ENC_UPDATE_256 + #define RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_256 RSIP_PRV_FUNC_NAME_AES_CCM_ENC_FINAL_256 + #define RSIP_PRV_FUNC_AES_CCM_DEC_INIT_256 RSIP_PRV_FUNC_NAME_AES_CCM_DEC_INIT_256 + #define RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_256 RSIP_PRV_FUNC_NAME_AES_CCM_DEC_UPDATE_256 + #define RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_256 RSIP_PRV_FUNC_NAME_AES_CCM_DEC_FINAL_256 +#else + #define RSIP_PRV_FUNC_AES_CCM_ENC_INIT_256 NULL + #define RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_256 NULL + #define RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_256 NULL + #define RSIP_PRV_FUNC_AES_CCM_DEC_INIT_256 NULL + #define RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_256 NULL + #define RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_256 NULL +#endif + +#if RSIP_CFG_AES_256_ENABLE && RSIP_CFG_AES_CMAC_ENABLE + #define RSIP_PRV_FUNC_AES_CMAC_INIT_256 RSIP_PRV_FUNC_NAME_AES_CMAC_INIT_256 + #define RSIP_PRV_FUNC_AES_CMAC_UPDATE_256 RSIP_PRV_FUNC_NAME_AES_CMAC_UPDATE_256 + #define RSIP_PRV_FUNC_AES_CMAC_GENERATE_FINAL_256 RSIP_PRV_FUNC_NAME_AES_CMAC_GENERATE_FINAL_256 + #define RSIP_PRV_FUNC_AES_CMAC_VERIFY_FINAL_256 RSIP_PRV_FUNC_NAME_AES_CMAC_VERIFY_FINAL_256 +#else + #define RSIP_PRV_FUNC_AES_CMAC_INIT_256 NULL + #define RSIP_PRV_FUNC_AES_CMAC_UPDATE_256 NULL + #define RSIP_PRV_FUNC_AES_CMAC_GENERATE_FINAL_256 NULL + #define RSIP_PRV_FUNC_AES_CMAC_VERIFY_FINAL_256 NULL +#endif + +#if RSIP_CFG_AES_GCM_ENABLE + #define RSIP_PRV_FUNC_GHASH_COMPUTE RSIP_PRV_FUNC_NAME_GHASH_COMPUTE +#else + #define RSIP_PRV_FUNC_GHASH_COMPUTE NULL +#endif + +#if RSIP_CFG_XTS_AES_128_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_128 RSIP_PRV_FUNC_NAME_KEY_GENERATE_XTS_AES_128 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_XTS_AES_128 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_XTS_AES_128 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_128 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_XTS_AES_128 NULL +#endif + +#if RSIP_CFG_XTS_AES_128_ENABLE && RSIP_CFG_AES_XTS_ENABLE + #define RSIP_PRV_FUNC_XTS_AES_ENC_INIT_128 RSIP_PRV_FUNC_NAME_XTS_AES_ENC_INIT_128 + #define RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_128 RSIP_PRV_FUNC_NAME_XTS_AES_ENC_UPDATE_128 + #define RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_128 RSIP_PRV_FUNC_NAME_XTS_AES_ENC_FINAL_128 + #define RSIP_PRV_FUNC_XTS_AES_DEC_INIT_128 RSIP_PRV_FUNC_NAME_XTS_AES_DEC_INIT_128 + #define RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_128 RSIP_PRV_FUNC_NAME_XTS_AES_DEC_UPDATE_128 + #define RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_128 RSIP_PRV_FUNC_NAME_XTS_AES_DEC_FINAL_128 +#else + #define RSIP_PRV_FUNC_XTS_AES_ENC_INIT_128 NULL + #define RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_128 NULL + #define RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_128 NULL + #define RSIP_PRV_FUNC_XTS_AES_DEC_INIT_128 NULL + #define RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_128 NULL + #define RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_128 NULL +#endif + +#if RSIP_CFG_XTS_AES_256_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_256 RSIP_PRV_FUNC_NAME_KEY_GENERATE_XTS_AES_256 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_XTS_AES_256 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_XTS_AES_256 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_256 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_XTS_AES_256 NULL +#endif + +#if RSIP_CFG_XTS_AES_256_ENABLE && RSIP_CFG_AES_XTS_ENABLE + #define RSIP_PRV_FUNC_XTS_AES_ENC_INIT_256 RSIP_PRV_FUNC_NAME_XTS_AES_ENC_INIT_256 + #define RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_256 RSIP_PRV_FUNC_NAME_XTS_AES_ENC_UPDATE_256 + #define RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_256 RSIP_PRV_FUNC_NAME_XTS_AES_ENC_FINAL_256 + #define RSIP_PRV_FUNC_XTS_AES_DEC_INIT_256 RSIP_PRV_FUNC_NAME_XTS_AES_DEC_INIT_256 + #define RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_256 RSIP_PRV_FUNC_NAME_XTS_AES_DEC_UPDATE_256 + #define RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_256 RSIP_PRV_FUNC_NAME_XTS_AES_DEC_FINAL_256 +#else + #define RSIP_PRV_FUNC_XTS_AES_ENC_INIT_256 NULL + #define RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_256 NULL + #define RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_256 NULL + #define RSIP_PRV_FUNC_XTS_AES_DEC_INIT_256 NULL + #define RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_256 NULL + #define RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_256 NULL +#endif + + +#if RSIP_CFG_ECC_SECP256R1_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP256R1 RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_SECP256R1 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256R1_PUBLIC RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP256R1_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256R1_PRIVATE RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP256R1_PRIVATE + + #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP256R1 RSIP_PRV_FUNC_NAME_ECDSA_SIGN_SECP256R1 + #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP256R1 RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_SECP256R1 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP256R1 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256R1_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256R1_PRIVATE NULL + + #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP256R1 NULL + #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP256R1 NULL +#endif + +#if RSIP_CFG_ECC_SECP384R1_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP384R1 RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_SECP384R1 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP384R1_PUBLIC RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP384R1_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP384R1_PRIVATE RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP384R1_PRIVATE + + #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP384R1 RSIP_PRV_FUNC_NAME_ECDSA_SIGN_SECP384R1 + #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP384R1 RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_SECP384R1 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP384R1 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP384R1_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP384R1_PRIVATE NULL + + #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP384R1 NULL + #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP384R1 NULL +#endif + +#if RSIP_CFG_ECC_SECP521R1_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP521R1 RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_SECP521R1 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP521R1_PUBLIC RSIP_PRV_FUNC_NAME_KEY_WRAP_ECC_SECP521R1_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP521R1_PRIVATE RSIP_PRV_FUNC_NAME_KEY_WRAP_ECC_SECP521R1_PRIVATE + + #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP521R1 RSIP_PRV_FUNC_NAME_ECDSA_SIGN_SECP521R1 + #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP521R1 RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_SECP521R1 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP521R1 NULL + #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP521R1_PUBLIC NULL + #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP521R1_PRIVATE NULL + + #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP521R1 NULL + #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP521R1 NULL +#endif + +#if RSIP_CFG_RSA_2048_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_2048 RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_RSA_2048 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_2048_PUBLIC RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_2048_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_2048_PRIVATE RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_2048_PRIVATE + + #define RSIP_PRV_FUNC_RSA_ENCRYPT_2048 RSIP_PRV_FUNC_NAME_RSA_ENCRYPT_2048 + #define RSIP_PRV_FUNC_RSA_DECRYPT_2048 RSIP_PRV_FUNC_NAME_RSA_DECRYPT_2048 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_2048 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_2048_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_2048_PRIVATE NULL + + #define RSIP_PRV_FUNC_RSA_ENCRYPT_2048 NULL + #define RSIP_PRV_FUNC_RSA_DECRYPT_2048 NULL +#endif + +#if RSIP_CFG_RSA_3072_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_3072 RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_RSA_3072 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_3072_PUBLIC RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_3072_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_3072_PRIVATE RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_3072_PRIVATE + + #define RSIP_PRV_FUNC_RSA_ENCRYPT_3072 RSIP_PRV_FUNC_NAME_RSA_ENCRYPT_3072 + #define RSIP_PRV_FUNC_RSA_DECRYPT_3072 RSIP_PRV_FUNC_NAME_RSA_DECRYPT_3072 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_3072 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_3072_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_3072_PRIVATE NULL + + #define RSIP_PRV_FUNC_RSA_ENCRYPT_3072 NULL + #define RSIP_PRV_FUNC_RSA_DECRYPT_3072 NULL +#endif + +#if RSIP_CFG_RSA_4096_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_4096 RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_RSA_4096 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_4096_PUBLIC RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_4096_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_4096_PRIVATE RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_4096_PRIVATE + + #define RSIP_PRV_FUNC_RSA_ENCRYPT_4096 RSIP_PRV_FUNC_NAME_RSA_ENCRYPT_4096 + #define RSIP_PRV_FUNC_RSA_DECRYPT_4096 RSIP_PRV_FUNC_NAME_RSA_DECRYPT_4096 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_4096 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_4096_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_4096_PRIVATE NULL + + #define RSIP_PRV_FUNC_RSA_ENCRYPT_4096 NULL + #define RSIP_PRV_FUNC_RSA_DECRYPT_4096 NULL +#endif + +#if RSIP_CFG_HMAC_SHA1_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA1 RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA1 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA1 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA1 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA1 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA1 NULL +#endif + +#if RSIP_CFG_HMAC_SHA224_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA224 RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA224 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA224 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA224 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA224 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA224 NULL +#endif + +#if RSIP_CFG_HMAC_SHA256_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA256 RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA256 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA256 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA256 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA256 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA256 NULL +#endif + +#if RSIP_CFG_HMAC_SHA384_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA384 RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA384 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA384 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA384 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA384 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA384 NULL +#endif + +#if RSIP_CFG_HMAC_SHA512_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA512 RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA512 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA512 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA512 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA512 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA512 NULL +#endif + +#define RSIP_PRV_FUNC_RANDOM_NUMBER_GENERATE RSIP_PRV_FUNC_NAME_RANDOM_NUMBER_GENERATE + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +const bool g_sha_enabled[RSIP_HASH_TYPE_NUM] = +{ + [RSIP_HASH_TYPE_SHA256] = RSIP_CFG_SHA256_ENABLE, + [RSIP_HASH_TYPE_SHA384] = RSIP_CFG_SHA384_ENABLE, + [RSIP_HASH_TYPE_SHA512] = RSIP_CFG_SHA512_ENABLE, +}; + +const bool g_hmac_enabled[RSIP_KEY_HMAC_NUM] = +{ + [RSIP_KEY_HMAC_SHA256] = RSIP_CFG_HMAC_SHA256_ENABLE, + [RSIP_KEY_HMAC_SHA384] = RSIP_CFG_HMAC_SHA384_ENABLE, + [RSIP_KEY_HMAC_SHA512] = RSIP_CFG_HMAC_SHA512_ENABLE, +}; + +const rsip_func_key_generate_t gp_func_key_generate_aes[RSIP_KEY_AES_NUM] = +{ + [RSIP_KEY_AES_128] = RSIP_PRV_FUNC_KEY_GENERATE_AES_128, + [RSIP_KEY_AES_256] = RSIP_PRV_FUNC_KEY_GENERATE_AES_256 +}; + +const rsip_func_key_generate_t gp_func_key_generate_xts_aes[RSIP_KEY_AES_NUM] = +{ + [RSIP_KEY_AES_128] = RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_128, + [RSIP_KEY_AES_256] = RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_256 +}; + +const rsip_func_key_generate_t gp_func_key_generate_chacha[RSIP_KEY_CHACHA_NUM] = +{ + NULL +}; + +const rsip_func_key_generate_t gp_func_key_generate_hmac[RSIP_KEY_HMAC_NUM] = +{ + [RSIP_KEY_HMAC_SHA1] = RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA1, + [RSIP_KEY_HMAC_SHA224] = RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA224, + [RSIP_KEY_HMAC_SHA256] = RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA256, + [RSIP_KEY_HMAC_SHA384] = RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA384, + [RSIP_KEY_HMAC_SHA512] = RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA512 +}; + +const rsip_func_key_pair_generate_t gp_func_key_pair_generate_ecc[RSIP_KEY_ECC_NUM] = +{ + [RSIP_KEY_ECC_SECP256R1] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP256R1, + [RSIP_KEY_ECC_SECP384R1] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP384R1, + [RSIP_KEY_ECC_SECP521R1] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP521R1, +}; + +const rsip_func_key_pair_generate_t gp_func_key_pair_generate_rsa[RSIP_KEY_RSA_NUM] = +{ + [RSIP_KEY_RSA_1024] = NULL, + [RSIP_KEY_RSA_2048] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_2048, + [RSIP_KEY_RSA_3072] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_3072, + [RSIP_KEY_RSA_4096] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_4096 +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_aes[RSIP_KEY_AES_NUM] = +{ + [RSIP_KEY_AES_128] = RSIP_PRV_FUNC_ENC_KEY_WRAP_AES_128, + [RSIP_KEY_AES_256] = RSIP_PRV_FUNC_ENC_KEY_WRAP_AES_256 +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_xts_aes[RSIP_KEY_AES_NUM] = +{ + [RSIP_KEY_AES_128] = RSIP_PRV_FUNC_ENC_KEY_WRAP_XTS_AES_128, + [RSIP_KEY_AES_256] = RSIP_PRV_FUNC_ENC_KEY_WRAP_XTS_AES_256 +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_chacha[RSIP_KEY_CHACHA_NUM] = +{ + NULL +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_ecc_pub[RSIP_KEY_ECC_NUM] = +{ + [RSIP_KEY_ECC_SECP256R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256R1_PUBLIC, + [RSIP_KEY_ECC_SECP384R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP384R1_PUBLIC, + [RSIP_KEY_ECC_SECP521R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP521R1_PUBLIC +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_ecc_priv[RSIP_KEY_ECC_NUM] = +{ + [RSIP_KEY_ECC_SECP256R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256R1_PRIVATE, + [RSIP_KEY_ECC_SECP384R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP384R1_PRIVATE, + [RSIP_KEY_ECC_SECP521R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP521R1_PRIVATE +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_rsa_pub[RSIP_KEY_RSA_NUM] = +{ + [RSIP_KEY_RSA_2048] = RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_2048_PUBLIC, + [RSIP_KEY_RSA_3072] = RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_3072_PUBLIC, + [RSIP_KEY_RSA_4096] = RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_4096_PUBLIC +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_rsa_priv[RSIP_KEY_RSA_NUM] = +{ + [RSIP_KEY_RSA_2048] = RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_2048_PRIVATE, + [RSIP_KEY_RSA_3072] = RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_3072_PRIVATE, + [RSIP_KEY_RSA_4096] = RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_4096_PRIVATE +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_hmac[RSIP_KEY_HMAC_NUM] = +{ + [RSIP_KEY_HMAC_SHA256] = RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA256, + [RSIP_KEY_HMAC_SHA384] = RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA384, + [RSIP_KEY_HMAC_SHA512] = RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA512 +}; + +const rsip_func_subset_aes_cipher_t gp_func_aes_cipher[RSIP_KEY_AES_NUM] = +{ + [RSIP_KEY_AES_128] = + { + .p_init_ecb_enc = RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_128, + .p_init_ecb_dec = RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_128, + .p_init_cbc_enc = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_128, + .p_init_cbc_dec = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_128, + .p_init_ctr = RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_128, + .p_update = RSIP_PRV_FUNC_AES_CIPHER_UPDATE_128, + .p_final = RSIP_PRV_FUNC_AES_CIPHER_FINAL_128, + }, + [RSIP_KEY_AES_256] = + { + .p_init_ecb_enc = RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_256, + .p_init_ecb_dec = RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_256, + .p_init_cbc_enc = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_256, + .p_init_cbc_dec = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_256, + .p_init_ctr = RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_256, + .p_update = RSIP_PRV_FUNC_AES_CIPHER_UPDATE_256, + .p_final = RSIP_PRV_FUNC_AES_CIPHER_FINAL_256, + } +}; + +const rsip_func_subset_aes_xts_t gp_func_aes_xts_enc[RSIP_KEY_AES_NUM] = +{ + [RSIP_KEY_AES_128] = + { + .p_init = RSIP_PRV_FUNC_XTS_AES_ENC_INIT_128, + .p_update = RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_128, + .p_final = RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_128 + }, + [RSIP_KEY_AES_256] = + { + .p_init = RSIP_PRV_FUNC_XTS_AES_ENC_INIT_256, + .p_update = RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_256, + .p_final = RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_256 + } +}; + +const rsip_func_subset_aes_xts_t gp_func_aes_xts_dec[RSIP_KEY_AES_NUM] = +{ + [RSIP_KEY_AES_128] = + { + .p_init = RSIP_PRV_FUNC_XTS_AES_DEC_INIT_128, + .p_update = RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_128, + .p_final = RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_128 + }, + [RSIP_KEY_AES_256] = + { + .p_init = RSIP_PRV_FUNC_XTS_AES_DEC_INIT_256, + .p_update = RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_256, + .p_final = RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_256 + } +}; + +const rsip_func_subset_aes_gcm_t gp_func_aes_gcm_enc[RSIP_KEY_AES_NUM] = +{ + [RSIP_KEY_AES_128] = + { + .p_init = RSIP_PRV_FUNC_AES_GCM_ENC_INIT_128, + .p_updateAad = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_128, + .p_updateTransition = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_128, + .p_update = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_128, + .p_encryptFinal = RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_128 + }, + [RSIP_KEY_AES_256] = + { + .p_init = RSIP_PRV_FUNC_AES_GCM_ENC_INIT_256, + .p_updateAad = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_256, + .p_updateTransition = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_256, + .p_update = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_256, + .p_encryptFinal = RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_256 + } +}; + +const rsip_func_subset_aes_gcm_t gp_func_aes_gcm_dec[RSIP_KEY_AES_NUM] = +{ + [RSIP_KEY_AES_128] = + { + .p_init = RSIP_PRV_FUNC_AES_GCM_DEC_INIT_128, + .p_updateAad = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_128, + .p_updateTransition = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_128, + .p_update = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_128, + .p_decryptFinal = RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_128 + }, + [RSIP_KEY_AES_256] = + { + .p_init = RSIP_PRV_FUNC_AES_GCM_DEC_INIT_256, + .p_updateAad = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_256, + .p_updateTransition = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_256, + .p_update = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_256, + .p_decryptFinal = RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_256 + } +}; + +const rsip_func_subset_aes_ccm_t gp_func_aes_ccm_enc[RSIP_KEY_AES_NUM] = +{ + [RSIP_KEY_AES_128] = + { + .p_encryptInit = RSIP_PRV_FUNC_AES_CCM_ENC_INIT_128, + .p_update = RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_128, + .p_encryptFinal = RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_128 + }, + [RSIP_KEY_AES_256] = + { + .p_encryptInit = RSIP_PRV_FUNC_AES_CCM_ENC_INIT_256, + .p_update = RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_256, + .p_encryptFinal = RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_256 + } +}; + +const rsip_func_subset_aes_ccm_t gp_func_aes_ccm_dec[RSIP_KEY_AES_NUM] = +{ + [RSIP_KEY_AES_128] = + { + .p_decryptInit = RSIP_PRV_FUNC_AES_CCM_DEC_INIT_128, + .p_update = RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_128, + .p_decryptFinal = RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_128 + }, + [RSIP_KEY_AES_256] = + { + .p_decryptInit = RSIP_PRV_FUNC_AES_CCM_DEC_INIT_256, + .p_update = RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_256, + .p_decryptFinal = RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_256 + } +}; + +const rsip_func_subset_aes_cmac_t gp_func_aes_cmac[RSIP_KEY_AES_NUM] = +{ + [RSIP_KEY_AES_128] = + { + .p_init = RSIP_PRV_FUNC_AES_CMAC_INIT_128, + .p_update = RSIP_PRV_FUNC_AES_CMAC_UPDATE_128, + .p_generateFinal = RSIP_PRV_FUNC_AES_CMAC_GENERATE_FINAL_128, + .p_verifyFinal = RSIP_PRV_FUNC_AES_CMAC_VERIFY_FINAL_128 + }, + [RSIP_KEY_AES_256] = + { + .p_init = RSIP_PRV_FUNC_AES_CMAC_INIT_256, + .p_update = RSIP_PRV_FUNC_AES_CMAC_UPDATE_256, + .p_generateFinal = RSIP_PRV_FUNC_AES_CMAC_GENERATE_FINAL_256, + .p_verifyFinal = RSIP_PRV_FUNC_AES_CMAC_VERIFY_FINAL_256 + } +}; + +const rsip_func_ecdsa_sign_t gp_func_ecdsa_sign[RSIP_KEY_ECC_NUM] = +{ + [RSIP_KEY_ECC_SECP256R1] = RSIP_PRV_FUNC_ECDSA_SIGN_SECP256R1, + [RSIP_KEY_ECC_SECP384R1] = RSIP_PRV_FUNC_ECDSA_SIGN_SECP384R1, + [RSIP_KEY_ECC_SECP521R1] = RSIP_PRV_FUNC_ECDSA_SIGN_SECP521R1, +}; + +const rsip_func_ecdsa_verify_t gp_func_ecdsa_verify[RSIP_KEY_ECC_NUM] = +{ + [RSIP_KEY_ECC_SECP256R1] = RSIP_PRV_FUNC_ECDSA_VERIFY_SECP256R1, + [RSIP_KEY_ECC_SECP384R1] = RSIP_PRV_FUNC_ECDSA_VERIFY_SECP384R1, + [RSIP_KEY_ECC_SECP521R1] = RSIP_PRV_FUNC_ECDSA_VERIFY_SECP521R1, +}; + +const rsip_func_rsa_t gp_func_rsa_public[RSIP_KEY_RSA_NUM] = +{ + [RSIP_KEY_RSA_2048] = RSIP_PRV_FUNC_RSA_ENCRYPT_2048, + [RSIP_KEY_RSA_3072] = RSIP_PRV_FUNC_RSA_ENCRYPT_3072, + [RSIP_KEY_RSA_4096] = RSIP_PRV_FUNC_RSA_ENCRYPT_4096 +}; + +const rsip_func_rsa_t gp_func_rsa_private[RSIP_KEY_RSA_NUM] = +{ + [RSIP_KEY_RSA_2048] = RSIP_PRV_FUNC_RSA_DECRYPT_2048, + [RSIP_KEY_RSA_3072] = RSIP_PRV_FUNC_RSA_DECRYPT_3072, + [RSIP_KEY_RSA_4096] = RSIP_PRV_FUNC_RSA_DECRYPT_4096 +}; + +const rsip_func_rfc3394_key_wrap_t gp_func_rfc3394_key_wrap[RSIP_KEY_AES_NUM] = +{ + [RSIP_KEY_AES_128] = RSIP_PRV_FUNC_RFC3394_AES_128_KEY_WRAP, + [RSIP_KEY_AES_192] = NULL, + [RSIP_KEY_AES_256] = RSIP_PRV_FUNC_RFC3394_AES_256_KEY_WRAP +}; + +const rsip_func_rfc3394_key_unwrap_t gp_func_rfc3394_key_unwrap[RSIP_KEY_AES_NUM] = +{ + [RSIP_KEY_AES_128] = RSIP_PRV_FUNC_RFC3394_AES_128_KEY_UNWRAP, + [RSIP_KEY_AES_192] = NULL, + [RSIP_KEY_AES_256] = RSIP_PRV_FUNC_RFC3394_AES_256_KEY_UNWRAP +}; + + +const rsip_func_otf_t gp_func_otf[RSIP_OTF_CHANNEL_NUM][RSIP_KEY_AES_NUM] = +{ + [RSIP_OTF_CHANNEL_0] = + { + [RSIP_KEY_AES_128] = RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_128, + [RSIP_KEY_AES_192] = NULL, + [RSIP_KEY_AES_256] = RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_256 + }, + [RSIP_OTF_CHANNEL_1] = + { + [RSIP_KEY_AES_128] = NULL, + [RSIP_KEY_AES_192] = NULL, + [RSIP_KEY_AES_256] = NULL + } +}; + +const rsip_func_rng_t gp_func_rng = RSIP_PRV_FUNC_RANDOM_NUMBER_GENERATE; +const rsip_func_ghash_t gp_func_ghash_compute = RSIP_PRV_FUNC_GHASH_COMPUTE; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/common/r_rsip_private.h b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.h similarity index 54% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/common/r_rsip_private.h rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.h index 463a1895d..16d2f156d 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/common/r_rsip_private.h +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.h @@ -65,6 +65,7 @@ typedef rsip_ret_t (* rsip_func_rsa_t)(const uint32_t InData_KeyIndex[], const u uint32_t OutData_Text[]); /* OTF */ typedef rsip_ret_t (* rsip_func_otf_t)(const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]); + /* * Private/Primitive function subsets */ @@ -121,76 +122,15 @@ typedef struct st_rsip_func_subset_aes_ccm } rsip_func_subset_aes_ccm_t; /* AES-CMAC */ -typedef struct st_rsip_func_subset_aes_mac +typedef struct st_rsip_func_subset_aes_cmac { rsip_ret_t (* p_init)(const uint32_t * InData_KeyIndex); void (* p_update)(const uint32_t * InData_Text, uint32_t MAX_CNT); rsip_ret_t (* p_generateFinal)(const uint32_t * InData_Text, uint32_t * OutData_DataT, const uint32_t all_msg_len); rsip_ret_t (* p_verifyFinal)(const uint32_t * InData_Text, const uint32_t * InData_DataT, const uint32_t * InData_DataTLen, const uint32_t all_msg_len); -} rsip_func_subset_aes_mac_t; - -/* HMAC */ -typedef rsip_ret_t (* rsip_func_hmac_single_t)(const uint32_t InData_KeyIndex[], const uint32_t InData_Cmd[], - const uint32_t InData_Msg[], const uint32_t InData_MsgLen[], - const uint32_t InData_MAC[], - const uint32_t InData_length[], uint32_t MAX_CNT, - uint32_t OutData_MAC[]); -typedef rsip_ret_t (* rsip_func_hmac_multi_t)(const uint32_t InData_KeyIndex[], const uint32_t InData_Cmd[], - const uint32_t InData_Msg[], const uint32_t InData_MsgLen[], - const uint32_t InData_MAC[], - const uint32_t InData_length[], const uint32_t InData_State[], - uint32_t MAX_CNT, uint32_t OutData_MAC[], - uint32_t OutData_State[]); - -/* - * Private/Primitive function subsets - */ +} rsip_func_subset_aes_cmac_t; -typedef struct st_rsip_func -{ - rsip_func_key_generate_t p_key_generate_aes[RSIP_KEY_AES_NUM]; - rsip_func_key_generate_t p_key_generate_xts_aes[RSIP_KEY_AES_NUM]; - rsip_func_key_generate_t p_key_generate_chacha[RSIP_KEY_CHACHA_NUM]; - rsip_func_key_generate_t p_key_generate_hmac[RSIP_KEY_HMAC_NUM]; - - rsip_func_key_pair_generate_t p_key_pair_generate_ecc[RSIP_KEY_ECC_NUM]; - rsip_func_key_pair_generate_t p_key_pair_generate_rsa[RSIP_KEY_RSA_NUM]; - - rsip_func_encrypted_key_wrap_t p_encrypted_key_wrap_aes[RSIP_KEY_AES_NUM]; - rsip_func_encrypted_key_wrap_t p_encrypted_key_wrap_xts_aes[RSIP_KEY_AES_NUM]; - rsip_func_encrypted_key_wrap_t p_encrypted_key_wrap_chacha[RSIP_KEY_CHACHA_NUM]; - rsip_func_encrypted_key_wrap_t p_encrypted_key_wrap_ecc_pub[RSIP_KEY_ECC_NUM]; - rsip_func_encrypted_key_wrap_t p_encrypted_key_wrap_ecc_priv[RSIP_KEY_ECC_NUM]; - rsip_func_encrypted_key_wrap_t p_encrypted_key_wrap_rsa_pub[RSIP_KEY_RSA_NUM]; - rsip_func_encrypted_key_wrap_t p_encrypted_key_wrap_rsa_priv[RSIP_KEY_RSA_NUM]; - rsip_func_encrypted_key_wrap_t p_encrypted_key_wrap_hmac[RSIP_KEY_HMAC_NUM]; - - rsip_func_rfc3394_key_wrap_t p_rfc3394_key_wrap[RSIP_KEY_AES_NUM]; - rsip_func_rfc3394_key_unwrap_t p_rfc3394_key_unwrap[RSIP_KEY_AES_NUM]; - - rsip_func_subset_aes_cipher_t p_aes_cipher[RSIP_KEY_AES_NUM]; - rsip_func_subset_aes_xts_t p_aes_xts_enc[RSIP_KEY_AES_NUM]; - rsip_func_subset_aes_xts_t p_aes_xts_dec[RSIP_KEY_AES_NUM]; - rsip_func_subset_aes_gcm_t p_aes_gcm_enc[RSIP_KEY_AES_NUM]; - rsip_func_subset_aes_gcm_t p_aes_gcm_dec[RSIP_KEY_AES_NUM]; - rsip_func_subset_aes_ccm_t p_aes_ccm_enc[RSIP_KEY_AES_NUM]; - rsip_func_subset_aes_ccm_t p_aes_ccm_dec[RSIP_KEY_AES_NUM]; - rsip_func_subset_aes_mac_t p_aes_mac[RSIP_KEY_AES_NUM]; - - rsip_func_ecdsa_sign_t p_ecdsa_sign[RSIP_KEY_ECC_NUM]; - rsip_func_ecdsa_verify_t p_ecdsa_verify[RSIP_KEY_ECC_NUM]; - rsip_func_otf_t p_func_otf[RSIP_OTF_CHANNEL_NUM][RSIP_KEY_AES_NUM]; - - rsip_func_rsa_t p_rsa_public[RSIP_KEY_RSA_NUM]; - rsip_func_rsa_t p_rsa_private[RSIP_KEY_RSA_NUM]; - - rsip_func_hmac_single_t p_hmac_single[RSIP_KEY_HMAC_NUM]; - rsip_func_hmac_multi_t p_hmac_multi[RSIP_KEY_HMAC_NUM]; - - rsip_func_rng_t p_rng; - rsip_func_ghash_t p_ghash_compute; -} rsip_func_t; /********************************************************************************************************************** * Exported global variables @@ -199,7 +139,45 @@ typedef struct st_rsip_func extern const bool g_sha_enabled[RSIP_HASH_TYPE_NUM]; extern const bool g_hmac_enabled[RSIP_KEY_HMAC_NUM]; -extern const rsip_func_t g_func; +extern const rsip_func_key_generate_t gp_func_key_generate_aes[RSIP_KEY_AES_NUM]; +extern const rsip_func_key_generate_t gp_func_key_generate_xts_aes[RSIP_KEY_AES_NUM]; +extern const rsip_func_key_generate_t gp_func_key_generate_chacha[RSIP_KEY_CHACHA_NUM]; +extern const rsip_func_key_generate_t gp_func_key_generate_hmac[RSIP_KEY_HMAC_NUM]; + +extern const rsip_func_key_pair_generate_t gp_func_key_pair_generate_ecc[RSIP_KEY_ECC_NUM]; +extern const rsip_func_key_pair_generate_t gp_func_key_pair_generate_rsa[RSIP_KEY_RSA_NUM]; + +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_aes[RSIP_KEY_AES_NUM]; +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_xts_aes[RSIP_KEY_AES_NUM]; +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_chacha[RSIP_KEY_CHACHA_NUM]; +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_ecc_pub[RSIP_KEY_ECC_NUM]; +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_ecc_priv[RSIP_KEY_ECC_NUM]; +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_rsa_pub[RSIP_KEY_RSA_NUM]; +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_rsa_priv[RSIP_KEY_RSA_NUM]; +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_hmac[RSIP_KEY_HMAC_NUM]; + +extern const rsip_func_subset_aes_cipher_t gp_func_aes_cipher[RSIP_KEY_AES_NUM]; +extern const rsip_func_subset_aes_xts_t gp_func_aes_xts_enc[RSIP_KEY_AES_NUM]; +extern const rsip_func_subset_aes_xts_t gp_func_aes_xts_dec[RSIP_KEY_AES_NUM]; +extern const rsip_func_subset_aes_gcm_t gp_func_aes_gcm_enc[RSIP_KEY_AES_NUM]; +extern const rsip_func_subset_aes_gcm_t gp_func_aes_gcm_dec[RSIP_KEY_AES_NUM]; +extern const rsip_func_subset_aes_ccm_t gp_func_aes_ccm_enc[RSIP_KEY_AES_NUM]; +extern const rsip_func_subset_aes_ccm_t gp_func_aes_ccm_dec[RSIP_KEY_AES_NUM]; +extern const rsip_func_subset_aes_cmac_t gp_func_aes_cmac[RSIP_KEY_AES_NUM]; + +extern const rsip_func_ecdsa_sign_t gp_func_ecdsa_sign[RSIP_KEY_ECC_NUM]; +extern const rsip_func_ecdsa_verify_t gp_func_ecdsa_verify[RSIP_KEY_ECC_NUM]; + +extern const rsip_func_rsa_t gp_func_rsa_public[RSIP_KEY_RSA_NUM]; +extern const rsip_func_rsa_t gp_func_rsa_private[RSIP_KEY_RSA_NUM]; + +extern const rsip_func_rfc3394_key_wrap_t gp_func_rfc3394_key_wrap[RSIP_KEY_AES_NUM]; +extern const rsip_func_rfc3394_key_unwrap_t gp_func_rfc3394_key_unwrap[RSIP_KEY_AES_NUM]; + +extern const rsip_func_otf_t gp_func_otf[RSIP_OTF_CHANNEL_NUM][RSIP_KEY_AES_NUM]; + +extern const rsip_func_rng_t gp_func_rng; +extern const rsip_func_ghash_t gp_func_ghash_compute; /********************************************************************************************************************** * Public Function Prototypes @@ -220,104 +198,128 @@ rsip_ret_t r_rsip_open(void); rsip_ret_t r_rsip_close(void); /*******************************************************************************************************************//** - * Stores input Key Update Key (KUK). + * Sets Key Update Key (KUK). * * @param[in] p_key_update_key_value KUK value. **********************************************************************************************************************/ -void r_rsip_kuk_store(const uint8_t * p_key_update_key_value); +void r_rsip_kuk_set(const uint8_t * p_key_update_key_value); /*******************************************************************************************************************//** - * Computes SHA-1 or SHA-2 message digest in single-part operation. + * 1. Initialize hash operation. + * 2. Input block message in block length. * - * @param[in] in_data_msg Big-endian message. - * @param[out] out_data_msg_digest Big-endian message digest. - * @param[in] hash_type Generating hash type. - * @param[in] message_length Byte size of message. + * @note Message length must be at least 1 block. + * + * @param[in] hash_type Generating hash type. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[in,out] internal_state Buffer of internal state. * * @return The return value of the internally called primitive function. **********************************************************************************************************************/ -rsip_ret_t r_rsip_sha1sha2_compute_single(const uint32_t in_data_msg[], - uint32_t out_data_msg_digest[], - rsip_hash_type_t hash_type, - uint32_t message_length); +rsip_ret_t r_rsip_sha1sha2_init_update(rsip_hash_type_t hash_type, + const uint8_t * p_message, + uint64_t message_length, + uint32_t * internal_state); /*******************************************************************************************************************//** - * Computes HMAC message digest in single-part operation. + * 1. Resume hash operation. + * 2. Input block message in block length. * - * @param[in] InData_Msg Big-endian message. - * @param[out] OutData_MAC Big-endian MAC. - * @param[in] p_func Private/Primitive function. - * @param[in] p_wrapped_key Wrapped HMAC key. - * @param[in] message_length Byte size of message. + * @note Message length must be at least 1 block. + * + * @param[in] hash_type Generating hash type. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[in,out] internal_state Buffer of internal state. * * @return The return value of the internally called primitive function. **********************************************************************************************************************/ -rsip_ret_t r_rsip_hmac_compute_single(const uint32_t InData_Msg[], - uint32_t OutData_MAC[], - const rsip_func_hmac_single_t p_func, - const rsip_wrapped_key_t * p_wrapped_key, - uint32_t message_length); +rsip_ret_t r_rsip_sha1sha2_resume_update(rsip_hash_type_t hash_type, + const uint8_t * p_message, + uint64_t message_length, + uint32_t * internal_state); /*******************************************************************************************************************//** - * Verifies HMAC message digest in single-part operation. + * Input block message in block length. * - * @param[in] InData_Msg Big-endian message. - * @param[in] p_mac Big-endian MAC. - * @param[in] p_func Private/Primitive function. - * @param[in] p_wrapped_key Wrapped HMAC key. - * @param[in] message_length Byte size of message. - * @param[in] mac_length Byte size of MAC. + * @note Message length must be at least 1 block. + * + * @param[in] hash_type Generating hash type. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[in,out] internal_state Buffer of internal state. * * @return The return value of the internally called primitive function. **********************************************************************************************************************/ -rsip_ret_t r_rsip_hmac_verify_single(const uint32_t InData_Msg[], - const uint8_t * p_mac, - const rsip_func_hmac_single_t p_func, - const rsip_wrapped_key_t * p_wrapped_key, - uint32_t message_length, - uint32_t mac_length); +rsip_ret_t r_rsip_sha1sha2_update(rsip_hash_type_t hash_type, + const uint8_t * p_message, + uint64_t message_length, + uint32_t * internal_state); /*******************************************************************************************************************//** - * Computes or Verifies HMAC in multi-part operation. + * Suspend hash operation. * - * @param[in,out] p_ctrl Pointer to control block. - * @param[in] p_message Big-endian message. - * @param[in] message_length Byte size of message. - * @param[in,out] p_mac Big-endian MAC. For computation finalization, it is output data; - * for verification finalization, it is input data. - * @param[in] mac_length Byte size of MAC. This value is input only verification finalization. + * @param[in,out] internal_state Buffer of internal state. * * @return The return value of the internally called primitive function. **********************************************************************************************************************/ -rsip_ret_t r_rsip_hmac_calc_multi(rsip_ctrl_t * const p_ctrl, - const uint8_t * p_message, - uint32_t message_length, - uint8_t * p_mac, - uint32_t mac_length); - -rsip_ret_t r_rsip_sha1sha2_init_update(rsip_hash_type_t hash_type, - const uint8_t * p_message, - uint64_t message_length, - uint32_t * internal_state); -rsip_ret_t r_rsip_sha1sha2_resume_update(rsip_hash_type_t hash_type, - const uint8_t * p_message, - uint64_t message_length, - uint32_t * internal_state); -rsip_ret_t r_rsip_sha1sha2_update(rsip_hash_type_t hash_type, - const uint8_t * p_message, - uint64_t message_length, - uint32_t * internal_state); rsip_ret_t r_rsip_sha1sha2_suspend(uint32_t * internal_state); + +/*******************************************************************************************************************//** + * 1. Initialize hash operation. + * 2. Input the remaining message and finalize hash operation. + * + * @note This function allows empty message. + * + * @param[in] hash_type Generating hash type. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[out] p_digest Pointer to destination of message digest. The length depends on hash type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ rsip_ret_t r_rsip_sha1sha2_init_final(rsip_hash_type_t hash_type, const uint8_t * p_message, uint64_t message_length, uint8_t * p_digest); + +/*******************************************************************************************************************//** + * 1. Resume hash operation. + * 2. Input the remaining message and finalize hash operation. + * + * @note Message length must be at least 1 byte. + * + * @param[in] hash_type Generating hash type. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[in] total_message_length Byte length of total message length. + * @param[out] p_digest Pointer to destination of message digest. The length depends on hash type. + * @param[in,out] internal_state Buffer of internal state. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ rsip_ret_t r_rsip_sha1sha2_resume_final(rsip_hash_type_t hash_type, const uint8_t * p_message, uint64_t message_length, uint64_t total_message_length, uint8_t * p_digest, uint32_t * internal_state); + +/*******************************************************************************************************************//** + * Input the remaining message and finalize hash operation. + * + * @note Message length must be at least 1 byte. + * + * @param[in] hash_type Generating hash type. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[in] total_message_length Byte length of total message length. + * @param[out] p_digest Pointer to destination of message digest. The length depends on hash type. + * @param[in,out] internal_state Buffer of internal state. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ rsip_ret_t r_rsip_sha1sha2_final(rsip_hash_type_t hash_type, const uint8_t * p_message, uint64_t message_length, @@ -325,40 +327,170 @@ rsip_ret_t r_rsip_sha1sha2_final(rsip_hash_type_t hash_type, uint8_t * p_digest, uint32_t * internal_state); +/*******************************************************************************************************************//** + * 1. Initialize HMAC operation. + * 2. Input block message in block length. + * + * @note Message length must be at least 1 block. + * + * @param[in] p_wrapped_key Pointer to wrapped key of HMAC key. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[in,out] internal_state Buffer of internal state. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ rsip_ret_t r_rsip_hmac_init_update(const rsip_wrapped_key_t * p_wrapped_key, const uint8_t * p_message, uint64_t message_length, uint32_t * internal_state); + +/*******************************************************************************************************************//** + * 1. Resume HMAC operation. + * 2. Input block message in block length. + * + * @note Message length must be at least 1 block. + * + * @param[in] p_wrapped_key Pointer to wrapped key of HMAC key. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[in,out] internal_state Buffer of internal state. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ rsip_ret_t r_rsip_hmac_resume_update(const rsip_wrapped_key_t * p_wrapped_key, const uint8_t * p_message, uint64_t message_length, uint32_t * internal_state); + +/*******************************************************************************************************************//** + * Input block message in block length. + * + * @note Message length must be at least 1 block. + * + * @param[in] p_wrapped_key Pointer to wrapped key of HMAC key. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[in,out] internal_state Buffer of internal state. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ rsip_ret_t r_rsip_hmac_update(const rsip_wrapped_key_t * p_wrapped_key, const uint8_t * p_message, uint64_t message_length, uint32_t * internal_state); + +/*******************************************************************************************************************//** + * Suspend HMAC operation. + * + * @param[in,out] internal_state Buffer of internal state. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ rsip_ret_t r_rsip_hmac_suspend(uint32_t * internal_state); + +/*******************************************************************************************************************//** + * 1. Initialize HMAC operation. + * 2. Input the remaining message and finalize HMAC operation. + * 3. Output MAC. + * + * @note This function allows empty message. + * + * @param[in] p_wrapped_key Pointer to wrapped key of HMAC key. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[out] p_mac Pointer to destination of message digest. The length depends on MAC type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ rsip_ret_t r_rsip_hmac_init_final(const rsip_wrapped_key_t * p_wrapped_key, const uint8_t * p_message, uint64_t message_length, uint8_t * p_mac); + +/*******************************************************************************************************************//** + * 1. Resume HMAC operation. + * 2. Input the remaining message and finalize HMAC operation. + * 3. Output MAC. + * + * @note Message length must be at least 1 byte. + * + * @param[in] p_wrapped_key Pointer to wrapped key of HMAC key. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[in] total_message_length Byte length of total message length. + * @param[out] p_mac Pointer to destination of message digest. The length depends on MAC type. + * @param[in,out] internal_state Buffer of internal state. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ rsip_ret_t r_rsip_hmac_resume_final(const rsip_wrapped_key_t * p_wrapped_key, const uint8_t * p_message, uint64_t message_length, uint64_t total_message_length, uint8_t * p_mac, uint32_t * internal_state); + +/*******************************************************************************************************************//** + * 1. Input the remaining message and finalize HMAC operation. + * 2. Output MAC. + * + * @note Message length must be at least 1 byte. + * + * @param[in] p_wrapped_key Pointer to wrapped key of HMAC key. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[in] total_message_length Byte length of total message length. + * @param[out] p_mac Pointer to destination of message digest. The length depends on MAC type. + * @param[in,out] internal_state Buffer of internal state. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ rsip_ret_t r_rsip_hmac_final(const rsip_wrapped_key_t * p_wrapped_key, const uint8_t * p_message, uint64_t message_length, uint64_t total_message_length, uint8_t * p_mac, uint32_t * internal_state); + +/*******************************************************************************************************************//** + * 1. Initialize HMAC operation. + * 2. Input the remaining message and finalize HMAC operation. + * 3. Verify MAC. + * + * @note This function allows empty message. + * + * @param[in] p_wrapped_key Pointer to wrapped key of HMAC key. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[in] p_mac Pointer to MAC. The length depends on mac_length. + * @param[in] mac_length Byte length of MAC. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ rsip_ret_t r_rsip_hmac_init_verify(const rsip_wrapped_key_t * p_wrapped_key, const uint8_t * p_message, uint64_t message_length, const uint8_t * p_mac, uint32_t mac_length); + +/*******************************************************************************************************************//** + * 1. Resume HMAC operation. + * 2. Input the remaining message and finalize HMAC operation. + * 3. Verify MAC. + * + * @note Message length must be at least 1 byte. + * + * @param[in] p_wrapped_key Pointer to wrapped key of HMAC key. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[in] total_message_length Byte length of total message length. + * @param[in] p_mac Pointer to MAC. The length depends on mac_length. + * @param[in] mac_length Byte length of MAC. + * @param[in,out] internal_state Buffer of internal state. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ rsip_ret_t r_rsip_hmac_resume_verify(const rsip_wrapped_key_t * p_wrapped_key, const uint8_t * p_message, uint64_t message_length, @@ -366,6 +498,23 @@ rsip_ret_t r_rsip_hmac_resume_verify(const rsip_wrapped_key_t * p_wrapped_key, const uint8_t * p_mac, uint32_t mac_length, uint32_t * internal_state); + +/*******************************************************************************************************************//** + * 1. Input the remaining message and finalize HMAC operation. + * 2. Verify MAC. + * + * @note Message length must be at least 1 byte. + * + * @param[in] p_wrapped_key Pointer to wrapped key of HMAC key. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[in] total_message_length Byte length of total message length. + * @param[in] p_mac Pointer to MAC. The length depends on mac_length. + * @param[in] mac_length Byte length of MAC. + * @param[in,out] internal_state Buffer of internal state. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ rsip_ret_t r_rsip_hmac_verify(const rsip_wrapped_key_t * p_wrapped_key, const uint8_t * p_message, uint64_t message_length, @@ -374,8 +523,83 @@ rsip_ret_t r_rsip_hmac_verify(const rsip_wrapped_key_t * p_wrapped_key, uint32_t mac_length, uint32_t * internal_state); +/*******************************************************************************************************************//** + * Computes SHA-1 or SHA-2 message digest in single-part operation. + * + * @param[in] in_data_msg Big-endian message. + * @param[out] out_data_msg_digest Big-endian message digest. + * @param[in] hash_type Generating hash type. + * @param[in] message_length Byte size of message. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_sha1sha2_compute_single(const uint32_t in_data_msg[], + uint32_t out_data_msg_digest[], + rsip_hash_type_t hash_type, + uint32_t message_length); +#if 0 +/*******************************************************************************************************************//** + * Computes HMAC message digest in single-part operation. + * + * @param[in] InData_Msg Big-endian message. + * @param[out] OutData_MAC Big-endian MAC. + * @param[in] p_func Private/Primitive function. + * @param[in] p_wrapped_key Wrapped HMAC key. + * @param[in] message_length Byte size of message. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_hmac_compute_single(const uint32_t InData_Msg[], + uint32_t OutData_MAC[], + const rsip_func_hmac_single_t p_func, + const rsip_wrapped_key_t * p_wrapped_key, + uint32_t message_length); + +/*******************************************************************************************************************//** + * Verifies HMAC message digest in single-part operation. + * + * @param[in] InData_Msg Big-endian message. + * @param[in] p_mac Big-endian MAC. + * @param[in] p_func Private/Primitive function. + * @param[in] p_wrapped_key Wrapped HMAC key. + * @param[in] message_length Byte size of message. + * @param[in] mac_length Byte size of MAC. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_hmac_verify_single(const uint32_t InData_Msg[], + const uint8_t * p_mac, + const rsip_func_hmac_single_t p_func, + const rsip_wrapped_key_t * p_wrapped_key, + uint32_t message_length, + uint32_t mac_length); +#endif +/*******************************************************************************************************************//** + * Computes or Verifies HMAC in multi-part operation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_message Big-endian message. + * @param[in] message_length Byte size of message. + * @param[in,out] p_mac Big-endian MAC. For computation finalization, it is output data; + * for verification finalization, it is input data. + * @param[in] mac_length Byte size of MAC. This value is input only verification finalization. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_hmac_calc_multi(rsip_ctrl_t * const p_ctrl, + const uint8_t * p_message, + uint32_t message_length, + uint8_t * p_mac, + uint32_t mac_length); + + /*******************************************************************************************************************//** * Converts byte data to word (4-byte) and rounds up it. + * + * @param[in] bytes Byte length + * + * @return Word length + ***********************************************************************************************************************/ RSIP_PRV_STATIC_INLINE uint32_t r_rsip_byte_to_word_convert (const uint32_t bytes) { @@ -384,6 +608,10 @@ RSIP_PRV_STATIC_INLINE uint32_t r_rsip_byte_to_word_convert (const uint32_t byte /*******************************************************************************************************************//** * Converts byte data to bit data. This function returns upper 3 digits. + * + * @param[in] bytes Byte length + * + * @return Bit length (upper 3 digits) ***********************************************************************************************************************/ RSIP_PRV_STATIC_INLINE uint32_t r_rsip_byte_to_bit_convert_upper (const uint64_t bytes) { @@ -392,6 +620,10 @@ RSIP_PRV_STATIC_INLINE uint32_t r_rsip_byte_to_bit_convert_upper (const uint64_t /*******************************************************************************************************************//** * Converts byte data to bit data. This function returns lower 32 digits. + * + * @param[in] bytes Byte length + * + * @return Bit length (lower 32 digits) ***********************************************************************************************************************/ RSIP_PRV_STATIC_INLINE uint32_t r_rsip_byte_to_bit_convert_lower (const uint64_t bytes) { diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip.c similarity index 80% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip.c index 3646b7dd4..53b503f56 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip.c +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip.c @@ -114,26 +114,33 @@ static const uint32_t gs_wrapped_key_value_len_xts_aes[RSIP_KEY_AES_NUM] = [RSIP_KEY_AES_256] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_XTS_AES_256, }; -static const uint32_t gs_wrapped_key_value_len_chacha[RSIP_KEY_CHACHA_NUM] = -{ -}; - static const uint32_t gs_wrapped_key_value_len_ecc_pub[RSIP_KEY_ECC_NUM] = { - [RSIP_KEY_ECC_SECP256R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_SECP256R1_PUBLIC, - [RSIP_KEY_ECC_SECP384R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_SECP384R1_PUBLIC, - [RSIP_KEY_ECC_SECP521R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_SECP521R1_PUBLIC, + [RSIP_KEY_ECC_SECP256R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_SECP256R1_PUBLIC, + [RSIP_KEY_ECC_SECP384R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_SECP384R1_PUBLIC, + [RSIP_KEY_ECC_SECP521R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_SECP521R1_PUBLIC, + [RSIP_KEY_ECC_SECP256K1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_SECP256K1_PUBLIC, + [RSIP_KEY_ECC_BRAINPOOLP256R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_BRAINPOOLP256R1_PUBLIC, + [RSIP_KEY_ECC_BRAINPOOLP384R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_BRAINPOOLP384R1_PUBLIC, + [RSIP_KEY_ECC_BRAINPOOLP512R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_BRAINPOOLP512R1_PUBLIC, + [RSIP_KEY_ECC_EDWARDS25519] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_EDWARDS25519_PUBLIC, }; static const uint32_t gs_wrapped_key_value_len_ecc_priv[RSIP_KEY_ECC_NUM] = { - [RSIP_KEY_ECC_SECP256R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_SECP256R1_PRIVATE, - [RSIP_KEY_ECC_SECP384R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_SECP384R1_PRIVATE, - [RSIP_KEY_ECC_SECP521R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_SECP521R1_PRIVATE, + [RSIP_KEY_ECC_SECP256R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_SECP256R1_PRIVATE, + [RSIP_KEY_ECC_SECP384R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_SECP384R1_PRIVATE, + [RSIP_KEY_ECC_SECP521R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_SECP521R1_PRIVATE, + [RSIP_KEY_ECC_SECP256K1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_SECP256K1_PRIVATE, + [RSIP_KEY_ECC_BRAINPOOLP256R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_BRAINPOOLP256R1_PRIVATE, + [RSIP_KEY_ECC_BRAINPOOLP384R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_BRAINPOOLP384R1_PRIVATE, + [RSIP_KEY_ECC_BRAINPOOLP512R1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_BRAINPOOLP512R1_PRIVATE, + [RSIP_KEY_ECC_EDWARDS25519] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_ECC_EDWARDS25519_PRIVATE, }; static const uint32_t gs_wrapped_key_value_len_rsa_pub[RSIP_KEY_RSA_NUM] = { + [RSIP_KEY_RSA_1024] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_RSA_1024_PUBLIC, [RSIP_KEY_RSA_2048] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_RSA_2048_PUBLIC, [RSIP_KEY_RSA_3072] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_RSA_3072_PUBLIC, [RSIP_KEY_RSA_4096] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_RSA_4096_PUBLIC, @@ -141,6 +148,7 @@ static const uint32_t gs_wrapped_key_value_len_rsa_pub[RSIP_KEY_RSA_NUM] = static const uint32_t gs_wrapped_key_value_len_rsa_priv[RSIP_KEY_RSA_NUM] = { + [RSIP_KEY_RSA_1024] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_RSA_1024_PRIVATE, [RSIP_KEY_RSA_2048] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_RSA_2048_PRIVATE, [RSIP_KEY_RSA_3072] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_RSA_3072_PRIVATE, [RSIP_KEY_RSA_4096] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_RSA_4096_PRIVATE, @@ -148,7 +156,11 @@ static const uint32_t gs_wrapped_key_value_len_rsa_priv[RSIP_KEY_RSA_NUM] = static const uint32_t gs_wrapped_key_value_len_hmac[RSIP_KEY_HMAC_NUM] = { + [RSIP_KEY_HMAC_SHA1] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_HMAC_SHA1, + [RSIP_KEY_HMAC_SHA224] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_HMAC_SHA224, [RSIP_KEY_HMAC_SHA256] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_HMAC_SHA256, + [RSIP_KEY_HMAC_SHA384] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_HMAC_SHA384, + [RSIP_KEY_HMAC_SHA512] = RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_HMAC_SHA512, }; /*********************************************************************************************************************** @@ -219,17 +231,19 @@ const rsip_api_t g_rsip_on_rsip = **********************************************************************************************************************/ /*******************************************************************************************************************//** - * Enables use of Renesas Secure IP functionality.
+ * Enables use of Renesas Secure IP functionality. + * * Implements @ref rsip_api_t::open. - * - * \
- * This API can only be executed in the STATE_INITIAL, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_SUCCESSSTATE_MAIN
OthersNo change
+ * + * @par State transition + * @parblock + * This API can only be executed in **STATE_INITIAL**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |Others |No change | + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -310,17 +324,19 @@ fsp_err_t R_RSIP_Open (rsip_ctrl_t * const p_ctrl, rsip_cfg_t const * const p_cf } /*******************************************************************************************************************//** - * Disables use of Renesas Secure IP functionality.
+ * Disables use of Renesas Secure IP functionality. + * * Implements @ref rsip_api_t::close. * - * \
- * This API can be executed in except STATE_INITIAL, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_SUCCESSSTATE_INITIAL
OthersNo change
+ * @par State transition + * @parblock + * This API can be executed in **except STATE_INITIAL**, and causes state transition. + * + * |Return value|Next state | + * |------------|-------------| + * |FSP_SUCCESS |STATE_INITIAL| + * |Others |No change | + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -363,11 +379,12 @@ fsp_err_t R_RSIP_Close (rsip_ctrl_t * const p_ctrl) } /*******************************************************************************************************************//** - * Generates a 128-bit random number.
+ * Generates a 128-bit random number. + * * Implements @ref rsip_api_t::randomNumberGenerate. * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -392,25 +409,20 @@ fsp_err_t R_RSIP_RandomNumberGenerate (rsip_ctrl_t * const p_ctrl, uint8_t * con } /*******************************************************************************************************************//** - * Generate a wrapped symmetric key from a random number. + * Generates a wrapped symmetric key from a random number. * In this API, user key input is unnecessary. - * By encrypting data using the wrapped key is output by this API, dead copying of data can be prevented.
- * Implements @ref rsip_api_t::keyGenerate. + * By encrypting data using the wrapped key is output by this API, dead copying of data can be prevented. * - * \ - * @arg Valid key types. + * Implements @ref rsip_api_t::keyGenerate. * - * - * - *
key_typeRSIP_KEY_TYPE_AES_128
- * RSIP_KEY_TYPE_AES_256
- * RSIP_KEY_TYPE_XTS_AES_128
- * RSIP_KEY_TYPE_XTS_AES_256
- * RSIP_KEY_TYPE_HMAC_SHA256 - *
+ * @par Conditions + * Argument key_type must be one of the following: + * - @ref RSIP_KEY_TYPE_AES_128, @ref RSIP_KEY_TYPE_AES_256 + * - @ref RSIP_KEY_TYPE_XTS_AES_128, @ref RSIP_KEY_TYPE_XTS_AES_256 + * - @ref RSIP_KEY_TYPE_HMAC_SHA256, @ref RSIP_KEY_TYPE_HMAC_SHA384, @ref RSIP_KEY_TYPE_HMAC_SHA512 * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -422,7 +434,7 @@ fsp_err_t R_RSIP_RandomNumberGenerate (rsip_ctrl_t * const p_ctrl, uint8_t * con * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. * - * @sa Section @ref r-rsip-key-management "Key Management" + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_KeyGenerate (rsip_ctrl_t * const p_ctrl, rsip_key_type_t const key_type, @@ -454,7 +466,7 @@ fsp_err_t R_RSIP_KeyGenerate (rsip_ctrl_t * const p_ctrl, { case RSIP_RET_PASS: { - p_wrapped_key->alg = (uint8_t) r_rsip_key_type_to_alg(key_type); + p_wrapped_key->alg = r_rsip_key_type_to_alg(key_type); p_wrapped_key->subtype = r_rsip_key_type_to_subtype(key_type); err = FSP_SUCCESS; @@ -477,25 +489,18 @@ fsp_err_t R_RSIP_KeyGenerate (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Generate a wrapped asymmetric key pair from a random number. In this API, user key input is unnecessary. - * By encrypting data using the wrapped key is output by this API, dead copying of data can be prevented.
- * Implements @ref rsip_api_t::keyPairGenerate. + * Generates a wrapped asymmetric key pair from a random number. In this API, user key input is unnecessary. + * By encrypting data using the wrapped key is output by this API, dead copying of data can be prevented. * - * \ - * @arg Valid key pair types. + * Implements @ref rsip_api_t::keyPairGenerate. * - * - * - *
key_pair_typeRSIP_KEY_PAIR_TYPE_ECC_SECP256R1
- * RSIP_KEY_PAIR_TYPE_ECC_SECP384R1
- * RSIP_KEY_PAIR_TYPE_ECC_SECP521R1
- * RSIP_KEY_PAIR_TYPE_RSA_2048
- * RSIP_KEY_PAIR_TYPE_RSA_3072
- * RSIP_KEY_PAIR_TYPE_RSA_4096 - *
+ * @par Conditions + * Argument key_pair_type must be one of the following: + * - @ref RSIP_KEY_PAIR_TYPE_ECC_SECP256R1, @ref RSIP_KEY_PAIR_TYPE_ECC_SECP384R1, @ref RSIP_KEY_PAIR_TYPE_ECC_SECP521R1, + * - @ref RSIP_KEY_PAIR_TYPE_RSA_2048, @ref RSIP_KEY_PAIR_TYPE_RSA_3072, @ref RSIP_KEY_PAIR_TYPE_RSA_4096 * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -507,7 +512,7 @@ fsp_err_t R_RSIP_KeyGenerate (rsip_ctrl_t * const p_ctrl, * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. * - * @sa Section @ref r-rsip-key-management "Key Management" + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_KeyPairGenerate (rsip_ctrl_t * const p_ctrl, rsip_key_pair_type_t const key_pair_type, @@ -541,9 +546,9 @@ fsp_err_t R_RSIP_KeyPairGenerate (rsip_ctrl_t * const p_ctrl, { case RSIP_RET_PASS: { - p_wrapped_public_key->alg = (uint8_t) r_rsip_key_pair_type_to_public_alg(key_pair_type); + p_wrapped_public_key->alg = r_rsip_key_pair_type_to_public_alg(key_pair_type); p_wrapped_public_key->subtype = r_rsip_key_pair_type_to_subtype(key_pair_type); - p_wrapped_private_key->alg = (uint8_t) r_rsip_key_pair_type_to_private_alg(key_pair_type); + p_wrapped_private_key->alg = r_rsip_key_pair_type_to_private_alg(key_pair_type); p_wrapped_private_key->subtype = r_rsip_key_pair_type_to_subtype(key_pair_type); err = FSP_SUCCESS; @@ -566,11 +571,12 @@ fsp_err_t R_RSIP_KeyPairGenerate (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Decrypt the encrypted user key with Key Update Key (KUK) and wrap it with the Hardware Unique Key (HUK).
+ * Decrypts an encrypted user key with Key Update Key (KUK) and wrap it with the Hardware Unique Key (HUK). + * * Implements @ref rsip_api_t::encryptedKeyWrap. * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -583,7 +589,7 @@ fsp_err_t R_RSIP_KeyPairGenerate (rsip_ctrl_t * const p_ctrl, * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. * - * @sa Section @ref r-rsip-key-management "Key Management" + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms" **********************************************************************************************************************/ fsp_err_t R_RSIP_EncryptedKeyWrap (rsip_ctrl_t * const p_ctrl, rsip_key_update_key_t const * const p_key_update_key, @@ -612,8 +618,8 @@ fsp_err_t R_RSIP_EncryptedKeyWrap (rsip_ctrl_t * const p_ctrl, /* Check state */ FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); - /* Store KUK */ - r_rsip_kuk_store(p_key_update_key->value); + /* Set KUK */ + r_rsip_kuk_set(p_key_update_key->value); /* Call primitive (cast to match the argument type with the primitive function) */ rsip_ret_t rsip_ret = @@ -627,7 +633,7 @@ fsp_err_t R_RSIP_EncryptedKeyWrap (rsip_ctrl_t * const p_ctrl, { case RSIP_RET_PASS: { - p_wrapped_key->alg = (uint8_t) r_rsip_key_type_to_alg(key_type); + p_wrapped_key->alg = r_rsip_key_type_to_alg(key_type); p_wrapped_key->subtype = r_rsip_key_type_to_subtype(key_type); err = FSP_SUCCESS; @@ -693,8 +699,6 @@ fsp_err_t R_RSIP_EncryptedKeyWrap (rsip_ctrl_t * const p_ctrl, * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. - * - * @sa Section @ref r-rsip-key-management "Key Management" **********************************************************************************************************************/ fsp_err_t R_RSIP_RFC3394_KeyWrap (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_kek, @@ -714,7 +718,7 @@ fsp_err_t R_RSIP_RFC3394_KeyWrap (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_ALG_AES == p_wrapped_kek->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ - FSP_ERROR_RETURN(g_func.p_rfc3394_key_wrap[p_wrapped_kek->subtype], FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_rfc3394_key_wrap[p_wrapped_kek->subtype], FSP_ERR_NOT_ENABLED); #endif /* Check state */ @@ -723,10 +727,10 @@ fsp_err_t R_RSIP_RFC3394_KeyWrap (rsip_ctrl_t * const p_ctrl, /* Call primitive (cast to match the argument type with the primitive function) */ rsip_key_type_t key_type = (rsip_key_type_t)RSIP_PRV_KEY_TYPE(p_wrapped_target_key->alg, p_wrapped_target_key->subtype); rsip_ret_t rsip_ret = - g_func.p_rfc3394_key_wrap[p_wrapped_kek->subtype]((const uint32_t *) p_wrapped_kek->value, - key_type, - (const uint32_t *) p_wrapped_target_key->value, - (uint32_t *) p_rfc3394_wrapped_target_key); + gp_func_rfc3394_key_wrap[p_wrapped_kek->subtype]((const uint32_t *) p_wrapped_kek->value, + key_type, + (const uint32_t *) p_wrapped_target_key->value, + (uint32_t *) p_rfc3394_wrapped_target_key); /* Check error */ fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; @@ -803,8 +807,6 @@ fsp_err_t R_RSIP_RFC3394_KeyWrap (rsip_ctrl_t * const p_ctrl, * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. - * - * @sa Section @ref r-rsip-key-management "Key Management" **********************************************************************************************************************/ fsp_err_t R_RSIP_RFC3394_KeyUnwrap (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_kek, @@ -825,7 +827,7 @@ fsp_err_t R_RSIP_RFC3394_KeyUnwrap (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_ALG_AES == p_wrapped_kek->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ - FSP_ERROR_RETURN(g_func.p_rfc3394_key_unwrap[p_wrapped_kek->subtype], FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_rfc3394_key_unwrap[p_wrapped_kek->subtype], FSP_ERR_NOT_ENABLED); #endif /* Check state */ @@ -833,10 +835,10 @@ fsp_err_t R_RSIP_RFC3394_KeyUnwrap (rsip_ctrl_t * const p_ctrl, /* Call primitive (cast to match the argument type with the primitive function) */ rsip_ret_t rsip_ret = - g_func.p_rfc3394_key_unwrap[p_wrapped_kek->subtype]((const uint32_t *) p_wrapped_kek->value, - key_type, - (const uint32_t *) p_rfc3394_wrapped_target_key, - (uint32_t *) p_wrapped_target_key->value); + gp_func_rfc3394_key_unwrap[p_wrapped_kek->subtype]((const uint32_t *) p_wrapped_kek->value, + key_type, + (const uint32_t *) p_rfc3394_wrapped_target_key, + (uint32_t *) p_wrapped_target_key->value); /* Check error */ fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; @@ -844,7 +846,7 @@ fsp_err_t R_RSIP_RFC3394_KeyUnwrap (rsip_ctrl_t * const p_ctrl, { case RSIP_RET_PASS: { - p_wrapped_target_key->alg = (uint8_t) r_rsip_key_type_to_alg(key_type); + p_wrapped_target_key->alg = r_rsip_key_type_to_alg(key_type); p_wrapped_target_key->subtype = r_rsip_key_type_to_subtype(key_type); err = FSP_SUCCESS; @@ -879,19 +881,23 @@ fsp_err_t R_RSIP_RFC3394_KeyUnwrap (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * This function provides the ability to construct structure data "rsip_wrapped_key_t" from injected key data. - * The value of injected key is not validated in this API. Refer "Key Size Table" for supported key types.
+ * Generates structure data "rsip_wrapped_key_t" from injected key value. + * Refer "Key Size Table" for supported key types. + * * Implements @ref rsip_api_t::injectedKeyImport. * - * \
- * This API can be executed in any state including STATE_INITIAL, and there are no state transitions. + * @par State transition + * This API can be executed in **any state** including STATE_INITIAL, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_UNSUPPORTED Selected key type is not supported. * @retval FSP_ERR_INVALID_SIZE Buffer length is too short. * - * @sa Section @ref r-rsip-key-management "Key Management" + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms" + * + * @note Injected key value is not validated in this API. + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_InjectedKeyImport (rsip_key_type_t const key_type, uint8_t const * const p_injected_key, @@ -917,7 +923,7 @@ fsp_err_t R_RSIP_InjectedKeyImport (rsip_key_type_t const key_type, } else { - p_wrapped_key->alg = (uint8_t) r_rsip_key_type_to_alg(key_type); + p_wrapped_key->alg = r_rsip_key_type_to_alg(key_type); p_wrapped_key->subtype = r_rsip_key_type_to_subtype(key_type); memcpy(p_wrapped_key->value, p_injected_key, len); @@ -928,43 +934,35 @@ fsp_err_t R_RSIP_InjectedKeyImport (rsip_key_type_t const key_type, } /*******************************************************************************************************************//** - * Exports public key parameters from a wrapped key.
+ * Exports public key parameters from a wrapped key. + * * Implements @ref rsip_api_t::publicKeyExport. * - * \
- * @arg The key type of p_wrapped_public_key must be RSIP_KEY_TYPE_ECC_xxx_PUBLIC or RSIP_KEY_TYPE_RSA_xxx_PUBLIC - * @arg For ECC public keys, raw_public_key has QX placed first and QY placed after that. - * @arg For RSA public keys, raw_public_key has N placed first and E placed after that. - * @arg The value location of each elements in public key is shown in below: - * - * - * - * - * - * - * - * - * - *
ECC bit lengthQX locationQY location
192(*)024
224(*)028
256032
384048
512(*)064
521(*)066
+ * Relative position of each elements in p_raw_public_key is shown in below: + * - ECC (RSIP_KEY_TYPE_ECC_*) : + * Qx placed first and Qy placed after that. + * |bit length|Qx|Qy| + * |----------|--|--| + * |256 |0 |32| + * |384 |0 |48| + * |521 |0 |66| * - * - * - * - * - * - * - * - *
RSA bit lengthN locationE location
1024(*)0128
20480256
30720384
40960512
- * (*) These bit lengths are not supported in V.5.2.0. + * - RSA (RSIP_KEY_TYPE_RSA_*) : n placed first and e placed after that. + * |modulus|n|e | + * |-------|-|---| + * |1024 |0|128| + * |2048 |0|256| + * |3072 |0|384| + * |4096 |0|512| * - * \
- * This API can be executed in any state including STATE_INITIAL, and there are no state transitions. + * @par State transition + * This API can be executed in **any state** including STATE_INITIAL, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. * - * @sa Section @ref r-rsip-key-management "Key Management" + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_PublicKeyExport (rsip_wrapped_key_t const * const p_wrapped_public_key, uint8_t * const p_raw_public_key) @@ -1043,7 +1041,7 @@ fsp_err_t r_rsip_random_number_generate (rsip_ctrl_t * const p_ctrl, uint8_t * c FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); /* Call primitive (cast to match the argument type with the primitive function) */ - rsip_ret_t rsip_ret = g_func.p_rng((uint32_t *) p_random); + rsip_ret_t rsip_ret = gp_func_rng((uint32_t *) p_random); /* Check error */ fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; @@ -1074,35 +1072,42 @@ fsp_err_t r_rsip_random_number_generate (rsip_ctrl_t * const p_ctrl, uint8_t * c * Private Functions **********************************************************************************************************************/ +/*******************************************************************************************************************//** + * Select primitive function of key generation from key type. + * + * @param[in] key_type Key type. + * + * @return Pointer to function. + ***********************************************************************************************************************/ static rsip_func_key_generate_t select_func_key_generate (rsip_key_type_t key_type) { - rsip_func_key_generate_t ret = NULL; - rsip_alg_t alg = r_rsip_key_type_to_alg(key_type); - uint32_t subtype = r_rsip_key_type_to_subtype(key_type); + rsip_func_key_generate_t ret = NULL; + uint8_t alg = r_rsip_key_type_to_alg(key_type); + uint8_t subtype = r_rsip_key_type_to_subtype(key_type); switch (alg) { case RSIP_ALG_AES: { - ret = g_func.p_key_generate_aes[subtype]; + ret = gp_func_key_generate_aes[subtype]; break; } case RSIP_ALG_XTS_AES: { - ret = g_func.p_key_generate_xts_aes[subtype]; + ret = gp_func_key_generate_xts_aes[subtype]; break; } case RSIP_ALG_CHACHA: { - ret = g_func.p_key_generate_chacha[subtype]; + ret = gp_func_key_generate_chacha[subtype]; break; } case RSIP_ALG_HMAC: { - ret = g_func.p_key_generate_hmac[subtype]; + ret = gp_func_key_generate_hmac[subtype]; break; } @@ -1115,23 +1120,30 @@ static rsip_func_key_generate_t select_func_key_generate (rsip_key_type_t key_ty return ret; } +/*******************************************************************************************************************//** + * Select primitive function of key pair generation from key pair type. + * + * @param[in] key_pair_type Key pair type. + * + * @return Pointer to function. + ***********************************************************************************************************************/ static rsip_func_key_pair_generate_t select_func_key_pair_generate (rsip_key_pair_type_t key_pair_type) { rsip_func_key_pair_generate_t ret = NULL; - rsip_alg_t alg = r_rsip_key_pair_type_to_public_alg(key_pair_type); - uint32_t subtype = r_rsip_key_pair_type_to_subtype(key_pair_type); + uint8_t alg = r_rsip_key_pair_type_to_public_alg(key_pair_type); + uint8_t subtype = r_rsip_key_pair_type_to_subtype(key_pair_type); switch (alg) { case RSIP_ALG_ECC_PUBLIC: { - ret = g_func.p_key_pair_generate_ecc[subtype]; + ret = gp_func_key_pair_generate_ecc[subtype]; break; } case RSIP_ALG_RSA_PUBLIC: { - ret = g_func.p_key_pair_generate_rsa[subtype]; + ret = gp_func_key_pair_generate_rsa[subtype]; break; } @@ -1144,59 +1156,66 @@ static rsip_func_key_pair_generate_t select_func_key_pair_generate (rsip_key_pai return ret; } +/*******************************************************************************************************************//** + * Select primitive function of encrypted key wrapping from key type. + * + * @param[in] key_type Key type. + * + * @return Pointer to function. + ***********************************************************************************************************************/ static rsip_func_encrypted_key_wrap_t select_func_encrypted_key_wrap (rsip_key_type_t key_type) { rsip_func_encrypted_key_wrap_t ret = NULL; - rsip_alg_t alg = r_rsip_key_type_to_alg(key_type); - uint32_t subtype = r_rsip_key_type_to_subtype(key_type); + uint8_t alg = r_rsip_key_type_to_alg(key_type); + uint8_t subtype = r_rsip_key_type_to_subtype(key_type); switch (alg) { case RSIP_ALG_AES: { - ret = g_func.p_encrypted_key_wrap_aes[subtype]; + ret = gp_func_encrypted_key_wrap_aes[subtype]; break; } case RSIP_ALG_XTS_AES: { - ret = g_func.p_encrypted_key_wrap_xts_aes[subtype]; + ret = gp_func_encrypted_key_wrap_xts_aes[subtype]; break; } case RSIP_ALG_CHACHA: { - ret = g_func.p_encrypted_key_wrap_chacha[subtype]; + ret = gp_func_encrypted_key_wrap_chacha[subtype]; break; } case RSIP_ALG_ECC_PUBLIC: { - ret = g_func.p_encrypted_key_wrap_ecc_pub[subtype]; + ret = gp_func_encrypted_key_wrap_ecc_pub[subtype]; break; } case RSIP_ALG_ECC_PRIVATE: { - ret = g_func.p_encrypted_key_wrap_ecc_priv[subtype]; + ret = gp_func_encrypted_key_wrap_ecc_priv[subtype]; break; } case RSIP_ALG_RSA_PUBLIC: { - ret = g_func.p_encrypted_key_wrap_rsa_pub[subtype]; + ret = gp_func_encrypted_key_wrap_rsa_pub[subtype]; break; } case RSIP_ALG_RSA_PRIVATE: { - ret = g_func.p_encrypted_key_wrap_rsa_priv[subtype]; + ret = gp_func_encrypted_key_wrap_rsa_priv[subtype]; break; } case RSIP_ALG_HMAC: { - ret = g_func.p_encrypted_key_wrap_hmac[subtype]; + ret = gp_func_encrypted_key_wrap_hmac[subtype]; break; } @@ -1209,11 +1228,18 @@ static rsip_func_encrypted_key_wrap_t select_func_encrypted_key_wrap (rsip_key_t return ret; } +/*******************************************************************************************************************//** + * Output wrapped key size from key type. + * + * @param[in] key_type Key type. + * + * @return Byte size of key type. + ***********************************************************************************************************************/ static uint32_t get_wrapped_key_size (rsip_key_type_t key_type) { - uint32_t ret = 0; - rsip_alg_t alg = r_rsip_key_type_to_alg(key_type); - uint32_t subtype = r_rsip_key_type_to_subtype(key_type); + uint32_t ret = 0; + uint8_t alg = r_rsip_key_type_to_alg(key_type); + uint8_t subtype = r_rsip_key_type_to_subtype(key_type); switch (alg) { @@ -1229,12 +1255,6 @@ static uint32_t get_wrapped_key_size (rsip_key_type_t key_type) break; } - case RSIP_ALG_CHACHA: - { - ret = gs_wrapped_key_value_len_chacha[subtype]; - break; - } - case RSIP_ALG_ECC_PUBLIC: { ret = gs_wrapped_key_value_len_ecc_pub[subtype]; diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_aes.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_aes.c similarity index 87% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_aes.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_aes.c index 93b91a936..63cf0dd0e 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_aes.c +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_aes.c @@ -28,18 +28,18 @@ static fsp_err_t aes_init(rsip_ctrl_t * p_ctrl, const rsip_wrapped_key_t * p_wrapped_key, const uint8_t * p_initial_vector); static fsp_err_t aes_update(rsip_ctrl_t * p_ctrl, const uint8_t * p_input, uint8_t * p_output, uint32_t input_length); -static fsp_err_t aes_final(rsip_ctrl_t * p_ctrl); +static fsp_err_t aes_finish(rsip_ctrl_t * p_ctrl); static fsp_err_t xts_init(rsip_ctrl_t * p_ctrl, rsip_aes_cipher_mode_t mode, const rsip_wrapped_key_t * p_wrapped_key, const uint8_t * p_initial_vector); static fsp_err_t xts_update(rsip_ctrl_t * p_ctrl, const uint8_t * p_input, uint8_t * p_output, uint32_t input_length); -static fsp_err_t xts_final(rsip_ctrl_t * p_ctrl); -static fsp_err_t xts_final_primitive(rsip_func_subset_aes_xts_t * p_func, - const uint8_t * p_input, - uint8_t * p_output, - uint32_t input_length); +static fsp_err_t xts_finish(rsip_ctrl_t * p_ctrl); +static fsp_err_t xts_finish_primitive(rsip_func_subset_aes_xts_t * p_func, + const uint8_t * p_input, + uint8_t * p_output, + uint32_t input_length); static fsp_err_t gcm_init(rsip_ctrl_t * p_ctrl, rsip_aes_aead_mode_t mode, @@ -120,22 +120,40 @@ static void ccm_format(const uint8_t * nonce, **********************************************************************************************************************/ /*******************************************************************************************************************//** - * Set parameters of AES cipher.
- * Implements @ref rsip_api_t::aesCipherInit. + * Starts AES cipher operation in confidentiality mode (ECB/CBC/CTR) or XTS mode. * - * \ - * @arg p_initial_vector is not required for ECB mode. - * @arg p_initial_vector is IV for CBC mode or XTS mode. - * @arg p_initial_vector is nonce for CTR mode. + * Implements @ref rsip_api_t::aesCipherInit. * - * \
- * This API can only be executed in the STATE_MAIN, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_SUCCESSSTATE_AES
OthersNo change
+ * @par Conditions + * @parblock + * Key type of p_wrapped_key must be one of the following: + * - @ref RSIP_KEY_TYPE_AES_128, @ref RSIP_KEY_TYPE_AES_256 + * - @ref RSIP_KEY_TYPE_XTS_AES_128, @ref RSIP_KEY_TYPE_XTS_AES_256 + * + * Argument mode must be the following: + * - AES key + * - @ref RSIP_AES_CIPHER_MODE_ECB_ENC, @ref RSIP_AES_CIPHER_MODE_ECB_DEC + * - @ref RSIP_AES_CIPHER_MODE_CBC_ENC, @ref RSIP_AES_CIPHER_MODE_CBC_DEC + * - @ref RSIP_AES_CIPHER_MODE_CTR + * - XTS-AES key + * - @ref RSIP_AES_CIPHER_MODE_XTS_ENC, @ref RSIP_AES_CIPHER_MODE_XTS_DEC + * + * Argument p_initial_vector must be the following: + * - [ECB] Not used + * - [CBC] Raw initial vector + * - [CTR] Raw nonce + * - [XTS] Raw initial vector + * @endparblock + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_AES | + * |Others |No change | + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -148,6 +166,8 @@ static void ccm_format(const uint8_t * nonce, * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_AES_Cipher_Init (rsip_ctrl_t * const p_ctrl, rsip_aes_cipher_mode_t const mode, @@ -202,34 +222,33 @@ fsp_err_t R_RSIP_AES_Cipher_Init (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Encrypts plaintext.
+ * Encrypts plaintext or decrypts ciphertext. + * * Implements @ref rsip_api_t::aesCipherUpdate. * - * \ - * @arg Requires prerequisite that R_RSIP_AES_Cipher_Init or R_RSIP_AES_Cipher_Update results in FSP_SUCCESS. - * @arg The length is as follows: - * - * - * - * - * - * - *
length
ECB,CBC,CTRMust be 0 or a multiple of 16.
XTSMust be 0 or greater than or equal to 16.
- * After an integer not divisible by 16 is input, update will no longer be able to execute.
- * - * \
- * This API can only be executed in the STATE_AES, and the state after execution changes as follows depending on the return value. - * - * - * - * - *
Return ValueState after execution
AnyNo change
+ * @par Conditions + * Argument length must be the following: + * - [ECB][CBC][CTR] 0 or a multiple of 16. + * - [XTS] 0 or greater than or equal to 16. + * + * @par Output length + * Output length to p_output is `length`. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_AES**, and does not cause any state transitions. + * + * In XTS mode, if once an integer other than 0 or a multiple of 16 is input, this API can no longer be called. + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. * @retval FSP_ERR_INVALID_SIZE Input length is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. **********************************************************************************************************************/ fsp_err_t R_RSIP_AES_Cipher_Update (rsip_ctrl_t * const p_ctrl, uint8_t const * const p_input, @@ -275,23 +294,29 @@ fsp_err_t R_RSIP_AES_Cipher_Update (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Finalize AES operation.
+ * Finishes AES operation. + * * Implements @ref rsip_api_t::aesCipherFinish. * - * \
- * This API can only be executed in the STATE_AES, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_ERR_ASSERTION
FSP_ERR_NOT_OPEN
FSP_ERR_INVALID_STATE		No change
OthersSTATE_MAIN
+ * @par State transition + * @parblock + * This API can only be executed in **STATE_AES**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. - * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. **********************************************************************************************************************/ fsp_err_t R_RSIP_AES_Cipher_Finish (rsip_ctrl_t * const p_ctrl) @@ -310,7 +335,7 @@ fsp_err_t R_RSIP_AES_Cipher_Finish (rsip_ctrl_t * const p_ctrl) /* AES-ECB, AES-CBC, AES-CTR */ case RSIP_STATE_AES_CIPHER: { - err = aes_final(p_ctrl); + err = aes_finish(p_ctrl); break; } @@ -318,7 +343,7 @@ fsp_err_t R_RSIP_AES_Cipher_Finish (rsip_ctrl_t * const p_ctrl) case RSIP_STATE_AES_XTS_UPDATE: case RSIP_STATE_AES_XTS_FINISH: { - err = xts_final(p_ctrl); + err = xts_finish(p_ctrl); break; } @@ -332,25 +357,43 @@ fsp_err_t R_RSIP_AES_Cipher_Finish (rsip_ctrl_t * const p_ctrl) } /*******************************************************************************************************************//** - * Prepares an AES-AEAD function.
+ * Starts AES AEAD function. + * * Implements @ref rsip_api_t::aesAeadInit. * - * \ - * @arg The key type of p_wrapped_key must be RSIP_KEY_TYPE_AES_xxx. + * @par Conditions + * @parblock + * Key type of p_wrapped_key must be one of the following: + * - @ref RSIP_KEY_TYPE_AES_128 + * - @ref RSIP_KEY_TYPE_AES_256 + * + * Argument mode accepts any member of enumeration @ref rsip_aes_aead_mode_t. + * + * Argument nonce_length must be the following: + * - [GCM] Any length is accepted, but 12 bytes is generally recommended. + * - [CCM] 7 to 13 bytes. + * @endparblock + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. * - * \
- * This API can only be executed in the STATE_MAIN, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_SUCCESSSTATE_AES_AEAD
OthersNo change
+ * |Return value|Next state | + * |------------|--------------| + * |FSP_SUCCESS |STATE_AES_AEAD| + * |Others |No change | + * + * The next callable API functions in STATE_AES_AEAD are as below. + * - [GCM] R_RSIP_AES_AEAD_AADUpdate(), R_RSIP_AES_AEAD_Update(), R_RSIP_AES_AEAD_Finish() (encryption), + * R_RSIP_AES_AEAD_Verify() (decryption) + * - [CCM] R_RSIP_AES_AEAD_LengthsSet() + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_INVALID_SIZE nonce_length is illegal. * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. * @retval FSP_ERR_INVALID_ARGUMENT Input key type is illegal. * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. @@ -358,6 +401,8 @@ fsp_err_t R_RSIP_AES_Cipher_Finish (rsip_ctrl_t * const p_ctrl) * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_AES_AEAD_Init (rsip_ctrl_t * const p_ctrl, rsip_aes_aead_mode_t mode, @@ -407,33 +452,35 @@ fsp_err_t R_RSIP_AES_AEAD_Init (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Set text and tag lengths for specific mode.
+ * Sets text and tag lengths for CCM mode. + * * Implements @ref rsip_api_t::aesAeadLengthsSet. * - * \ - * @arg Requires prerequisite that R_RSIP_AES_AEAD_Init results in FSP_SUCCESS. - * @arg The lengths are as follows: - * - * - * - * - *
total_aad_lengthMust be 110 or less.
tag_lengthThe following values are allowed
4, 6, 8, 10, 12, 14, 16
+ * @par Conditions + * @parblock + * Argument total_aad_length must be equal to the length of AAD and must be 110 or less. + * + * Argument total_test_length must be equal to the length of the plaintext or ciphertext. * - * \
- * This API can only be executed in the STATE_AES_AEAD, and there are no state transitions.
- * However, this function can only be called once.
+ * Argument tag_length must be 4, 6, 8, 10, 12, 14, or 16. + * @endparblock * - * \
- * This API must be called directly after executing R_RSIP_AES_AEAD_Init API.
+ * @par State transition + * @parblock + * This API can only be executed in **STATE_AES_AEAD**, and does not cause any state transitions. * - * \
- * This API must NOT be called. Each input length is indeterminate and output tag length is fixed to 16 bytes.
- * If called, FSP_ERR_INVALID_STATE will be returned. + * The next callable API functions in STATE_AES_AEAD are as below. + * - [CCM] R_RSIP_AES_AEAD_AADUpdate() + * @endparblock * * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_SIZE Input length is illegal. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @note In GCM mode, this API must NOT be called. If called, FSP_ERR_INVALID_STATE will be returned. + * AAD length and text length are indeterminate and output tag length is fixed to 16 bytes. **********************************************************************************************************************/ fsp_err_t R_RSIP_AES_AEAD_LengthsSet (rsip_ctrl_t * const p_ctrl, uint32_t const total_aad_length, @@ -468,25 +515,25 @@ fsp_err_t R_RSIP_AES_AEAD_LengthsSet (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Inputs additional authentication data.
- * Implements @ref rsip_api_t::aesAeadAadUpdate. + * Inputs Additional Authentication Data (AAD). * - * \ - * @arg For GCM processing requires prerequisite that R_RSIP_AES_AEAD_Init or R_RSIP_AES_AEAD_AADUpdate results in FSP_SUCCESS. - * @arg For CCM processing requires prerequisite that R_RSIP_AES_AEAD_LengthsSet or R_RSIP_AES_AEAD_AADUpdate results in FSP_SUCCESS. - * @arg This API can be called repeatedly, and in the case of CCM, it must be called at least once. - * @arg This API cannot be called after the R_RSIP_AES_AEAD_Update API has been executed. + * Implements @ref rsip_api_t::aesAeadAadUpdate. * - * \
- * This API can only be executed in the STATE_AES_AEAD, and there are no state transitions. + * @par State transition + * @parblock + * This API can only be executed in **STATE_AES_AEAD**, and does not cause any state transitions. * - * \
- * For GCM processing, this API can be skipped. + * - [GCM] R_RSIP_AES_AEAD_AADUpdate(), R_RSIP_AES_AEAD_Update(), R_RSIP_AES_AEAD_Finish() (encryption), + * R_RSIP_AES_AEAD_Verify() (decryption) + * - [CCM] R_RSIP_AES_AEAD_AADUpdate() (AAD input is not completed), + * R_RSIP_AES_AEAD_Update() (AAD input is completed) + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_INVALID_SIZE aad_length is illegal. * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. @@ -533,27 +580,30 @@ fsp_err_t R_RSIP_AES_AEAD_AADUpdate (rsip_ctrl_t * const p_ctrl, uint8_t const * } /*******************************************************************************************************************//** - * Inputs additional authentication data.
+ * Encrypts plaintext or decrypts ciphertext. + * * Implements @ref rsip_api_t::aesAeadUpdate. * - * \ - * @arg For GCM processing requires prerequisite that R_RSIP_AES_AEAD_Init, R_RSIP_AES_AEAD_AADUpdate, or R_RSIP_AES_AEAD_Update results in FSP_SUCCESS. - * @arg For CCM processing requires prerequisite that R_RSIP_AES_AEAD_AADUpdate or R_RSIP_AES_AEAD_Update results in FSP_SUCCESS. - * @arg In the case of CCM, it must be called at least once. - * @arg This API must be called after all input by R_RSIP_AES_AEAD_AADUpdate API is complete. + * @par Output length + * Output length to p_output (p_output_length) is calculated text that has not yet been output in multiple of 16 bytes. * - * \
- * This API can only be executed in the STATE_AES_AEAD, and there are no state transitions. + * @par State transition + * @parblock + * This API can only be executed in **STATE_AES_AEAD**, and does not cause any state transitions. * - * \
- * GMAC processing can be performed by skipping this API.
- * For detailed usage, refer to the example code. + * - [GCM] R_RSIP_AES_AEAD_Update(), R_RSIP_AES_AEAD_Finish() (encryption), R_RSIP_AES_AEAD_Verify() (decryption) + * - [CCM] R_RSIP_AES_AEAD_Update() (text input is not completed), + * R_RSIP_AES_AEAD_Finish() (text input is completed, encryption), + * R_RSIP_AES_AEAD_Verify() (text input is completed, decryption) + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_SIZE Input length is illegal. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @note In GCM mode, if this API is skipped, GMAC will be calculated. For detailed usage, refer to example code. **********************************************************************************************************************/ fsp_err_t R_RSIP_AES_AEAD_Update (rsip_ctrl_t * const p_ctrl, uint8_t const * const p_input, @@ -567,6 +617,7 @@ fsp_err_t R_RSIP_AES_AEAD_Update (rsip_ctrl_t * const p_ctrl, FSP_ASSERT(p_instance_ctrl); FSP_ASSERT(p_input || (0 == input_length)); FSP_ASSERT(p_output || (0 == input_length)); + FSP_ASSERT(p_output_length); FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); #endif @@ -602,23 +653,31 @@ fsp_err_t R_RSIP_AES_AEAD_Update (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Finalizes an AES-AEAD encryption.
+ * Finalizes an AES AEAD encryption. + * * Implements @ref rsip_api_t::aesAeadFinish. * - * \ - * @arg RSIP_AES_AEAD_MODE_GCM_ENC or RSIP_AES_AEAD_MODE_CCM_ENC must be input as the mode in R_RSIP_AES_AEAD_Init. - * @arg For GCM processing, requires prerequisite that R_RSIP_AES_AEAD_Init, R_RSIP_AES_AEAD_AADUpdate, or R_RSIP_AES_AEAD_Update results in FSP_SUCCESS. - * @arg For CCM processing, requires prerequisite that R_RSIP_AES_AEAD_Update results in FSP_SUCCESS. + * @par Output length + * @parblock + * Output length to p_output (p_output_length) is the remaining calculated text length. + * + * Output length to p_tag as below. + * - [GCM] 16 bytes. + * - [CCM] Input value as tag_length in R_RSIP_AES_AEAD_LengthsSet(). + * @endparblock * - * \
- * This API can be executed in the STATE_AES_AEAD, and the state after execution changes as follows depending on the return value. + * @par State transition + * @parblock + * This API can only be executed in **STATE_AES_AEAD**, and causes state transition. * - * - * - * - * - * - *
Return ValueState after execution
FSP_ERR_ASSERTION
FSP_ERR_NOT_OPEN
FSP_ERR_INVALID_STATE		No change
AnySTATE_MAIN
+ * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -672,27 +731,35 @@ fsp_err_t R_RSIP_AES_AEAD_Finish (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Finalizes an AES-AEAD decryption.
+ * Finalizes an AES AEAD decryption. + * + * If there is 16-byte fractional data indicated by the total data length of the value of p_cipher that was input by + * R_RSIP_AES_GCM_DecryptUpdate(), this API will output the result of decrypting that fractional data to p_cipher. + * Here, the portion that does not reach 16 bytes will be padded with zeros. + * * Implements @ref rsip_api_t::aesAeadVerify. * - * \ - * @arg RSIP_AES_AEAD_MODE_GCM_DEC or RSIP_AES_AEAD_MODE_CCM_DEC must be input as the mode in R_RSIP_AES_AEAD_Init. - * @arg For GCM processing, requires prerequisite that R_RSIP_AES_AEAD_Init, R_RSIP_AES_AEAD_AADUpdate, or R_RSIP_AES_AEAD_Update results in FSP_SUCCESS. - * @arg For CCM processing, requires prerequisite that R_RSIP_AES_AEAD_Update results in FSP_SUCCESS. + * @par Conditions + * Argument tag_length must be as below. + * - [GCM] 1 to 16 bytes. + * - [CCM] Input value as tag_length in R_RSIP_AES_AEAD_LengthsSet(). * - * \
- * This API can be executed in the STATE_AES_AEAD, and the state after execution changes as follows depending on the return value. + * @par Output length + * Output length to p_output (p_output_length) is the remaining calculated text length. * - * - * - * - * - * - *
Return ValueState after execution
FSP_ERR_ASSERTION
FSP_ERR_NOT_OPEN
FSP_ERR_INVALID_STATE		No change
AnySTATE_MAIN
+ * @par State transition + * @parblock + * This API can only be executed in **STATE_AES_AEAD**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock * - * If there is 16-byte fractional data indicated by the total data length of the value of p_cipher that was input by - * R_RSIP_AES_GCM_DecryptUpdate(), this API will output the result of decrypting that fractional data to p_cipher. - * Here, the portion that does not reach 16 bytes will be padded with zeros. * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. @@ -748,28 +815,28 @@ fsp_err_t R_RSIP_AES_AEAD_Verify (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Prepares an AES-MAC generation and verification.
+ * Starts an AES MAC operation. + * * Implements @ref rsip_api_t::aesMacInit. * - * \ - * @arg The key type of p_wrapped_key must be RSIP_KEY_TYPE_AES_xxx. - * @arg The argument mode only supports the feature listed below. - * - * - * - * - *
ModeCorresponding Parameter
CMACRSIP_AES_MAC_MODE_CMAC
- * * GMAC processing can be performed with R_RSIP_AES_AEAD_xxx API.
- * 　 Refer to the desceription about R_RSIP_AES_AEAD_Update() API. - * - * \
- * This API can only be executed in the STATE_MAIN, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_SUCCESSSTATE_AES_MAC
OthersNo change
+ * @par Conditions + * @parblock + * Key type of p_wrapped_key must be one of the following: + * - @ref RSIP_KEY_TYPE_AES_128 + * - @ref RSIP_KEY_TYPE_AES_256 + * + * Argument mode accepts any member of enumeration @ref rsip_aes_aead_mode_t. + * @endparblock + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state | + * |------------|--------------| + * |FSP_SUCCESS |STATE_AES_MAC | + * |Others |No change | + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -781,6 +848,11 @@ fsp_err_t R_RSIP_AES_AEAD_Verify (rsip_ctrl_t * const p_ctrl, * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @note To calculate AES-GMAC, please use not R_RSIP_MAC_*() but R_RSIP_AEAD_*(). + * For detailed usage, refer to example code. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_AES_MAC_Init (rsip_ctrl_t * const p_ctrl, rsip_aes_mac_mode_t const mode, @@ -799,7 +871,7 @@ fsp_err_t R_RSIP_AES_MAC_Init (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_ALG_AES == p_wrapped_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check if the key type is enabled on configuration */ - FSP_ERROR_RETURN(g_func.p_aes_mac[p_wrapped_key->subtype].p_init, FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_aes_cmac[p_wrapped_key->subtype].p_init, FSP_ERR_NOT_ENABLED); #endif /* Check state */ @@ -809,11 +881,11 @@ fsp_err_t R_RSIP_AES_MAC_Init (rsip_ctrl_t * const p_ctrl, r_rsip_handle_reset(&p_instance_ctrl->handle); /* Set primitive */ - p_handle->p_func = &g_func.p_aes_mac[p_wrapped_key->subtype]; + p_handle->p_func = &gp_func_aes_cmac[p_wrapped_key->subtype]; /* Call primitive (cast to match the argument type with the primitive function) */ - rsip_func_subset_aes_mac_t * p_func = (rsip_func_subset_aes_mac_t *) p_handle->p_func; - rsip_ret_t rsip_ret = p_func->p_init((const uint32_t *) p_wrapped_key->value); + rsip_func_subset_aes_cmac_t * p_func = (rsip_func_subset_aes_cmac_t *) p_handle->p_func; + rsip_ret_t rsip_ret = p_func->p_init((const uint32_t *) p_wrapped_key->value); /* Check error */ fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; @@ -850,22 +922,15 @@ fsp_err_t R_RSIP_AES_MAC_Init (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Input message.
+ * Inputs message. + * * Implements @ref rsip_api_t::aesMacUpdate. * * Inside this function, the data that is input by the user is buffered until the input value of p_message exceeds 16 bytes. * If the input value, p_message, is not a multiple of 16 bytes, it will be padded within the function. * - * \ - * @arg Requires prerequisite that R_RSIP_AES_MAC_Init or R_RSIP_AES_MAC_Update results in FSP_SUCCESS. - * - * \
- * This API can only be executed in the STATE_AES_MAC, and the state after execution changes as follows depending on the return value. - * - * - * - * - *
Return ValueState after execution
AnyNo change
+ * @par State transition + * This API can only be executed in **STATE_AES_MAC**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -884,8 +949,8 @@ fsp_err_t R_RSIP_AES_MAC_Update (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); #endif - rsip_aes_cmac_handle_t * p_handle = &p_instance_ctrl->handle.aes_cmac; - rsip_func_subset_aes_mac_t * p_func = (rsip_func_subset_aes_mac_t *) p_handle->p_func; + rsip_aes_cmac_handle_t * p_handle = &p_instance_ctrl->handle.aes_cmac; + rsip_func_subset_aes_cmac_t * p_func = (rsip_func_subset_aes_cmac_t *) p_handle->p_func; /* Check state */ FSP_ERROR_RETURN(RSIP_STATE_AES_CMAC == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); @@ -936,26 +1001,30 @@ fsp_err_t R_RSIP_AES_MAC_Update (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Finalizes an AES-MAC generation.
+ * Outputs AES MAC. + * * Implements @ref rsip_api_t::aesMacSignFinish. * - * \ - * @arg Requires prerequisite that R_RSIP_AES_MAC_Init or R_RSIP_AES_MAC_Update results in FSP_SUCCESS. + * @par Output length + * Output length to p_mac is 16 bytes. * - * \
- * This API can only be executed in the STATE_AES_MAC, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_ERR_ASSERTION
FSP_ERR_NOT_OPEN
FSP_ERR_INVALID_STATE		No change
OthersSTATE_MAIN
+ * @par State transition + * @parblock + * This API can only be executed in **STATE_AES_MAC**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. - * @retval FSP_ERR_INVALID_SIZE Input length is illegal. * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. **********************************************************************************************************************/ @@ -969,8 +1038,8 @@ fsp_err_t R_RSIP_AES_MAC_SignFinish (rsip_ctrl_t * const p_ctrl, uint8_t * const FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); #endif - rsip_aes_cmac_handle_t * p_handle = &p_instance_ctrl->handle.aes_cmac; - rsip_func_subset_aes_mac_t * p_func = (rsip_func_subset_aes_mac_t *) p_handle->p_func; + rsip_aes_cmac_handle_t * p_handle = &p_instance_ctrl->handle.aes_cmac; + rsip_func_subset_aes_cmac_t * p_func = (rsip_func_subset_aes_cmac_t *) p_handle->p_func; /* Check state */ FSP_ERROR_RETURN(RSIP_STATE_AES_CMAC == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); @@ -1023,20 +1092,26 @@ fsp_err_t R_RSIP_AES_MAC_SignFinish (rsip_ctrl_t * const p_ctrl, uint8_t * const } /*******************************************************************************************************************//** - * Finalizes an AES-MAC verification.
+ * Verifies AES MAC. + * * Implements @ref rsip_api_t::aesMacVerifyFinish. * - * \ - * @arg Requires prerequisite that R_RSIP_AES_MAC_Init or R_RSIP_AES_MAC_Update results in FSP_SUCCESS. + * @par Conditions + * Argument mac_length must be as below. + * - [CMAC] 2 to 16 bytes. * - * \
- * This API can only be executed in the STATE_AES_MAC, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_ERR_ASSERTION
FSP_ERR_NOT_OPEN
FSP_ERR_INVALID_STATE
FSP_ERR_INVALID_SIZE		No change
OthersSTATE_MAIN
+ * @par State transition + * @parblock + * This API can only be executed in **STATE_AES_MAC**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -1059,8 +1134,8 @@ fsp_err_t R_RSIP_AES_MAC_VerifyFinish (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); #endif - rsip_aes_cmac_handle_t * p_handle = &p_instance_ctrl->handle.aes_cmac; - rsip_func_subset_aes_mac_t * p_func = (rsip_func_subset_aes_mac_t *) p_handle->p_func; + rsip_aes_cmac_handle_t * p_handle = &p_instance_ctrl->handle.aes_cmac; + rsip_func_subset_aes_cmac_t * p_func = (rsip_func_subset_aes_cmac_t *) p_handle->p_func; /* Check state */ FSP_ERROR_RETURN(RSIP_STATE_AES_CMAC == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); @@ -1147,7 +1222,6 @@ fsp_err_t R_RSIP_AES_MAC_VerifyFinish (rsip_ctrl_t * const p_ctrl, * Prepares an AES-ECB/CBC/CTR. * * @retval FSP_SUCCESS Normal termination. - * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. @@ -1163,7 +1237,7 @@ static fsp_err_t aes_init (rsip_ctrl_t * p_ctrl, { rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; rsip_aes_cipher_handle_t * p_handle = &p_instance_ctrl->handle.aes_cipher; - const rsip_func_subset_aes_cipher_t * p_func = &g_func.p_aes_cipher[p_wrapped_key->subtype]; + const rsip_func_subset_aes_cipher_t * p_func = &gp_func_aes_cipher[p_wrapped_key->subtype]; #if RSIP_CFG_PARAM_CHECKING_ENABLE @@ -1255,7 +1329,6 @@ static fsp_err_t aes_init (rsip_ctrl_t * p_ctrl, * Executes AES-ECB/CBC/CTR encryption and decryption. * * @retval FSP_SUCCESS Normal termination. - * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. * @retval FSP_ERR_INVALID_SIZE Input length is illegal. **********************************************************************************************************************/ @@ -1293,7 +1366,7 @@ static fsp_err_t aes_update (rsip_ctrl_t * p_ctrl, const uint8_t * p_input, uint * * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. **********************************************************************************************************************/ -static fsp_err_t aes_final (rsip_ctrl_t * p_ctrl) +static fsp_err_t aes_finish (rsip_ctrl_t * p_ctrl) { rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; rsip_aes_cipher_handle_t * p_handle = &p_instance_ctrl->handle.aes_cipher; @@ -1334,7 +1407,6 @@ static fsp_err_t aes_final (rsip_ctrl_t * p_ctrl) * Prepares an AES-XTS. * * @retval FSP_SUCCESS Normal termination. - * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. @@ -1351,8 +1423,8 @@ static fsp_err_t xts_init (rsip_ctrl_t * p_ctrl, rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; rsip_aes_cipher_handle_t * p_handle = &p_instance_ctrl->handle.aes_cipher; const rsip_func_subset_aes_xts_t * p_func = (RSIP_AES_CIPHER_MODE_XTS_ENC == mode) ? - &g_func.p_aes_xts_enc[p_wrapped_key->subtype] : &g_func. - p_aes_xts_dec[p_wrapped_key->subtype]; + &gp_func_aes_xts_enc[p_wrapped_key->subtype] : + &gp_func_aes_xts_dec[p_wrapped_key->subtype]; #if RSIP_CFG_PARAM_CHECKING_ENABLE @@ -1410,7 +1482,6 @@ static fsp_err_t xts_init (rsip_ctrl_t * p_ctrl, * Executes AES-XTS encryption and decryption. * * @retval FSP_SUCCESS Normal termination. - * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_INVALID_SIZE Input length is illegal. * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. * @@ -1447,7 +1518,7 @@ static fsp_err_t xts_update (rsip_ctrl_t * p_ctrl, const uint8_t * p_input, uint uint8_t buffer[RSIP_PRV_BYTE_SIZE_AES_BLOCK * 2] = {0}; memcpy(buffer, p_input + block_length, remaining_length); - err = xts_final_primitive(p_func, buffer, p_output + block_length, remaining_length); + err = xts_finish_primitive(p_func, buffer, p_output + block_length, remaining_length); /* After input remaining blocks, final function must be called */ p_instance_ctrl->state = RSIP_STATE_AES_XTS_FINISH; @@ -1465,7 +1536,7 @@ static fsp_err_t xts_update (rsip_ctrl_t * p_ctrl, const uint8_t * p_input, uint * * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. **********************************************************************************************************************/ -static fsp_err_t xts_final (rsip_ctrl_t * p_ctrl) +static fsp_err_t xts_finish (rsip_ctrl_t * p_ctrl) { rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; rsip_aes_cipher_handle_t * p_handle = &p_instance_ctrl->handle.aes_cipher; @@ -1475,7 +1546,7 @@ static fsp_err_t xts_final (rsip_ctrl_t * p_ctrl) if (RSIP_STATE_AES_XTS_UPDATE == p_instance_ctrl->state) { /* If final function have not called (remaining blocks have not been input), Call primitive for empty message */ - err = xts_final_primitive(p_func, NULL, NULL, 0); + err = xts_finish_primitive(p_func, NULL, NULL, 0); } /* Reset handle */ @@ -1495,10 +1566,10 @@ static fsp_err_t xts_final (rsip_ctrl_t * p_ctrl) * * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. **********************************************************************************************************************/ -static fsp_err_t xts_final_primitive (rsip_func_subset_aes_xts_t * p_func, - const uint8_t * p_input, - uint8_t * p_output, - uint32_t input_length) +static fsp_err_t xts_finish_primitive (rsip_func_subset_aes_xts_t * p_func, + const uint8_t * p_input, + uint8_t * p_output, + uint32_t input_length) { uint32_t output_length_bit[1] = { @@ -1539,7 +1610,6 @@ static fsp_err_t xts_final_primitive (rsip_func_subset_aes_xts_t * p_func, * Prepares an AES-GCM. * * @retval FSP_SUCCESS Normal termination. - * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. @@ -1557,8 +1627,8 @@ static fsp_err_t gcm_init (rsip_ctrl_t * p_ctrl, rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; rsip_aes_gcm_handle_t * p_handle = &p_instance_ctrl->handle.aes_gcm; const rsip_func_subset_aes_gcm_t * p_func = (RSIP_AES_AEAD_MODE_GCM_ENC == mode) ? - &g_func.p_aes_gcm_enc[p_wrapped_key->subtype] : &g_func. - p_aes_gcm_dec[p_wrapped_key->subtype]; + &gp_func_aes_gcm_enc[p_wrapped_key->subtype] : + &gp_func_aes_gcm_dec[p_wrapped_key->subtype]; #if RSIP_CFG_PARAM_CHECKING_ENABLE @@ -1582,7 +1652,7 @@ static fsp_err_t gcm_init (rsip_ctrl_t * p_ctrl, }; fsp_err_t err = - gcm_iv_prepare(&g_func.p_aes_cipher[p_wrapped_key->subtype], p_nonce, nonce_length, p_wrapped_key, hashed_ivec); + gcm_iv_prepare(&gp_func_aes_cipher[p_wrapped_key->subtype], p_nonce, nonce_length, p_wrapped_key, hashed_ivec); if (FSP_SUCCESS == err) { @@ -1636,7 +1706,6 @@ static fsp_err_t gcm_init (rsip_ctrl_t * p_ctrl, * Inputs aad and executes encryption and decryption. * * @retval FSP_SUCCESS Normal termination. - * @retval FSP_ERR_ASSERTION A required parameter is NULL. **********************************************************************************************************************/ static fsp_err_t gcm_aad_update (rsip_ctrl_t * p_ctrl, const uint8_t * p_aad, uint32_t aad_length) { @@ -1698,7 +1767,6 @@ static fsp_err_t gcm_aad_update (rsip_ctrl_t * p_ctrl, const uint8_t * p_aad, ui * Inputs aad and executes encryption and decryption. * * @retval FSP_SUCCESS Normal termination. - * @retval FSP_ERR_ASSERTION A required parameter is NULL. **********************************************************************************************************************/ static fsp_err_t gcm_update (rsip_ctrl_t * p_ctrl, uint8_t const * const p_input, @@ -1794,7 +1862,6 @@ static fsp_err_t gcm_update (rsip_ctrl_t * p_ctrl, * @param[out] p_tag Pointer to destination of tag for authentication. The length is 16 bytes. * * @retval FSP_SUCCESS Normal termination. - * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. * * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. @@ -1836,7 +1903,7 @@ static fsp_err_t gcm_finish (rsip_ctrl_t * const p_ctrl, aad_bit_size[1] = bswap_32big(r_rsip_byte_to_bit_convert_lower(p_handle->total_aad_length)); data_bit_size[0] = bswap_32big((r_rsip_byte_to_bit_convert_upper(p_handle->total_length))); data_bit_size[1] = bswap_32big(r_rsip_byte_to_bit_convert_lower(p_handle->total_length)); - *p_output_length = p_handle->total_length; + *p_output_length = p_handle->buffered_length; /* Call primitive (cast to match the argument type with the primitive function) */ rsip_ret_t rsip_ret = @@ -1888,7 +1955,6 @@ static fsp_err_t gcm_finish (rsip_ctrl_t * const p_ctrl, * @param[in] tag_length Byte length of tag. Must be 1 to 16. * * @retval FSP_SUCCESS Normal termination. - * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_INVALID_SIZE tag_length is illegal. * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. * @retval FSP_ERR_CRYPTO_RSIP_AUTHENTICATION Authentication is failed. @@ -1947,8 +2013,8 @@ static fsp_err_t gcm_verify (rsip_ctrl_t * const p_ctrl, aad_bit_size[1] = bswap_32big(r_rsip_byte_to_bit_convert_lower(p_handle->total_aad_length)); data_bit_size[0] = bswap_32big(r_rsip_byte_to_bit_convert_upper(p_handle->total_length)); data_bit_size[1] = bswap_32big(r_rsip_byte_to_bit_convert_lower(p_handle->total_length)); - *p_output_length = p_handle->total_length; tag_length_tmp[0] = bswap_32big(tag_length); + *p_output_length = p_handle->buffered_length; /* Call primitive (cast to match the argument type with the primitive function) */ rsip_ret_t rsip_ret = p_func->p_decryptFinal((uint32_t *) (p_handle->buffer), @@ -2067,8 +2133,8 @@ static fsp_err_t gcm_iv_prepare (const rsip_func_subset_aes_cipher_t * p_func_ae { /* Call primitive (cast to match the argument type with the primitive function) */ rsip_ret = - g_func.p_ghash_compute(hash_subkey, zero, (const uint32_t *) p_initial_vector, hashed_ivec_tmp, - (initial_vector_length / RSIP_PRV_BYTE_SIZE_AES_BLOCK) * sizeof(uint32_t)); + gp_func_ghash_compute(hash_subkey, zero, (const uint32_t *) p_initial_vector, hashed_ivec_tmp, + (initial_vector_length / RSIP_PRV_BYTE_SIZE_AES_BLOCK) * sizeof(uint32_t)); if (RSIP_RET_PASS == rsip_ret) { ivec_length_rest = initial_vector_length % RSIP_PRV_BYTE_SIZE_AES_BLOCK; @@ -2078,11 +2144,11 @@ static fsp_err_t gcm_iv_prepare (const rsip_func_subset_aes_cipher_t * p_func_ae ivec_length_rest); /* Call primitive (cast to match the argument type with the primitive function) */ - rsip_ret = g_func.p_ghash_compute(hash_subkey, - hashed_ivec_tmp, - ivec_tmp, - hashed_ivec_tmp, - RSIP_PRV_BYTE_SIZE_AES_BLOCK / sizeof(uint32_t)); + rsip_ret = gp_func_ghash_compute(hash_subkey, + hashed_ivec_tmp, + ivec_tmp, + hashed_ivec_tmp, + RSIP_PRV_BYTE_SIZE_AES_BLOCK / sizeof(uint32_t)); } } } @@ -2091,11 +2157,11 @@ static fsp_err_t gcm_iv_prepare (const rsip_func_subset_aes_cipher_t * p_func_ae memcpy(ivec_tmp, p_initial_vector, initial_vector_length); /* Call primitive (cast to match the argument type with the primitive function) */ - rsip_ret = g_func.p_ghash_compute(hash_subkey, - zero, - ivec_tmp, - hashed_ivec_tmp, - RSIP_PRV_BYTE_SIZE_AES_BLOCK / sizeof(uint32_t)); + rsip_ret = gp_func_ghash_compute(hash_subkey, + zero, + ivec_tmp, + hashed_ivec_tmp, + RSIP_PRV_BYTE_SIZE_AES_BLOCK / sizeof(uint32_t)); } if (RSIP_RET_PASS == rsip_ret) @@ -2107,11 +2173,11 @@ static fsp_err_t gcm_iv_prepare (const rsip_func_subset_aes_cipher_t * p_func_ae ivec_bit_len[3] = bswap_32big(r_rsip_byte_to_bit_convert_lower(initial_vector_length)); /* Call primitive (cast to match the argument type with the primitive function) */ - rsip_ret = g_func.p_ghash_compute(hash_subkey, - hashed_ivec_tmp, - ivec_bit_len, - p_hashed_ivec, - RSIP_PRV_BYTE_SIZE_AES_BLOCK / sizeof(uint32_t)); + rsip_ret = gp_func_ghash_compute(hash_subkey, + hashed_ivec_tmp, + ivec_bit_len, + p_hashed_ivec, + RSIP_PRV_BYTE_SIZE_AES_BLOCK / sizeof(uint32_t)); } } @@ -2184,7 +2250,7 @@ static void gcm_aad_input_terminate (rsip_instance_ctrl_t * p_instance_ctrl) * Prepares an AES-CCM. * * @retval FSP_SUCCESS Normal termination. - * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. * @retval FSP_ERR_INVALID_SIZE nonce_length is illegal. * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. **********************************************************************************************************************/ @@ -2197,8 +2263,8 @@ static fsp_err_t ccm_init (rsip_ctrl_t * p_ctrl, rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; rsip_aes_ccm_handle_t * p_handle = &p_instance_ctrl->handle.aes_ccm; const rsip_func_subset_aes_ccm_t * p_func = (RSIP_AES_AEAD_MODE_CCM_ENC == mode) ? - &g_func.p_aes_ccm_enc[p_wrapped_key->subtype] : &g_func. - p_aes_ccm_dec[p_wrapped_key->subtype]; + &gp_func_aes_ccm_enc[p_wrapped_key->subtype] : & + gp_func_aes_ccm_dec[p_wrapped_key->subtype]; #if RSIP_CFG_PARAM_CHECKING_ENABLE @@ -2277,8 +2343,7 @@ static fsp_err_t ccm_length_set (rsip_ctrl_t * const p_ctrl, * Inputs aad and executes encryption and decryption. * * @retval FSP_SUCCESS Normal termination. - * @retval FSP_ERR_ASSERTION A required parameter is NULL. - * @retval FSP_ERR_INVALID_SIZE nonce_length is illegal. + * @retval FSP_ERR_INVALID_SIZE aad_length is illegal. * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. * @@ -2395,8 +2460,7 @@ static fsp_err_t ccm_aad_update (rsip_ctrl_t * p_ctrl, const uint8_t * p_aad, ui * Inputs aad and executes encryption and decryption. * * @retval FSP_SUCCESS Normal termination. - * @retval FSP_ERR_ASSERTION A required parameter is NULL. - * @retval FSP_ERR_INVALID_SIZE nonce_length is illegal. + * @retval FSP_ERR_INVALID_SIZE input_length is illegal. **********************************************************************************************************************/ static fsp_err_t ccm_update (rsip_ctrl_t * p_ctrl, uint8_t const * const p_input, @@ -2485,7 +2549,6 @@ static fsp_err_t ccm_update (rsip_ctrl_t * p_ctrl, * @param[out] p_tag Pointer to destination of tag for authentication. The length is 16 bytes. * * @retval FSP_SUCCESS Normal termination. - * @retval FSP_ERR_ASSERTION A required parameter is NULL. * * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. **********************************************************************************************************************/ @@ -2520,7 +2583,7 @@ static fsp_err_t ccm_finish (rsip_ctrl_t * const p_ctrl, case RSIP_RET_PASS: { memcpy(p_output, output_tmp, p_handle->buffered_length); - *p_output_length = p_handle->total_length; + *p_output_length = p_handle->buffered_length; memcpy(p_tag, tag_tmp, p_handle->tag_length); err = FSP_SUCCESS; @@ -2552,9 +2615,9 @@ static fsp_err_t ccm_finish (rsip_ctrl_t * const p_ctrl, * @param[in] tag_length Byte length of tag. Must be 1 to 16. * * @retval FSP_SUCCESS Normal termination. - * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_INVALID_SIZE tag_length is illegal. * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * @retval FSP_ERR_CRYPTO_RSIP_AUTHENTICATION Authentication is failed. * * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. **********************************************************************************************************************/ @@ -2597,7 +2660,7 @@ static fsp_err_t ccm_verify (rsip_ctrl_t * const p_ctrl, case RSIP_RET_PASS: { memcpy(p_output, output_tmp, p_handle->buffered_length); - *p_output_length = p_handle->total_length; + *p_output_length = p_handle->buffered_length; err = FSP_SUCCESS; break; @@ -2609,6 +2672,12 @@ static fsp_err_t ccm_verify (rsip_ctrl_t * const p_ctrl, break; } + case RSIP_RET_AUTH_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_AUTHENTICATION; + break; + } + default: { err = FSP_ERR_CRYPTO_RSIP_FATAL; diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_ecc.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_ecc.c similarity index 74% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_ecc.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_ecc.c index 2ee0979b9..6537e0446 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_ecc.c +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_ecc.c @@ -39,38 +39,54 @@ **********************************************************************************************************************/ /*******************************************************************************************************************//** - * Signs a hashed message. The message hash should be generated in advance.
+ * Generates an ECDSA signature. + * * Implements @ref rsip_api_t::ecdsaSign. * - * \ - * @arg The key type of p_wrapped_private_key must be RSIP_KEY_TYPE_ECC_xxx_PRIVATE. - * @arg This version supports the following key types: - * - * - * - * - * - * - *
Key LengthKey Type
256 bitRSIP_KEY_TYPE_ECC_SECP256R1_PRIVATE
384 bitRSIP_KEY_TYPE_ECC_SECP384R1_PRIVATE
521 bitRSIP_KEY_TYPE_ECC_SECP521R1_PRIVATE
- * @arg The hash value must be computed and passed to the argument p_hash before executing this API.
+ * @par Conditions + * @parblock + * Key type of p_wrapped_private_key must be one of the following: + * - @ref RSIP_KEY_TYPE_ECC_SECP256R1_PRIVATE + * - @ref RSIP_KEY_TYPE_ECC_SECP384R1_PRIVATE + * - @ref RSIP_KEY_TYPE_ECC_SECP521R1_PRIVATE + * + * Message hash p_hash should be computed in advance. * In the case of hash length is less than the key length, padding is required to make it the same as the key length. + * + * For secp521r1 operation, the length of p_hash must be set to 64 bytes. + * + * For secp521r1 operation, the length of the argument p_signature must be set as 132 byte. + * Since 521 bit is not a 8-bit multiple, zero padding is required and the data format is as follows: + * + * + * + * + * + * + * + * + * + * + *
Data Format for secp521r1 (132 byte)
zero padding (7 bit)signature r (521 bit)zero padding (7 bit)signature s (521 bit)
+ * @endparblock * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. - * @retval FSP_ERR_INVALID_ARGUMENT Input key type or mode is illegal. - * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. * @retval FSP_ERR_CRYPTO_RSIP_FAIL @arg Input parameter is illegal. * @arg Signature generation is failed. * * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_ECDSA_Sign (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_private_key, @@ -90,7 +106,7 @@ fsp_err_t R_RSIP_ECDSA_Sign (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_ALG_ECC_PRIVATE == p_wrapped_private_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ - FSP_ERROR_RETURN(g_func.p_ecdsa_sign[p_wrapped_private_key->subtype], FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_ecdsa_sign[p_wrapped_private_key->subtype], FSP_ERR_NOT_ENABLED); #endif /* Check state */ @@ -98,9 +114,9 @@ fsp_err_t R_RSIP_ECDSA_Sign (rsip_ctrl_t * const p_ctrl, /* Call primitive (cast to match the argument type with the primitive function) */ rsip_ret_t rsip_ret = - g_func.p_ecdsa_sign[p_wrapped_private_key->subtype]((const uint32_t *) p_wrapped_private_key->value, - (const uint32_t *) p_hash, - (uint32_t *) p_signature); + gp_func_ecdsa_sign[p_wrapped_private_key->subtype]((const uint32_t *) p_wrapped_private_key->value, + (const uint32_t *) p_hash, + (uint32_t *) p_signature); /* Check error */ fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; @@ -140,38 +156,54 @@ fsp_err_t R_RSIP_ECDSA_Sign (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Verifies a hashed message. The message hash should be generated in advance.
+ * Verifies an ECDSA signature. + * * Implements @ref rsip_api_t::ecdsaVerify. * - * \ - * @arg The key type of p_wrapped_public_key must be RSIP_KEY_TYPE_ECC_xxx_PUBLIC. - * @arg This version supports the following key types: - * - * - * - * - * - * - *
Key LengthKey Type
256 bitRSIP_KEY_TYPE_ECC_SECP256R1_PUBLIC
384 bitRSIP_KEY_TYPE_ECC_SECP384R1_PUBLIC
521 bitRSIP_KEY_TYPE_ECC_SECP521R1_PUBLIC
- * @arg The hash value must be computed and passed to the argument p_hash before executing this API.
+ * @par Conditions + * @parblock + * Key type of p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_ECC_SECP256R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_SECP384R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_SECP521R1_PUBLIC + * + * Message hash p_hash should be computed in advance. * In the case of hash length is less than the key length, padding is required to make it the same as the key length. + * + * For secp521r1 operation, the length of p_hash must be set to 64 bytes. + * + * For secp521r1 operation, the length of the argument p_signature must be set as 132 byte. + * Since 521 bit is not a 8-bit multiple, zero padding is required and the data format is as follows: + * + * + * + * + * + * + * + * + * + * + *
Data Format for secp521r1 (132 byte)
zero padding (7 bit)signature r (521 bit)zero padding (7 bit)signature s (521 bit)
+ * @endparblock * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. - * @retval FSP_ERR_INVALID_ARGUMENT Input key type or mode is illegal. - * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. * @retval FSP_ERR_CRYPTO_RSIP_FAIL @arg Input parameter is illegal. * @arg Signature verification is failed. * * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_ECDSA_Verify (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_public_key, @@ -191,7 +223,7 @@ fsp_err_t R_RSIP_ECDSA_Verify (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_ALG_ECC_PUBLIC == p_wrapped_public_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ - FSP_ERROR_RETURN(g_func.p_ecdsa_verify[p_wrapped_public_key->subtype], FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_ecdsa_verify[p_wrapped_public_key->subtype], FSP_ERR_NOT_ENABLED); #endif /* Check state */ @@ -199,9 +231,9 @@ fsp_err_t R_RSIP_ECDSA_Verify (rsip_ctrl_t * const p_ctrl, /* Call primitive (cast to match the argument type with the primitive function) */ rsip_ret_t rsip_ret = - g_func.p_ecdsa_verify[p_wrapped_public_key->subtype]((const uint32_t *) p_wrapped_public_key->value, - (const uint32_t *) p_hash, - (const uint32_t *) p_signature); + gp_func_ecdsa_verify[p_wrapped_public_key->subtype]((const uint32_t *) p_wrapped_public_key->value, + (const uint32_t *) p_hash, + (const uint32_t *) p_signature); /* Check error */ fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_otf.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_otf.c similarity index 95% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_otf.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_otf.c index 4a3d83f55..93f1b8d14 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_otf.c +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_otf.c @@ -51,7 +51,7 @@ * CH-0RSIP_OTF_CHANNEL_0 * CH-1 (*)RSIP_OTF_CHANNEL_1 * - * (*) These features are not supported in v5.3.0. + * (*) These features are not supported. * * \
* This API can only be executed in the STATE_MAIN, and there are no state transitions. @@ -73,8 +73,6 @@ * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. * - * @sa Section @ref r-rsip-key-management "Key Management" - * * @attention This function is only part of on-the-fly decryption activation process and intended to be called from * a higher level FSP module. Even if a user calls this function directly, the feature will not be enabled. * The number of channels for the channel parameter is dependent on the hardware. @@ -97,14 +95,14 @@ fsp_err_t R_RSIP_OTF_Init (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_ALG_AES == p_wrapped_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check if the key type is enabled on configuration and the channel is enabled */ - FSP_ERROR_RETURN(g_func.p_func_otf[channel][p_wrapped_key->subtype], FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_otf[channel][p_wrapped_key->subtype], FSP_ERR_NOT_ENABLED); #endif /* Check state */ FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); /* Call primitive (cast to match the argument type with the primitive function) */ - rsip_ret_t rsip_ret = g_func.p_func_otf[channel][p_wrapped_key->subtype] + rsip_ret_t rsip_ret = gp_func_otf[channel][p_wrapped_key->subtype] ((const uint32_t *) p_wrapped_key->value, (const uint32_t *) p_seed); /* Check error */ diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_public.h b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_public.h similarity index 62% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_public.h rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_public.h index 15fa4710f..bac592346 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_public.h +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_public.h @@ -72,33 +72,70 @@ fsp_err_t r_rsip_sha_update(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_ fsp_err_t r_rsip_sha_finish(rsip_ctrl_t * const p_ctrl, uint8_t * const p_digest); /*******************************************************************************************************************//** - * Clears handle. + * Resets handle. + * + * @param[in] handle Pointer to handle. ***********************************************************************************************************************/ RSIP_PRV_STATIC_INLINE void r_rsip_handle_reset (rsip_handle_t * handle) { memset(handle, 0, sizeof(rsip_handle_t)); } -RSIP_PRV_STATIC_INLINE rsip_alg_t r_rsip_key_type_to_alg (rsip_key_type_t key_type) +/*******************************************************************************************************************//** + * Convert to key type to internal algorithm ID. + * + * @param[in] key_type Key type. + * + * @return Internal algorithm ID. + ***********************************************************************************************************************/ +RSIP_PRV_STATIC_INLINE uint8_t r_rsip_key_type_to_alg (rsip_key_type_t key_type) { - return (rsip_alg_t) ((key_type >> 8) & 0xff); + return (uint8_t) ((key_type >> 8) & 0xff); } +/*******************************************************************************************************************//** + * Convert to key type to internal key type (subtype). + * + * @param[in] key_type Key type. + * + * @return Internal key type. + ***********************************************************************************************************************/ RSIP_PRV_STATIC_INLINE uint8_t r_rsip_key_type_to_subtype (rsip_key_type_t key_type) { return (uint8_t) (key_type & 0xff); } -RSIP_PRV_STATIC_INLINE rsip_alg_t r_rsip_key_pair_type_to_public_alg (rsip_key_pair_type_t key_pair_type) +/*******************************************************************************************************************//** + * Convert to key pair type to internal algorithm ID (public key). + * + * @param[in] key_pair_type Key pair type. + * + * @return Internal algorithm ID (public key). + ***********************************************************************************************************************/ +RSIP_PRV_STATIC_INLINE uint8_t r_rsip_key_pair_type_to_public_alg (rsip_key_pair_type_t key_pair_type) { - return (rsip_alg_t) ((key_pair_type >> 16) & 0xff); + return (uint8_t) ((key_pair_type >> 16) & 0xff); } -RSIP_PRV_STATIC_INLINE rsip_alg_t r_rsip_key_pair_type_to_private_alg (rsip_key_pair_type_t key_pair_type) +/*******************************************************************************************************************//** + * Convert to key pair type to internal algorithm ID (private key). + * + * @param[in] key_pair_type Key pair type. + * + * @return Internal algorithm ID (private key). + ***********************************************************************************************************************/ +RSIP_PRV_STATIC_INLINE uint8_t r_rsip_key_pair_type_to_private_alg (rsip_key_pair_type_t key_pair_type) { - return (rsip_alg_t) ((key_pair_type >> 8) & 0xff); + return (uint8_t) ((key_pair_type >> 8) & 0xff); } +/*******************************************************************************************************************//** + * Convert to key pair type to internal key type (subtype). + * + * @param[in] key_pair_type Key pair type. + * + * @return Internal key type. + ***********************************************************************************************************************/ RSIP_PRV_STATIC_INLINE uint8_t r_rsip_key_pair_type_to_subtype (rsip_key_pair_type_t key_pair_type) { return (uint8_t) (key_pair_type & 0xff); diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_rsa.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_rsa.c similarity index 81% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_rsa.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_rsa.c index a7fcb129b..0b4739f87 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_rsa.c +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_rsa.c @@ -25,7 +25,17 @@ #endif /* Buffer size of hash function */ -#define RSIP_PRV_BYTE_SIZE_HASH_BUFFER (RSIP_PRV_BYTE_SIZE_DIGEST_SHA512) +#if RSIP_CFG_SHA512_ENABLE + #define RSIP_PRV_BYTE_SIZE_HASH_BUFFER (RSIP_PRV_BYTE_SIZE_DIGEST_SHA512) +#elif RSIP_CFG_SHA384_ENABLE + #define RSIP_PRV_BYTE_SIZE_HASH_BUFFER (RSIP_PRV_BYTE_SIZE_DIGEST_SHA384) +#elif RSIP_CFG_SHA256_ENABLE || RSIP_CFG_SHA512_256_ENABLE + #define RSIP_PRV_BYTE_SIZE_HASH_BUFFER (RSIP_PRV_BYTE_SIZE_DIGEST_SHA256) +#elif RSIP_CFG_SHA224_ENABLE || RSIP_CFG_SHA512_224_ENABLE + #define RSIP_PRV_BYTE_SIZE_HASH_BUFFER (RSIP_PRV_BYTE_SIZE_DIGEST_SHA224) +#else + #define RSIP_PRV_BYTE_SIZE_HASH_BUFFER (RSIP_PRV_BYTE_SIZE_DIGEST_SHA1) +#endif /* PS (padding string) of EMSA-PKCS1-v1_5 */ #define RSIP_PRV_EMSA_PKCS1_V1_5_PS (0xFF) @@ -79,11 +89,11 @@ static fsp_err_t emsa_pss_h_generate(rsip_ctrl_t * const p_ctrl, static fsp_err_t emsa_pss_salt_generate(rsip_ctrl_t * const p_ctrl, uint8_t * const p_salt, uint32_t const salt_length); -fsp_err_t emsa_pss_ps_check(uint8_t const * const p_db, - uint32_t const dblen, - uint8_t const ** const pp_salt, - uint32_t * const p_slen, - bool const salt_auto_detection); +static fsp_err_t emsa_pss_ps_check(uint8_t const * const p_db, + uint32_t const dblen, + uint8_t const ** const pp_salt, + uint32_t * const p_slen, + bool const salt_auto_detection); static fsp_err_t mgf1_mask(rsip_ctrl_t * const p_ctrl, rsip_hash_type_t const hash_function, uint8_t const * const p_mgf_seed, @@ -92,13 +102,13 @@ static fsp_err_t mgf1_mask(rsip_ctrl_t * const p_ctrl, uint32_t const mask_len); static uint32_t secure_memcmp(const void * buf1, const void * buf2, uint32_t num); static void * memxor(void * buf1, void * buf2, uint32_t num); -RSIP_PRV_STATIC_INLINE void stack_clear(void * p_buf, const uint32_t num); +RSIP_PRV_STATIC_INLINE void buffer_clear(void * p_buf, const uint32_t num); /*********************************************************************************************************************** * Private global variables **********************************************************************************************************************/ -const uint32_t gs_hash_length[] = +static const uint32_t gs_hash_length[] = { [RSIP_HASH_TYPE_SHA1] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA1, [RSIP_HASH_TYPE_SHA224] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA224, @@ -117,6 +127,10 @@ static const uint32_t gs_key_length[RSIP_KEY_RSA_NUM] = [RSIP_KEY_RSA_4096] = RSIP_PRV_BYTE_SIZE_RSA_4096_N, }; +/* Because the buffer sizes are large, allocate memory in the static area instead of the stack area. */ +static uint8_t em_buffer[RSIP_PRV_BYTE_SIZE_RSA_EM_BUFFER]; +static uint8_t em_buffer2[RSIP_PRV_BYTE_SIZE_RSA_EM_BUFFER]; + /*********************************************************************************************************************** * Global variables **********************************************************************************************************************/ @@ -131,22 +145,20 @@ static const uint32_t gs_key_length[RSIP_KEY_RSA_NUM] = **********************************************************************************************************************/ /*******************************************************************************************************************//** - * Encrypts plaintext with raw RSA.
+ * Encrypts plaintext with raw RSA. + * * Implements @ref rsip_api_t::rsaEncrypt. * - * \ - * @arg The key type of p_wrapped_public_key must be RSIP_KEY_TYPE_RSA_xxx_PUBLIC. - * @arg This version supports the following key types: - * - * - * - * - * - * - *
Key LengthKey Type
2048 bitRSIP_KEY_TYPE_RSA_2048_PUBLIC
3072 bitRSIP_KEY_TYPE_RSA_3072_PUBLIC
4096 bitRSIP_KEY_TYPE_RSA_4096_PUBLIC
+ * @par Conditions + * @parblock + * Key type of p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_3072_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_4096_PUBLIC + * @endparblock * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -162,6 +174,8 @@ static const uint32_t gs_key_length[RSIP_KEY_RSA_NUM] = * * @note This API provides RSA low-level primitives (RSAEP/RSAVP1). * It should be used in conjunction with any padding scheme. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_RSA_Encrypt (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_public_key, @@ -181,7 +195,7 @@ fsp_err_t R_RSIP_RSA_Encrypt (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_ALG_RSA_PUBLIC == p_wrapped_public_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ - FSP_ERROR_RETURN(g_func.p_rsa_public[p_wrapped_public_key->subtype], FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_rsa_public[p_wrapped_public_key->subtype], FSP_ERR_NOT_ENABLED); #endif /* Check state */ @@ -191,22 +205,20 @@ fsp_err_t R_RSIP_RSA_Encrypt (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Decrypts ciphertext with raw RSA.
+ * Decrypts ciphertext with raw RSA. + * * Implements @ref rsip_api_t::rsaDecrypt. * - * \ - * @arg The key type of p_wrapped_private_key must be RSIP_KEY_TYPE_RSA_xxx_PRIVATE. - * @arg This version supports the following key types: - * - * - * - * - * - * - *
Key LengthKey Type
2048 bitRSIP_KEY_TYPE_RSA_2048_PRIVATE
3072 bitRSIP_KEY_TYPE_RSA_3072_PRIVATE
4096 bitRSIP_KEY_TYPE_RSA_4096_PRIVATE
+ * @par Conditions + * @parblock + * Key type of p_wrapped_private_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_3072_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_4096_PRIVATE + * @endparblock * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -222,6 +234,8 @@ fsp_err_t R_RSIP_RSA_Encrypt (rsip_ctrl_t * const p_ctrl, * * @note This API provides RSA low-level primitives (RSADP/RSASP1). * It should be used in conjunction with any padding scheme. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_RSA_Decrypt (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_private_key, @@ -241,7 +255,7 @@ fsp_err_t R_RSIP_RSA_Decrypt (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_ALG_RSA_PRIVATE == p_wrapped_private_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ - FSP_ERROR_RETURN(g_func.p_rsa_private[p_wrapped_private_key->subtype], FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_rsa_private[p_wrapped_private_key->subtype], FSP_ERR_NOT_ENABLED); #endif /* Check state */ @@ -251,26 +265,23 @@ fsp_err_t R_RSIP_RSA_Decrypt (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Encrypts plaintext with RSAES-PKCS1-v1_5.
- * Implements @ref rsip_api_t::rsaesPkcs1V15Encrypt. + * Encrypts plaintext with RSAES-PKCS1-v1_5. * - * \ - * @arg The key type of p_wrapped_public_key must be RSIP_KEY_TYPE_RSA_xxx_PUBLIC. - * @arg This version supports the following key types: - * - * - * - * - * - * - *
Key LengthKey Type
2048 bitRSIP_KEY_TYPE_RSA_2048_PUBLIC
3072 bitRSIP_KEY_TYPE_RSA_3072_PUBLIC
4096 bitRSIP_KEY_TYPE_RSA_4096_PUBLIC
+ * Implements @ref rsip_api_t::rsaesPkcs1V15Encrypt. * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par Conditions + * @parblock + * Key type of p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_3072_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_4096_PUBLIC * - * `mLen` (plain_length) and `k` (RSA key length) must meet the following condition. + * mLen (plain_length) and k (modulus length) must meet the following condition. + * - mLen <= k - 11 + * @endparblock * - * `mlen <= k - 11` + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -285,6 +296,8 @@ fsp_err_t R_RSIP_RSA_Decrypt (rsip_ctrl_t * const p_ctrl, * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_RSAES_PKCS1_V1_5_Encrypt (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_public_key, @@ -305,7 +318,7 @@ fsp_err_t R_RSIP_RSAES_PKCS1_V1_5_Encrypt (rsip_ctrl_t * const p_ct FSP_ERROR_RETURN(RSIP_ALG_RSA_PUBLIC == p_wrapped_public_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ - FSP_ERROR_RETURN(g_func.p_rsa_public[p_wrapped_public_key->subtype], FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_rsa_public[p_wrapped_public_key->subtype], FSP_ERR_NOT_ENABLED); #endif /* Check state */ @@ -351,22 +364,22 @@ fsp_err_t R_RSIP_RSAES_PKCS1_V1_5_Encrypt (rsip_ctrl_t * const p_ct } /*******************************************************************************************************************//** - * Decrypts with RSAES-PKCS1-v1_5.
+ * Decrypts with RSAES-PKCS1-v1_5. + * * Implements @ref rsip_api_t::rsaesPkcs1V15Decrypt. * - * \ - * @arg The key type of p_wrapped_private_key must be RSIP_KEY_TYPE_RSA_xxx_PRIVATE. - * @arg This version supports the following key types: - * - * - * - * - * - * - *
Key LengthKey Type
2048 bitRSIP_KEY_TYPE_RSA_2048_PRIVATE
3072 bitRSIP_KEY_TYPE_RSA_3072_PRIVATE
4096 bitRSIP_KEY_TYPE_RSA_4096_PRIVATE
+ * @par Conditions + * @parblock + * Key type of p_wrapped_private_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_3072_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_4096_PRIVATE + * + * plain_buffer_length must be greater than or equal to mLen(plaintext length). + * @endparblock * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -382,10 +395,9 @@ fsp_err_t R_RSIP_RSAES_PKCS1_V1_5_Encrypt (rsip_ctrl_t * const p_ct * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. * - * @note The stack usage of this function depends on the maximum key length for RSA decryption enabled in configuration. - * For example, if RSA-2048 is enabled, this function uses at least 256 bytes (2048 bits) of stack. - * To shrink the stack size, please disable unused key length in configuration. * @note This API skips the ciphertext length checking at RFC8017 (PKCS#1 v2.2) Section 7.2.2 Step 1. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_RSAES_PKCS1_V1_5_Decrypt (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_private_key, @@ -408,7 +420,7 @@ fsp_err_t R_RSIP_RSAES_PKCS1_V1_5_Decrypt (rsip_ctrl_t * const p_ct FSP_ERROR_RETURN(RSIP_ALG_RSA_PRIVATE == p_wrapped_private_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ - FSP_ERROR_RETURN(g_func.p_rsa_private[p_wrapped_private_key->subtype], FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_rsa_private[p_wrapped_private_key->subtype], FSP_ERR_NOT_ENABLED); #endif /* Check state */ @@ -423,10 +435,6 @@ fsp_err_t R_RSIP_RSAES_PKCS1_V1_5_Decrypt (rsip_ctrl_t * const p_ct * * buffer = EM */ - uint8_t em_buffer[RSIP_PRV_BYTE_SIZE_RSA_EM_BUFFER] = - { - 0 - }; uint8_t * p_em = &em_buffer[0]; /* m = RSADP (K, c) */ @@ -493,50 +501,32 @@ fsp_err_t R_RSIP_RSAES_PKCS1_V1_5_Decrypt (rsip_ctrl_t * const p_ct } } - /* Clear plaintext in stack */ - stack_clear(p_em, klen); + /* Clear plaintext in buffer */ + buffer_clear(p_em, klen); return err; } /*******************************************************************************************************************//** - * Encrypts plaintext with RSAES-OAEP.
+ * Encrypts plaintext with RSAES-OAEP. + * * Implements @ref rsip_api_t::rsaesOaepEncrypt. * - * \ - * @arg The key type of p_wrapped_public_key must be RSIP_KEY_TYPE_RSA_xxx_PUBLIC. - * @arg This version supports the following key types: - * - * - * - * - * - * - *
Key LengthKey Type
2048 bitRSIP_KEY_TYPE_RSA_2048_PUBLIC
3072 bitRSIP_KEY_TYPE_RSA_3072_PUBLIC
4096 bitRSIP_KEY_TYPE_RSA_4096_PUBLIC
- * @arg Argument hash_function only supports the features listed below. - * - * - * - * - * - * - *
Hash FunctionCorresponding Parameter
SHA256RSIP_HASH_TYPE_SHA256
SHA384RSIP_HASH_TYPE_SHA384
SHA512RSIP_HASH_TYPE_SHA512
- * @arg Argument mask_generation_function only supports the features listed below. - * - * - * - * - * - * - *
Mask Generation FunctionCorresponding Parameter
SHA256RSIP_MGF_TYPE_MGF1_SHA256
SHA384RSIP_MGF_TYPE_MGF1_SHA384
SHA512RSIP_MGF_TYPE_MGF1_SHA512
- * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. - * - * `mLen` (plain_length), `hLen` (output length of hash_function), and `k` (RSA key length) + * @par Conditions + * @parblock + * Key type of p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_3072_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_4096_PUBLIC + * + * mLen (plain_length), hLen (hash length of hash_function), and k (modulus length) * must meet the following condition. + * - mLen <= k - 2 hLen - 2 + * + * Argument hash_function accepts any member of enumeration @ref rsip_hash_type_t. * - * `mLen <= k - 2 hLen - 2` + * Argument mask_generation_function accepts any member of enumeration @ref rsip_mgf_type_t. + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -551,6 +541,8 @@ fsp_err_t R_RSIP_RSAES_PKCS1_V1_5_Decrypt (rsip_ctrl_t * const p_ct * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_RSAES_OAEP_Encrypt (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_public_key, @@ -576,7 +568,7 @@ fsp_err_t R_RSIP_RSAES_OAEP_Encrypt (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_ALG_RSA_PUBLIC == p_wrapped_public_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ - FSP_ERROR_RETURN(g_func.p_rsa_public[p_wrapped_public_key->subtype], FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_rsa_public[p_wrapped_public_key->subtype], FSP_ERR_NOT_ENABLED); FSP_ERROR_RETURN(g_sha_enabled[hash_function], FSP_ERR_NOT_ENABLED); FSP_ERROR_RETURN(g_sha_enabled[mask_generation_function], FSP_ERR_NOT_ENABLED); #endif @@ -590,7 +582,7 @@ fsp_err_t R_RSIP_RSAES_OAEP_Encrypt (rsip_ctrl_t * const p_ctrl, uint32_t dblen = klen - hlen - 1; /* Check length */ - FSP_ERROR_RETURN(mlen <= (klen - 2 * hlen - 2), FSP_ERR_INVALID_SIZE); + FSP_ERROR_RETURN((mlen + 2 * hlen + 2) <= klen, FSP_ERR_INVALID_SIZE); /* * Prepare EME-OAEP encoding input @@ -693,42 +685,29 @@ fsp_err_t R_RSIP_RSAES_OAEP_Encrypt (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Decrypts ciphertext with RSAES-OAEP.
+ * Decrypts ciphertext with RSAES-OAEP. + * * Implements @ref rsip_api_t::rsaesOaepDecrypt. * - * \ - * @arg The key type of p_wrapped_private_key must be RSIP_KEY_TYPE_RSA_xxx_PRIVATE. - * @arg This version supports the following key types: - * - * - * - * - * - * - *
Key LengthKey Type
2048 bitRSIP_KEY_TYPE_RSA_2048_PRIVATE
3072 bitRSIP_KEY_TYPE_RSA_3072_PRIVATE
4096 bitRSIP_KEY_TYPE_RSA_4096_PRIVATE
- * @arg Argument hash_function only supports the features listed below. - * - * - * - * - * - * - *
Hash FunctionCorresponding Parameter
SHA256RSIP_HASH_TYPE_SHA256
SHA384RSIP_HASH_TYPE_SHA384
SHA512RSIP_HASH_TYPE_SHA512
- * @arg Argument mask_generation_function only supports the features listed below. - * - * - * - * - * - * - *
Mask Generation FunctionCorresponding Parameter
SHA256RSIP_MGF_TYPE_MGF1_SHA256
SHA384RSIP_MGF_TYPE_MGF1_SHA384
SHA512RSIP_MGF_TYPE_MGF1_SHA512
- * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. - * - * `hLen` (output length of hash_function) and `k` (RSA key length) must meet the following condition. - * - * `k >= 2 hLen + 2` + * @par Conditions + * @parblock + * Key type of p_wrapped_private_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_3072_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_4096_PRIVATE + * + * hLen (hash length of hash_function) and k (modulus length) must meet the following condition. + * - k >= 2 hLen + 2 + * + * plain_buffer_length must be greater than or equal to mLen(plaintext length). + * + * Argument hash_function accepts any member of enumeration @ref rsip_hash_type_t. + * + * Argument mask_generation_function accepts any member of enumeration @ref rsip_mgf_type_t. + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -744,10 +723,9 @@ fsp_err_t R_RSIP_RSAES_OAEP_Encrypt (rsip_ctrl_t * const p_ctrl, * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. * - * @note The stack usage of this function depends on the maximum key length for RSA decryption enabled in configuration. - * For example, if RSA-2048 is enabled, this function uses at least 256 bytes (2048 bits) of stack. - * To shrink the stack size, please disable unused key length in configuration. * @note This API skips the ciphertext length checking at RFC8017 (PKCS#1 v2.2) Section 7.1.2 Step 1. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_RSAES_OAEP_Decrypt (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_private_key, @@ -775,7 +753,7 @@ fsp_err_t R_RSIP_RSAES_OAEP_Decrypt (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_ALG_RSA_PRIVATE == p_wrapped_private_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ - FSP_ERROR_RETURN(g_func.p_rsa_private[p_wrapped_private_key->subtype], FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_rsa_private[p_wrapped_private_key->subtype], FSP_ERR_NOT_ENABLED); FSP_ERROR_RETURN(g_sha_enabled[hash_function], FSP_ERR_NOT_ENABLED); FSP_ERROR_RETURN(g_sha_enabled[mask_generation_function], FSP_ERR_NOT_ENABLED); #endif @@ -797,7 +775,6 @@ fsp_err_t R_RSIP_RSAES_OAEP_Decrypt (rsip_ctrl_t * const p_ctrl, * * buffer = EM */ - uint8_t em_buffer[RSIP_PRV_BYTE_SIZE_RSA_EM_BUFFER]; uint8_t hash_buffer[RSIP_PRV_BYTE_SIZE_HASH_BUFFER]; uint8_t * p_em = &em_buffer[0]; uint8_t * p_seed = &p_em[1]; @@ -904,37 +881,32 @@ fsp_err_t R_RSIP_RSAES_OAEP_Decrypt (rsip_ctrl_t * const p_ctrl, } } - /* Clear stack data */ - stack_clear(p_em, klen); - stack_clear(hash_buffer, hlen); + /* Clear buffer data */ + buffer_clear(p_em, klen); + buffer_clear(hash_buffer, hlen); return err; } /*******************************************************************************************************************//** - * Signs message with RSASSA-PKCS1-v1_5.
+ * Signs message with RSASSA-PKCS1-v1_5. + * * Implements @ref rsip_api_t::rsassaPkcs1V15Sign. * - * \ - * @arg The key type of p_wrapped_private_key must be RSIP_KEY_TYPE_RSA_xxx_PRIVATE. - * @arg This version supports the following key types: - * - * - * - * - * - * - *
Key LengthKey Type
2048 bitRSIP_KEY_TYPE_RSA_2048_PRIVATE
3072 bitRSIP_KEY_TYPE_RSA_3072_PRIVATE
4096 bitRSIP_KEY_TYPE_RSA_4096_PRIVATE
- * @arg Argument hash_function only supports the features listed below. - * - * - * - * - * - * - *
Hash FunctionCorresponding Parameter
SHA256RSIP_HASH_TYPE_SHA256
SHA384RSIP_HASH_TYPE_SHA384
SHA512RSIP_HASH_TYPE_SHA512
- * @arg The hash value must be computed and passed to the argument p_hash before executing this API.
- * Also, the argument hash_function must specify the one used when computing the hash value above. + * @par Conditions + * @parblock + * Key type of p_wrapped_private_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_3072_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_4096_PRIVATE + * + * Argument hash_function accepts any member of enumeration @ref rsip_hash_type_t. + * + * Message hash p_hash should be computed in advance with hash_function. + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -949,6 +921,8 @@ fsp_err_t R_RSIP_RSAES_OAEP_Decrypt (rsip_ctrl_t * const p_ctrl, * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_RSASSA_PKCS1_V1_5_Sign (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_private_key, @@ -969,7 +943,7 @@ fsp_err_t R_RSIP_RSASSA_PKCS1_V1_5_Sign (rsip_ctrl_t * const p_ctrl FSP_ERROR_RETURN(RSIP_ALG_RSA_PRIVATE == p_wrapped_private_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ - FSP_ERROR_RETURN(g_func.p_rsa_private[p_wrapped_private_key->subtype], FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_rsa_private[p_wrapped_private_key->subtype], FSP_ERR_NOT_ENABLED); FSP_ERROR_RETURN(g_sha_enabled[hash_function], FSP_ERR_NOT_ENABLED); #endif @@ -1000,32 +974,24 @@ fsp_err_t R_RSIP_RSASSA_PKCS1_V1_5_Sign (rsip_ctrl_t * const p_ctrl } /*******************************************************************************************************************//** - * Verifies signature with RSASSA-PKCS1-v1_5.
+ * Verifies signature with RSASSA-PKCS1-v1_5. + * * Implements @ref rsip_api_t::rsassaPkcs1V15Verify. * - * \ - * @arg The key type of p_wrapped_public_key must be RSIP_KEY_TYPE_RSA_xxx_PUBLIC. - * @arg This version supports the following key types: - * - * - * - * - * - * - *
Key LengthKey Type
2048 bitRSIP_KEY_TYPE_RSA_2048_PUBLIC
3072 bitRSIP_KEY_TYPE_RSA_3072_PUBLIC
4096 bitRSIP_KEY_TYPE_RSA_4096_PUBLIC
- * @arg Argument hash_function only supports the features listed below. - * - * - * - * - * - * - *
Hash FunctionCorresponding Parameter
SHA256RSIP_HASH_TYPE_SHA256
SHA384RSIP_HASH_TYPE_SHA384
SHA512RSIP_HASH_TYPE_SHA512
- * @arg The hash value must be computed and passed to the argument p_hash before executing this API.
- * Also, the argument hash_function must specify the one used when computing the hash value above. - * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par Conditions + * @parblock + * Key type of p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_3072_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_4096_PUBLIC + * + * Argument hash_function accepts any member of enumeration @ref rsip_hash_type_t. + * + * Message hash p_hash should be computed in advance with hash_function. + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -1041,9 +1007,7 @@ fsp_err_t R_RSIP_RSASSA_PKCS1_V1_5_Sign (rsip_ctrl_t * const p_ctrl * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. * - * @note The stack usage of this function depends on the maximum key length for RSA decryption enabled in configuration. - * For example, if RSA-2048 is enabled, this function uses at least 512 bytes (2048 bits * 2) of stack. - * To shrink the stack size, please disable unused key length in configuration. + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_RSASSA_PKCS1_V1_5_Verify (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_public_key, @@ -1064,7 +1028,7 @@ fsp_err_t R_RSIP_RSASSA_PKCS1_V1_5_Verify (rsip_ctrl_t * const p_ct FSP_ERROR_RETURN(RSIP_ALG_RSA_PUBLIC == p_wrapped_public_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ - FSP_ERROR_RETURN(g_func.p_rsa_public[p_wrapped_public_key->subtype], FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_rsa_public[p_wrapped_public_key->subtype], FSP_ERR_NOT_ENABLED); FSP_ERROR_RETURN(g_sha_enabled[hash_function], FSP_ERR_NOT_ENABLED); #endif @@ -1073,17 +1037,14 @@ fsp_err_t R_RSIP_RSASSA_PKCS1_V1_5_Verify (rsip_ctrl_t * const p_ct uint32_t klen = gs_key_length[p_wrapped_public_key->subtype]; // Actual name in RFC 8107 is "k" - uint8_t em1_buffer[RSIP_PRV_BYTE_SIZE_RSA_EM_BUFFER]; - uint8_t em2_buffer[RSIP_PRV_BYTE_SIZE_RSA_EM_BUFFER]; - /* * s = OS2IP (S) * m = RSAVP1 ((n, e), s) * EM = I2OSP (m, k) * - * em1_buffer = EM + * em_buffer = EM */ - fsp_err_t err = r_rsip_rsa_encrypt(p_wrapped_public_key, p_signature, em1_buffer); + fsp_err_t err = r_rsip_rsa_encrypt(p_wrapped_public_key, p_signature, em_buffer); if (FSP_SUCCESS == err) { @@ -1091,15 +1052,15 @@ fsp_err_t R_RSIP_RSASSA_PKCS1_V1_5_Verify (rsip_ctrl_t * const p_ct * EMSA-PKCS1-v1_5 encoding * EM' = EMSA-PKCS1-V1_5-ENCODE (M, k) * - * em2_buffer = EM' + * em_buffer2 = EM' */ - err = emsa_pkcs1_v1_5_encode(hash_function, p_hash, em2_buffer, klen); + err = emsa_pkcs1_v1_5_encode(hash_function, p_hash, em_buffer2, klen); } if (FSP_SUCCESS == err) { /* Compare the encoded message EM and the second encoded message EM' */ - if (0 != memcmp(em1_buffer, em2_buffer, klen)) + if (0 != memcmp(em_buffer, em_buffer2, klen)) { err = FSP_ERR_CRYPTO_RSIP_FAIL; } @@ -1109,53 +1070,36 @@ fsp_err_t R_RSIP_RSASSA_PKCS1_V1_5_Verify (rsip_ctrl_t * const p_ct } /*******************************************************************************************************************//** - * Signs message with RSASSA-PSS.
+ * Signs message with RSASSA-PSS. + * * Implements @ref rsip_api_t::rsassaPssSign. * - * \ - * @arg The key type of p_wrapped_private_key must be RSIP_KEY_TYPE_RSA_xxx_PRIVATE. - * @arg This version supports the following key types: - * - * - * - * - * - * - *
Key LengthKey Type
2048 bitRSIP_KEY_TYPE_RSA_2048_PRIVATE
3072 bitRSIP_KEY_TYPE_RSA_3072_PRIVATE
4096 bitRSIP_KEY_TYPE_RSA_4096_PRIVATE
- * @arg Argument hash_function only supports the features listed below. - * - * - * - * - * - * - *
Hash FunctionCorresponding Parameter
SHA256RSIP_HASH_TYPE_SHA256
SHA384RSIP_HASH_TYPE_SHA384
SHA512RSIP_HASH_TYPE_SHA512
- * @arg Argument mask_generation_function only supports the features listed below. - * - * - * - * - * - * - *
Mask Generation FunctionCorresponding Parameter
SHA256RSIP_MGF_TYPE_MGF1_SHA256
SHA384RSIP_MGF_TYPE_MGF1_SHA384
SHA512RSIP_MGF_TYPE_MGF1_SHA512
- * @arg Argument salt_length must follow the list below. - * - * - * - * - * - * - * - *
ParameterDescription
RSIP_RSA_SALT_LENGTH_AUTOThe salt length is set to - * RSIP_RSA_SALT_LENGTH_MAX or　RSIP_RSA_SALT_LENGTH_HASH, - * whichever is shorter. When verifying, the salt length is detected automatically.
RSIP_RSA_SALT_LENGTH_HASHThe salt length is set to the hash length.
RSIP_RSA_SALT_LENGTH_MAXThe salt length is set to emLen - hLen - 2, - * where emLen is the same as the key length and hLen is the hash length.
zero or positive integersThe following conditions must be satisfied.
- * salt_length <= emLen - hLen - 2 where emLen is the same as the key length and hLen is the hash length.
- * @arg The hash value must be computed and passed to the argument p_hash before executing this API.
- * Also, the argument hash_function must specify the one used when computing the hash value above. - * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par Conditions + * @parblock + * Key type of p_wrapped_private_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_3072_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_4096_PRIVATE + * + * Argument hash_function accepts any member of enumeration @ref rsip_hash_type_t. + * + * Argument mask_generation_function accepts any member of enumeration @ref rsip_mgf_type_t. + * + * Message hash p_hash should be computed in advance with hash_function. + * + * Salt length salt_length must be one of the following: + * - Any member of enumeration @ref rsip_rsa_salt_length_t + * - @ref RSIP_RSA_SALT_LENGTH_AUTO + * - @ref RSIP_RSA_SALT_LENGTH_HASH + * - @ref RSIP_RSA_SALT_LENGTH_MAX + * - Integers that satisfies the formula: sLen <= emLen - hLen - 2 + * - sLen is salt_length + * - emLen is the same as modulus length + * - hLen is the hash length + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -1170,6 +1114,8 @@ fsp_err_t R_RSIP_RSASSA_PKCS1_V1_5_Verify (rsip_ctrl_t * const p_ct * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_RSASSA_PSS_Sign (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_private_key, @@ -1192,7 +1138,7 @@ fsp_err_t R_RSIP_RSASSA_PSS_Sign (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_ALG_RSA_PRIVATE == p_wrapped_private_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ - FSP_ERROR_RETURN(g_func.p_rsa_private[p_wrapped_private_key->subtype], FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_rsa_private[p_wrapped_private_key->subtype], FSP_ERR_NOT_ENABLED); FSP_ERROR_RETURN(g_sha_enabled[hash_function], FSP_ERR_NOT_ENABLED); FSP_ERROR_RETURN(g_sha_enabled[mask_generation_function], FSP_ERR_NOT_ENABLED); #endif @@ -1230,53 +1176,35 @@ fsp_err_t R_RSIP_RSASSA_PSS_Sign (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Verifies signature with RSASSA-PSS.
+ * Verifies signature with RSASSA-PSS. * Implements @ref rsip_api_t::rsassaPssVerify. * - * \ - * @arg The key type of p_wrapped_public_key must be RSIP_KEY_TYPE_RSA_xxx_PUBLIC. - * @arg This version supports the following key types: - * - * - * - * - * - * - *
Key LengthKey Type
2048 bitRSIP_KEY_TYPE_RSA_2048_PUBLIC
3072 bitRSIP_KEY_TYPE_RSA_3072_PUBLIC
4096 bitRSIP_KEY_TYPE_RSA_4096_PUBLIC
- * @arg Argument hash_function only supports the features listed below. - * - * - * - * - * - * - *
Hash FunctionCorresponding Parameter
SHA256RSIP_HASH_TYPE_SHA256
SHA384RSIP_HASH_TYPE_SHA384
SHA512RSIP_HASH_TYPE_SHA512
- * @arg Argument mask_generation_function only supports the features listed below. - * - * - * - * - * - * - *
Mask Generation FunctionCorresponding Parameter
SHA256RSIP_MGF_TYPE_MGF1_SHA256
SHA384RSIP_MGF_TYPE_MGF1_SHA384
SHA512RSIP_MGF_TYPE_MGF1_SHA512
- * @arg Argument salt_length must follow the list below. - * - * - * - * - * - * - * - *
ParameterDescription
RSIP_RSA_SALT_LENGTH_AUTOThe salt length is set to - * RSIP_RSA_SALT_LENGTH_MAX or　RSIP_RSA_SALT_LENGTH_HASH, - * whichever is shorter. When verifying, the salt length is detected automatically.
RSIP_RSA_SALT_LENGTH_HASHThe salt length is set to the hash length.
RSIP_RSA_SALT_LENGTH_MAXThe salt length is set to emLen - hLen - 2, - * where emLen is the same as the key length and hLen is the hash length.
zero or positive integersThe following conditions must be satisfied.
- * salt_length <= emLen - hLen - 2 where emLen is the same as the key length and hLen is the hash length.
- * @arg The hash value must be computed and passed to the argument p_hash before executing this API.
- * Also, the argument hash_function must specify the one used when computing the hash value above. - * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par Conditions + * @parblock + * Key type of p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_3072_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_4096_PUBLIC + * + * Argument hash_function accepts any member of enumeration @ref rsip_hash_type_t. + * + * Argument mask_generation_function accepts any member of enumeration @ref rsip_mgf_type_t. + * + * Message hash p_hash should be computed in advance with hash_function. + * + * Salt length salt_length must be one of the following: + * - Any member of enumeration @ref rsip_rsa_salt_length_t + * - @ref RSIP_RSA_SALT_LENGTH_AUTO + * - @ref RSIP_RSA_SALT_LENGTH_HASH + * - @ref RSIP_RSA_SALT_LENGTH_MAX + * - Integers that satisfies the formula: sLen <= emLen - hLen - 2 + * - sLen is salt_length + * - emLen is the same as modulus length + * - hLen is the hash length + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -1292,9 +1220,7 @@ fsp_err_t R_RSIP_RSASSA_PSS_Sign (rsip_ctrl_t * const p_ctrl, * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. * - * @note The stack usage of this function depends on the maximum key length for RSA decryption enabled in configuration. - * For example, if RSA-2048 is enabled, this function uses at least 512 bytes (2048 bits * 2) of stack. - * To shrink the stack size, please disable unused key length in configuration. + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_RSASSA_PSS_Verify (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_public_key, @@ -1317,7 +1243,7 @@ fsp_err_t R_RSIP_RSASSA_PSS_Verify (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_ALG_RSA_PUBLIC == p_wrapped_public_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ - FSP_ERROR_RETURN(g_func.p_rsa_public[p_wrapped_public_key->subtype], FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(gp_func_rsa_public[p_wrapped_public_key->subtype], FSP_ERR_NOT_ENABLED); FSP_ERROR_RETURN(g_sha_enabled[hash_function], FSP_ERR_NOT_ENABLED); FSP_ERROR_RETURN(g_sha_enabled[mask_generation_function], FSP_ERR_NOT_ENABLED); #endif @@ -1327,8 +1253,6 @@ fsp_err_t R_RSIP_RSASSA_PSS_Verify (rsip_ctrl_t * const p_ctrl, uint32_t klen = gs_key_length[p_wrapped_public_key->subtype]; // Actual name in RFC 8107 is "k" - uint8_t em_buffer[RSIP_PRV_BYTE_SIZE_RSA_EM_BUFFER]; - /* * s = OS2IP (S) * m = RSAVP1 ((n, e), s) @@ -1385,9 +1309,9 @@ static fsp_err_t r_rsip_rsa_encrypt (rsip_wrapped_key_t const * const p_wrapped_ { /* Call primitive (cast to match the argument type with the primitive function) */ rsip_ret_t rsip_ret = - g_func.p_rsa_public[p_wrapped_public_key->subtype]((const uint32_t *) p_wrapped_public_key-> - value, (const uint32_t *) p_plain, - (uint32_t *) p_cipher); + gp_func_rsa_public[p_wrapped_public_key->subtype]((const uint32_t *) p_wrapped_public_key-> + value, (const uint32_t *) p_plain, + (uint32_t *) p_cipher); /* Check error */ fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; @@ -1447,9 +1371,9 @@ static fsp_err_t r_rsip_rsa_decrypt (rsip_wrapped_key_t const * const p_wrapped_ { /* Call primitive (cast to match the argument type with the primitive function) */ rsip_ret_t rsip_ret = - g_func.p_rsa_private[p_wrapped_private_key->subtype]((const uint32_t *) p_wrapped_private_key-> - value, (const uint32_t *) p_cipher, - (uint32_t *) p_plain); + gp_func_rsa_private[p_wrapped_private_key->subtype]((const uint32_t *) p_wrapped_private_key-> + value, (const uint32_t *) p_cipher, + (uint32_t *) p_plain); /* Check error */ fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; @@ -1978,11 +1902,11 @@ static fsp_err_t emsa_pss_salt_generate (rsip_ctrl_t * const p_ctrl, uint8_t * c * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_CRYPTO_RSIP_FAIL PS is invalid. **********************************************************************************************************************/ -fsp_err_t emsa_pss_ps_check (uint8_t const * const p_db, - uint32_t const dblen, - uint8_t const ** const pp_salt, - uint32_t * const p_slen, - bool const salt_auto_detection) +static fsp_err_t emsa_pss_ps_check (uint8_t const * const p_db, + uint32_t const dblen, + uint8_t const ** const pp_salt, + uint32_t * const p_slen, + bool const salt_auto_detection) { fsp_err_t err = FSP_SUCCESS; uint32_t ps_ptr = 0; @@ -2128,14 +2052,14 @@ static void * memxor (void * buf1, void * buf2, uint32_t num) } /*******************************************************************************************************************//** - * Clears stack data. + * Clears buffer. * * If memset_s is supported, it is guaranteed that this function will not be optimized. * - * @param[in,out] p_buf Stack data to be cleared. - * @param[in] num Stack data size. + * @param[in,out] p_buf Buffer data to be cleared. + * @param[in] num Buffer data size. ***********************************************************************************************************************/ -RSIP_PRV_STATIC_INLINE void stack_clear (void * p_buf, const uint32_t num) +RSIP_PRV_STATIC_INLINE void buffer_clear (void * p_buf, const uint32_t num) { #if __STDC_WANT_LIB_EXT1__ memset_s(p_buf, num, 0, num); diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_sha.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_sha.c similarity index 79% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_sha.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_sha.c index 56a6b48d0..2a062cf9c 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/public/common/r_rsip_sha.c +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_sha.c @@ -36,6 +36,8 @@ static const uint32_t gs_hmac_length[] = [RSIP_KEY_HMAC_SHA1] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA1, [RSIP_KEY_HMAC_SHA224] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA224, [RSIP_KEY_HMAC_SHA256] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA256, + [RSIP_KEY_HMAC_SHA384] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA384, + [RSIP_KEY_HMAC_SHA512] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA512, }; /*********************************************************************************************************************** @@ -52,39 +54,29 @@ static const uint32_t gs_hmac_length[] = **********************************************************************************************************************/ /*******************************************************************************************************************//** - * Generates SHA message digest.
+ * Generates SHA message digest. + * * Implements @ref rsip_api_t::shaCompute. * - * \ - * @arg Hash type must follow the list below. - * - * - * - * - * - * - *
Hash TypeCorresponding Parameter
SHA256RSIP_HASH_TYPE_SHA256
SHA384RSIP_HASH_TYPE_SHA384
SHA512RSIP_HASH_TYPE_SHA512
- * @arg The length of message digest is the list below. - * - * - * - * - * - * - *
Hash Typedigest length
SHA25632
SHA38448
SHA51264
- * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par Conditions + * See R_RSIP_SHA_Init(). + * + * @par Output length + * See R_RSIP_SHA_Finish(). + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. - * @retval FSP_ERR_INVALID_ARGUMENT Input key type or mode is illegal. * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_SHA_Compute (rsip_ctrl_t * const p_ctrl, rsip_hash_type_t const hash_type, @@ -136,35 +128,31 @@ fsp_err_t R_RSIP_SHA_Compute (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Prepares a SHA generation.
+ * Starts SHA operation. + * * Implements @ref rsip_api_t::shaInit. * - * \ - * @arg Hash type must follow the list below. - * - * - * - * - * - * - *
Hash TypeCorresponding Parameter
SHA256RSIP_HASH_TYPE_SHA256
SHA384RSIP_HASH_TYPE_SHA384
SHA512RSIP_HASH_TYPE_SHA512
- * - * \
- * This API can only be executed in the STATE_MAIN, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_SUCCESSSTATE_SHA
OthersNo change
+ * @par Conditions + * Argument hash_function accepts any member of enumeration @ref rsip_hash_type_t. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_SHA | + * |Others |No change | + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. - * @retval FSP_ERR_INVALID_ARGUMENT Input key type or mode is illegal. * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. -**********************************************************************************************************************/ + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ fsp_err_t R_RSIP_SHA_Init (rsip_ctrl_t * const p_ctrl, rsip_hash_type_t const hash_type) { #if RSIP_CFG_PARAM_CHECKING_ENABLE @@ -181,19 +169,12 @@ fsp_err_t R_RSIP_SHA_Init (rsip_ctrl_t * const p_ctrl, rsip_hash_type_t const ha } /*******************************************************************************************************************//** - * Inputs message.
- * Implements @ref rsip_api_t::shaUpdate. + * Inputs SHA message. * - * \ - * @arg Requires prerequisite that R_RSIP_SHA_Init, R_RSIP_SHA_Update, or R_RSIP_SHA_Resume results in FSP_SUCCESS. + * Implements @ref rsip_api_t::shaUpdate. * - * \
- * This API can only be executed in the STATE_SHA, and the state after execution changes as follows depending on the return value. - * - * - * - * - *
Return ValueState after execution
AnyNo change
+ * @par State transition + * This API can only be executed in **STATE_SHA**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -218,28 +199,28 @@ fsp_err_t R_RSIP_SHA_Update (rsip_ctrl_t * const p_ctrl, uint8_t const * const p } /*******************************************************************************************************************//** - * Finalizes a SHA generation.
+ * Outputs SHA message digest. + * * Implements @ref rsip_api_t::shaFinish. * - * \ - * @arg Requires prerequisite that R_RSIP_SHA_Init, R_RSIP_SHA_Update, or R_RSIP_SHA_Resume results in FSP_SUCCESS. - * @arg The length of message digest is the list below. - * - * - * - * - * - * - *
Hash Typedigest length
SHA25632
SHA38448
SHA51264
- * - * \
- * This API can only be executed in the STATE_SHA, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_ERR_ASSERTION
FSP_ERR_NOT_OPEN		No change
OthersSTATE_MAIN
+ * @par Output length + * Output length to p_digest depends on hash_function. + * - 32 ( @ref RSIP_HASH_TYPE_SHA256) + * - 48 ( @ref RSIP_HASH_TYPE_SHA384) + * - 64 ( @ref RSIP_HASH_TYPE_SHA512) + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_SHA**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -264,28 +245,30 @@ fsp_err_t R_RSIP_SHA_Finish (rsip_ctrl_t * const p_ctrl, uint8_t * const p_diges } /*******************************************************************************************************************//** - * Suspend SHA generation. - * This API allows you to suspend processing, for example, if you are in the middle of computing digest value for successive chunks of the message and need to perform another process.
+ * Suspends SHA operation. + * + * This API releases RSIP resource and outputs intermediate results. Therefore, it can be used in the following cases: + * - Execute another cryptographic operations during inputting successive chunks of the message. + * - Reuse intermediate results. + * * Implements @ref rsip_api_t::shaSuspend. * - * \ - * @arg Requires prerequisite that R_RSIP_SHA_Init, R_RSIP_SHA_Update, or R_RSIP_SHA_Resume results in FSP_SUCCESS. + * @par State transition + * @parblock + * This API can only be executed in **STATE_SHA**, and causes state transition. * - * \
- * This API can only be executed in the STATE_SHA, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_SUCCESS
FSP_ERR_CRYPTO_RSIP_FATAL		STATE_MAIN
OthersNo change
+ * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |Others |No change | + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. -**********************************************************************************************************************/ + **********************************************************************************************************************/ fsp_err_t R_RSIP_SHA_Suspend (rsip_ctrl_t * const p_ctrl, rsip_sha_handle_t * const p_handle) { rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; @@ -345,18 +328,19 @@ fsp_err_t R_RSIP_SHA_Suspend (rsip_ctrl_t * const p_ctrl, rsip_sha_handle_t * co } /*******************************************************************************************************************//** - * Resume SHA generation. - * This API allows you to resume a process that has been suspended by R_RSIP_SHA_Suspend() API.
+ * Resumes SHA operation suspended by R_RSIP_SHA_Suspend(). + * * Implements @ref rsip_api_t::shaResume. * - * \
- * This API can only be executed in the STATE_MAIN, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_SUCCESSSTATE_SHA
OthersNo change
+ * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_SHA | + * |Others |No change | + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -386,32 +370,31 @@ fsp_err_t R_RSIP_SHA_Resume (rsip_ctrl_t * const p_ctrl, rsip_sha_handle_t const } /*******************************************************************************************************************//** - * Generates HMAC.
+ * Generates HMAC. + * * Implements @ref rsip_api_t::hmacCompute. * - * \ - * @arg The key type of p_wrapped_key must be RSIP_KEY_TYPE_HMAC_xxx. - * @arg The length of MAC is the list below. - * - * - * - * - *
HMAC TypeMAC length
HMAC-SHA25632
+ * @par Conditions + * See R_RSIP_HMAC_Init(). + * + * @par Output length + * See R_RSIP_HMAC_SignFinish(). * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. - * @retval FSP_ERR_INVALID_ARGUMENT Input key type is illegal. * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. * * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_HMAC_Compute (rsip_ctrl_t * const p_ctrl, const rsip_wrapped_key_t * p_wrapped_key, @@ -430,7 +413,7 @@ fsp_err_t R_RSIP_HMAC_Compute (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); /* Check key type */ - FSP_ERROR_RETURN(RSIP_ALG_HMAC == p_wrapped_key->alg, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(RSIP_ALG_HMAC == p_wrapped_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ FSP_ERROR_RETURN(g_hmac_enabled[p_wrapped_key->subtype], FSP_ERR_NOT_ENABLED); @@ -475,20 +458,15 @@ fsp_err_t R_RSIP_HMAC_Compute (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Verifies HMAC.
+ * Verifies HMAC. + * * Implements @ref rsip_api_t::hmacVerify. * - * \ - * @arg The key type of p_wrapped_key must be RSIP_KEY_TYPE_HMAC_xxx. - * @arg The length of MAC must follow the list below. - * - * - * - * - *
HMAC TypeMAC length
HMAC-SHA2564 to 32
+ * @par Conditions + * See R_RSIP_HMAC_Init() and R_RSIP_HMAC_VerifyFinish(). * - * \
- * This API can only be executed in the STATE_MAIN, and there are no state transitions. + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. @@ -496,11 +474,13 @@ fsp_err_t R_RSIP_HMAC_Compute (rsip_ctrl_t * const p_ctrl, * @retval FSP_ERR_INVALID_STATE Internal state is illegal. * @retval FSP_ERR_INVALID_SIZE mac_length is illegal. * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. - * @retval FSP_ERR_INVALID_ARGUMENT Input key type is illegal. * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL MAC verification is failed. * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_HMAC_Verify (rsip_ctrl_t * const p_ctrl, const rsip_wrapped_key_t * p_wrapped_key, @@ -520,7 +500,7 @@ fsp_err_t R_RSIP_HMAC_Verify (rsip_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); /* Check key type */ - FSP_ERROR_RETURN(RSIP_ALG_HMAC == p_wrapped_key->alg, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(RSIP_ALG_HMAC == p_wrapped_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ FSP_ERROR_RETURN(g_hmac_enabled[p_wrapped_key->subtype], FSP_ERR_NOT_ENABLED); @@ -529,21 +509,8 @@ fsp_err_t R_RSIP_HMAC_Verify (rsip_ctrl_t * const p_ctrl, /* mac_length must be 4 or greater (common) */ FSP_ERROR_RETURN(4 <= mac_length, FSP_ERR_INVALID_SIZE); - uint8_t key_type = p_wrapped_key->subtype; - - /* mac_length must be 20 or less (SHA-1) */ - FSP_ERROR_RETURN((RSIP_KEY_HMAC_SHA1 != key_type) || (mac_length <= RSIP_PRV_BYTE_SIZE_DIGEST_SHA1), - FSP_ERR_INVALID_SIZE); - - /* mac_length must be 28 or less (SHA-224) */ - FSP_ERROR_RETURN((RSIP_KEY_HMAC_SHA224 != key_type) || - (mac_length <= RSIP_PRV_BYTE_SIZE_DIGEST_SHA224), - FSP_ERR_INVALID_SIZE); - - /* mac_length must be 32 or less (SHA-256) */ - FSP_ERROR_RETURN((RSIP_KEY_HMAC_SHA256 != key_type) || - (mac_length <= RSIP_PRV_BYTE_SIZE_DIGEST_SHA256), - FSP_ERR_INVALID_SIZE); + /* mac_length must be MAC size or less */ + FSP_ERROR_RETURN(mac_length <= gs_hmac_length[p_wrapped_key->subtype], FSP_ERR_INVALID_SIZE); /* Check state */ FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); @@ -588,31 +555,32 @@ fsp_err_t R_RSIP_HMAC_Verify (rsip_ctrl_t * const p_ctrl, } /*******************************************************************************************************************//** - * Prepares a HMAC generation.
+ * Starts HMAC operation. + * * Implements @ref rsip_api_t::hmacInit. * - * \ - * @arg The key type of p_wrapped_key must be RSIP_KEY_TYPE_HMAC_xxx. + * @par Conditions + * Key type of p_wrapped_key must be one of the following: + * - @ref RSIP_KEY_TYPE_HMAC_SHA256, @ref RSIP_KEY_TYPE_HMAC_SHA384, @ref RSIP_KEY_TYPE_HMAC_SHA512 * - * \
- * This API can only be executed in the STATE_MAIN, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_SUCCESSSTATE_HMAC
OthersNo change
+ * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_HMAC| + * |Others |No change | + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. - * @retval FSP_ERR_INVALID_ARGUMENT Input key type is illegal. - * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. - * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required - * by the processing is in use by other processing. - * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". **********************************************************************************************************************/ fsp_err_t R_RSIP_HMAC_Init (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_key) { @@ -624,7 +592,7 @@ fsp_err_t R_RSIP_HMAC_Init (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); /* Check key type */ - FSP_ERROR_RETURN(RSIP_ALG_HMAC == p_wrapped_key->alg, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(RSIP_ALG_HMAC == p_wrapped_key->alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); /* Check configuration */ FSP_ERROR_RETURN(g_hmac_enabled[p_wrapped_key->subtype], FSP_ERR_NOT_ENABLED); @@ -639,11 +607,35 @@ fsp_err_t R_RSIP_HMAC_Init (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const p_handle->buffered_length = 0; p_handle->total_length = 0; - /* Copy wrapped key */ - memcpy(p_handle->wrapped_key, p_wrapped_key, RSIP_BYTE_SIZE_WRAPPED_KEY_HMAC_SHA256); + /* Copy wrapped key & Set block size */ + switch(p_wrapped_key->subtype) + { + /* SHA-1, SHA-224, SHA-256 */ + case RSIP_KEY_HMAC_SHA1: + case RSIP_KEY_HMAC_SHA224: + case RSIP_KEY_HMAC_SHA256: + { + memcpy(p_handle->wrapped_key, p_wrapped_key, RSIP_BYTE_SIZE_WRAPPED_KEY_HMAC_SHA256); + p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA1_SHA224_SHA256; + break; + } - /* Set block size */ - p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA1_SHA224_SHA256; + /* SHA-384 */ + case RSIP_KEY_HMAC_SHA384: + { + memcpy(p_handle->wrapped_key, p_wrapped_key, RSIP_BYTE_SIZE_WRAPPED_KEY_HMAC_SHA384); + p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA384_SHA512; + break; + } + + /* SHA-512 */ + default: + { + memcpy(p_handle->wrapped_key, p_wrapped_key, RSIP_BYTE_SIZE_WRAPPED_KEY_HMAC_SHA512); + p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA384_SHA512; + break; + } + } /* State transition */ p_instance_ctrl->state = RSIP_STATE_HMAC; @@ -653,27 +645,18 @@ fsp_err_t R_RSIP_HMAC_Init (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const } /*******************************************************************************************************************//** - * Inputs message.
- * Implements @ref rsip_api_t::hmacUpdate. + * Inputs HMAC message. * - * \ - * @arg Requires prerequisite that R_RSIP_HMAC_Init, R_RSIP_HMAC_Update, or R_RSIP_HMAC_Resume results in FSP_SUCCESS. + * Implements @ref rsip_api_t::hmacUpdate. * - * \
- * This API can only be executed in the STATE_HMAC, and the state after execution changes as follows depending on the return value. - * - * - * - * - *
Return ValueState after execution
AnyNo change
+ * @par State transition + * This API can only be executed in **STATE_SHA**, and does not cause any state transitions. * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. - * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. - * @retval FSP_ERR_INVALID_ARGUMENT Input key type or mode is illegal. - * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. @@ -775,34 +758,34 @@ fsp_err_t R_RSIP_HMAC_Update (rsip_ctrl_t * const p_ctrl, uint8_t const * const } /*******************************************************************************************************************//** - * Finalizes a HMAC generation.
+ * Outputs HMAC. + * * Implements @ref rsip_api_t::hmacSignFinish. * - * \ - * @arg Requires prerequisite that R_RSIP_HMAC_Init, R_RSIP_HMAC_Update, or R_RSIP_HMAC_Resume results in FSP_SUCCESS. - * @arg The length of MAC is the list below. - * - * - * - * - *
HMAC TypeMAC length
HMAC-SHA25632
- * - * \
- * This API can only be executed in the STATE_HMAC, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_ERR_ASSERTION
FSP_ERR_NOT_OPEN
FSP_ERR_INVALID_STATE		No change
OthersSTATE_MAIN
+ * @par Output length + * Output length to p_mac depends on key type of p_wrapped_key. + * - 32 ( @ref RSIP_KEY_TYPE_HMAC_SHA256) + * - 48 ( @ref RSIP_KEY_TYPE_HMAC_SHA384) + * - 64 ( @ref RSIP_KEY_TYPE_HMAC_SHA512) + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_HMAC**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. - * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. - * @retval FSP_ERR_INVALID_ARGUMENT Input key type or mode is illegal. - * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. @@ -860,35 +843,36 @@ fsp_err_t R_RSIP_HMAC_SignFinish (rsip_ctrl_t * const p_ctrl, uint8_t * const p_ } /*******************************************************************************************************************//** - * Finalizes a HMAC verification.
+ * Verifies HMAC. + * * Implements @ref rsip_api_t::hmacVerifyFinish. * - * \ - * @arg Requires prerequisite that R_RSIP_HMAC_Init, R_RSIP_HMAC_Update, or R_RSIP_HMAC_Resume results in FSP_SUCCESS. - * @arg The length of MAC must follow the list below. - * - * - * - * - *
HMAC TypeMAC length
HMAC-SHA2564 to 32
- * - * \
- * This API can only be executed in the STATE_HMAC, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_ERR_ASSERTION
FSP_ERR_NOT_OPEN
FSP_ERR_INVALID_STATE
FSP_ERR_INVALID_SIZE		No change
OthersSTATE_MAIN
+ * @par Conditions + * Argument mac_length depends on key type of p_wrapped_key. Usually the longest length is recommended. + * - 4 to 32 ( @ref RSIP_KEY_TYPE_HMAC_SHA256) + * - 4 to 48 ( @ref RSIP_KEY_TYPE_HMAC_SHA384) + * - 4 to 64 ( @ref RSIP_KEY_TYPE_HMAC_SHA512) + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_HMAC**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |FSP_ERR_INVALID_SIZE |No change | + * |Others |STATE_MAIN| + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. * @retval FSP_ERR_INVALID_SIZE mac_length is illegal. - * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. - * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. - * @retval FSP_ERR_INVALID_ARGUMENT Input key type or mode is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. * @retval FSP_ERR_CRYPTO_RSIP_FAIL MAC verification is failed. * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required * by the processing is in use by other processing. @@ -960,31 +944,28 @@ fsp_err_t R_RSIP_HMAC_VerifyFinish (rsip_ctrl_t * const p_ctrl, uint8_t const * } /*******************************************************************************************************************//** - * Suspend HMAC generation. - * This API allows you to suspend processing, for example, if you are in the middle of computing HMAC for successive chunks of the message and need to perform another process.
+ * Suspends HMAC operation. + * + * This API releases RSIP resource and outputs intermediate results. Therefore, it can be used in the following cases: + * - Execute another cryptographic operations during inputting successive chunks of the message. + * - Reuse intermediate results. + * * Implements @ref rsip_api_t::hmacSuspend. * - * \ - * @arg Requires prerequisite that R_RSIP_HMAC_Init, R_RSIP_HMAC_Update, or R_RSIP_HMAC_Resume results in FSP_SUCCESS. + * @par State transition + * @parblock + * This API can only be executed in **STATE_HMAC**, and causes state transition. * - * \
- * This API can only be executed in the STATE_HMAC, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_SUCCESS
FSP_ERR_CRYPTO_RSIP_FATAL		STATE_MAIN
OthersNo change
+ * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |Others |No change | + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. - * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. - * @retval FSP_ERR_INVALID_ARGUMENT Input key type or mode is illegal. - * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. - * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required - * by the processing is in use by other processing. * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. **********************************************************************************************************************/ fsp_err_t R_RSIP_HMAC_Suspend (rsip_ctrl_t * const p_ctrl, rsip_hmac_handle_t * const p_handle) @@ -1046,29 +1027,24 @@ fsp_err_t R_RSIP_HMAC_Suspend (rsip_ctrl_t * const p_ctrl, rsip_hmac_handle_t * } /*******************************************************************************************************************//** - * Resume HMAC generation. - * This API allows you to resume a process that has been suspended by R_RSIP_HMAC_Suspend() API.
+ * Resumes HMAC operation suspended by R_RSIP_HMAC_Suspend(). + * * Implements @ref rsip_api_t::hmacResume. * - * \
- * This API can only be executed in the STATE_MAIN, and the state after execution changes as follows depending on the return value. - * - * - * - * - * - *
Return ValueState after execution
FSP_SUCCESSSTATE_HMAC
OthersNo change
+ * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_HMAC| + * |Others |No change | + * @endparblock * * @retval FSP_SUCCESS Normal termination. * @retval FSP_ERR_ASSERTION A required parameter is NULL. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_INVALID_STATE Internal state is illegal. - * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. - * @retval FSP_ERR_INVALID_ARGUMENT Input key type or mode is illegal. - * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. - * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required - * by the processing is in use by other processing. - * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. **********************************************************************************************************************/ fsp_err_t R_RSIP_HMAC_Resume (rsip_ctrl_t * const p_ctrl, rsip_hmac_handle_t const * const p_handle) { @@ -1294,6 +1270,15 @@ fsp_err_t r_rsip_sha_finish (rsip_ctrl_t * const p_ctrl, uint8_t * const p_diges * Private Functions **********************************************************************************************************************/ +/*******************************************************************************************************************//** + * Inputs message. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message (0 or more bytes). + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ static rsip_ret_t sha_update (rsip_ctrl_t * const p_ctrl, const uint8_t * p_message, uint32_t message_length) { rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; @@ -1341,6 +1326,14 @@ static rsip_ret_t sha_update (rsip_ctrl_t * const p_ctrl, const uint8_t * p_mess return ret; } +/*******************************************************************************************************************//** + * Finalizes a SHA generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_digest Pointer to destination of message digest. The length depends on hash type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ static rsip_ret_t sha_finish (rsip_ctrl_t * const p_ctrl, uint8_t * p_digest) { rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; @@ -1383,6 +1376,15 @@ static rsip_ret_t sha_finish (rsip_ctrl_t * const p_ctrl, uint8_t * p_digest) return ret; } +/*******************************************************************************************************************//** + * Inputs message. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message (0 or more bytes). + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ static rsip_ret_t hmac_update (rsip_ctrl_t * const p_ctrl, const uint8_t * p_message, uint32_t message_length) { rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; @@ -1439,6 +1441,14 @@ static rsip_ret_t hmac_update (rsip_ctrl_t * const p_ctrl, const uint8_t * p_mes return ret; } +/*******************************************************************************************************************//** + * Finalizes a HMAC generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_mac Pointer to destination of message digest. The length depends on MAC type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ static rsip_ret_t hmac_sign_finish (rsip_ctrl_t * const p_ctrl, uint8_t * p_mac) { rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; @@ -1485,6 +1495,15 @@ static rsip_ret_t hmac_sign_finish (rsip_ctrl_t * const p_ctrl, uint8_t * p_mac) return ret; } +/*******************************************************************************************************************//** + * Finalizes a HMAC verification. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_mac Pointer to MAC. The length depends on mac_length. + * @param[in] mac_length Byte length of MAC. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ static rsip_ret_t hmac_verify_finish (rsip_ctrl_t * const p_ctrl, const uint8_t * p_mac, const uint32_t mac_length) { rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p72.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p72.c deleted file mode 100644 index 001fba2b3..000000000 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p72.c +++ /dev/null @@ -1,356 +0,0 @@ -/* -* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "r_rsip_primitive.h" -#include "r_rsip_reg.h" -#include "r_rsip_util.h" - -/*********************************************************************************************************************** - * Functions - **********************************************************************************************************************/ - -rsip_ret_t r_rsip_p72 (const uint32_t InData_HashType[], - const uint32_t InData_Cmd[], - const uint32_t InData_Msg[], - const uint32_t InData_MsgLen[], - const uint32_t InData_State[], - uint32_t OutData_MsgDigest[], - uint32_t OutData_State[], - uint32_t MAX_CNT) -{ - uint32_t iLoop = 0U; - - if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) - { - return RSIP_RET_RESOURCE_CONFLICT; - } - else - { - ; - } - - WR1_PROG(REG_1B00H, 0x00720001U); - WR1_PROG(REG_144CH, 0x00000000U); - - r_rsip_func100(bswap_32big(0x9c7d57acU), bswap_32big(0xbeaca82cU), bswap_32big(0x1ed3bda7U), bswap_32big(0x9c158296U)); - WR1_PROG(REG_2000H, 0x00000001U); - - WR1_PROG(REG_1444H, 0x000001c7U); - WR1_PROG(REG_1608H, 0x80020000U); - WAIT_STS(REG_1444H, 31, 1); - WR1_PROG(REG_1420H, InData_HashType[0]); - WAIT_STS(REG_1444H, 31, 1); - WR1_PROG(REG_1420H, InData_Cmd[0]); - WR1_PROG(REG_1458H, 0x00000000U); - - WR1_PROG(REG_1600H, 0x3420a800U); - WR1_PROG(REG_1600H, 0x00000007U); - WR1_PROG(REG_1600H, 0x2000b400U); - WR1_PROG(REG_1600H, 0x00000006U); - - WR1_PROG(REG_1600H, 0x3420a820U); - WR1_PROG(REG_1600H, 0x00000004U); - WR1_PROG(REG_1600H, 0x2000b420U); - WR1_PROG(REG_1600H, 0x00000003U); - - WR1_PROG(REG_1600H, 0x000037e1U); - WR1_PROG(REG_1600H, 0x00008fe0U); - WR1_PROG(REG_1600H, 0x00000002U); - WR1_PROG(REG_1600H, 0x00046fffU); - - WR1_PROG(REG_1600H, 0x000013e0U); - - WR1_PROG(REG_1600H, 0x00007c1fU); - WR1_PROG(REG_143CH, 0x00600000U); - WR1_PROG(REG_1458H, 0x00000000U); - - if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) - { - WR1_PROG(REG_2004H, 0x00000000U); - - r_rsip_func101(bswap_32big(0xa9ba84c2U), bswap_32big(0x726aebd1U), bswap_32big(0x17713092U), bswap_32big(0x5399ff62U)); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000020U) - { - WR1_PROG(REG_2004H, 0x00001000U); - - r_rsip_func101(bswap_32big(0x2dba89daU), bswap_32big(0x55835517U), bswap_32big(0x8ac417eeU), bswap_32big(0x1113c758U)); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) - { - WR1_PROG(REG_2004H, 0x00000040U); - - r_rsip_func101(bswap_32big(0xb8288ecbU), bswap_32big(0x616da1b0U), bswap_32big(0x4d78c61bU), bswap_32big(0xeaed7b7cU)); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000021U) - { - WR1_PROG(REG_2004H, 0x00001040U); - - r_rsip_func101(bswap_32big(0x7ea05301U), bswap_32big(0x0644c4d7U), bswap_32big(0xb80da9abU), bswap_32big(0xa3ce0fcfU)); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) - { - WR1_PROG(REG_2004H, 0x00000050U); - - r_rsip_func101(bswap_32big(0xf8ee8793U), bswap_32big(0x30a900ddU), bswap_32big(0xa41cb008U), bswap_32big(0xa112043aU)); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000022U) - { - WR1_PROG(REG_2004H, 0x00001050U); - - r_rsip_func101(bswap_32big(0xa1612261U), bswap_32big(0x7bc298f2U), bswap_32big(0x88cf1842U), bswap_32big(0xf7ff5ed7U)); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) - { - WR1_PROG(REG_2004H, 0x00000080U); - - r_rsip_func101(bswap_32big(0x49f1bd01U), bswap_32big(0x208c73cbU), bswap_32big(0x41a4334eU), bswap_32big(0x5b2c8152U)); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000023U) - { - WR1_PROG(REG_2004H, 0x00001080U); - - r_rsip_func101(bswap_32big(0x080020a0U), bswap_32big(0xd6317bbaU), bswap_32big(0x1692e712U), bswap_32big(0x683fa089U)); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) - { - WR1_PROG(REG_2004H, 0x00000090U); - - r_rsip_func101(bswap_32big(0xb88e7b35U), bswap_32big(0x51bf2974U), bswap_32big(0x30e07cbaU), bswap_32big(0x99136c0eU)); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000024U) - { - WR1_PROG(REG_2004H, 0x00001090U); - - r_rsip_func101(bswap_32big(0x0e03211dU), bswap_32big(0x567ac0b4U), bswap_32big(0x944cc54cU), bswap_32big(0xbcda2403U)); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000005U) - { - WR1_PROG(REG_2004H, 0x000000a0U); - - r_rsip_func101(bswap_32big(0x5d70f497U), bswap_32big(0x989f2d80U), bswap_32big(0xc35fa8ebU), bswap_32big(0xca6496d3U)); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000025U) - { - WR1_PROG(REG_2004H, 0x000010a0U); - - r_rsip_func101(bswap_32big(0x7004d3b1U), bswap_32big(0x47bb832bU), bswap_32big(0x69b07a26U), bswap_32big(0x67477513U)); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) - { - WR1_PROG(REG_2004H, 0x000000b0U); - - r_rsip_func101(bswap_32big(0x494bd172U), bswap_32big(0x004530f0U), bswap_32big(0xda7913ceU), bswap_32big(0x9143c668U)); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000026U) - { - WR1_PROG(REG_2004H, 0x000010b0U); - - r_rsip_func101(bswap_32big(0xf4a051abU), bswap_32big(0x524ba351U), bswap_32big(0x08143ec2U), bswap_32big(0x8f7fa5a7U)); - } - - WR1_PROG(REG_1600H, 0x38008c20U); - WR1_PROG(REG_1600H, 0x00000002U); - WR1_PROG(REG_1608H, 0x00000080U); - WR1_PROG(REG_143CH, 0x00260000U); - - r_rsip_func100(bswap_32big(0xdfaf1cfdU), bswap_32big(0x9869e0cbU), bswap_32big(0xa569168bU), bswap_32big(0xd57a78c8U)); - WR1_PROG(REG_143CH, 0x00400000U); - - if (CHCK_STS(REG_143CH, 22, 1)) - { - if ((InData_MsgLen[0] == 0) && (InData_MsgLen[1] == 0)) - { - WR1_PROG(REG_200CH, 0x00000100U); - - r_rsip_func101(bswap_32big(0x89919595U), bswap_32big(0x3de2459dU), bswap_32big(0xcf5b8127U), bswap_32big(0xe411f0f8U)); - } - else - { - WR1_PROG(REG_1444H, 0x00000040U); - WR1_PROG(REG_2014H, InData_MsgLen[0]); - WR1_PROG(REG_1444H, 0x00000040U); - WR1_PROG(REG_2010H, InData_MsgLen[1]); - - r_rsip_func101(bswap_32big(0xd7e31e84U), bswap_32big(0x9e7f306dU), bswap_32big(0xe7ffdc84U), bswap_32big(0x1a9e1b34U)); - } - } - else - { - WR1_PROG(REG_1444H, 0x00000040U); - WR1_PROG(REG_2014H, InData_State[18]); - WR1_PROG(REG_1444H, 0x00000040U); - WR1_PROG(REG_2010H, InData_State[19]); - - for (iLoop = 0U; iLoop < 18U; iLoop++) - { - WR1_PROG(REG_1444H, 0x00000040U); - WR1_PROG(REG_2028H, InData_State[iLoop]); - } - - WR1_PROG(REG_1458H, 0x00000000U); - - r_rsip_func101(bswap_32big(0xa13b88e9U), bswap_32big(0x39c55df6U), bswap_32big(0x8ce8ebfdU), bswap_32big(0xcef4c7a0U)); - } - - WR1_PROG(REG_1444H, 0x00020064U); - - for (iLoop = 0U; iLoop < (MAX_CNT & 0xfffffff0U); ) - { - WAIT_STS(REG_1444H, 31, 1); - WR16_ADDR(REG_1420H, &InData_Msg[iLoop]); - - iLoop = iLoop + 16U; - } - - WR1_PROG(REG_1458H, 0x00000000U); - - WAIT_STS(REG_1444H, 31, 1); - for (iLoop = (MAX_CNT & 0xfffffff0U); iLoop < MAX_CNT; iLoop++) - { - WR1_PROG(REG_1420H, InData_Msg[iLoop]); - } - - WR1_PROG(REG_1458H, 0x00000000U); - - WR1_PROG(REG_1444H, 0x00000000U); - - WR1_PROG(REG_1600H, 0x38008820U); - WR1_PROG(REG_1600H, 0x00000001U); - WR1_PROG(REG_1608H, 0x00000080U); - WR1_PROG(REG_143CH, 0x00260000U); - - WR1_PROG(REG_1600H, 0x38008820U); - WR1_PROG(REG_1600H, 0x00000002U); - WR1_PROG(REG_1608H, 0x00000080U); - WR1_PROG(REG_143CH, 0x00260000U); - - r_rsip_func100(bswap_32big(0xb976fc9eU), bswap_32big(0x59d68416U), bswap_32big(0x60c329f3U), bswap_32big(0xdcfadda5U)); - WR1_PROG(REG_143CH, 0x00400000U); - - if (CHCK_STS(REG_143CH, 22, 1)) - { - WAIT_STS(REG_2030H, 8, 0); - for (iLoop = 0U; iLoop < 18U; iLoop++) - { - RD1_ADDR(REG_202CH, &OutData_State[iLoop]); - } - - WR1_PROG(REG_1458H, 0x00000000U); - - RD1_ADDR(REG_2014H, &OutData_State[18]); - RD1_ADDR(REG_2010H, &OutData_State[19]); - - r_rsip_func102(bswap_32big(0x9dbedc0fU), bswap_32big(0xd371c17cU), bswap_32big(0x609681e2U), bswap_32big(0x443ae86aU)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12, 0); - } - else - { - WAIT_STS(REG_2030H, 4, 1); - - r_rsip_func100(bswap_32big(0xbf38f3fcU), bswap_32big(0x0453199eU), bswap_32big(0x46e9af40U), bswap_32big(0x39e84223U)); - WR1_PROG(REG_1600H, 0x38008800U); - WR1_PROG(REG_1600H, 0x00000003U); - WR1_PROG(REG_1600H, 0x1000b400U); - WR1_PROG(REG_1600H, 0x00000001U); - - WR1_PROG(REG_1600H, 0x38008800U); - WR1_PROG(REG_1600H, 0x00000004U); - WR1_PROG(REG_1600H, 0x1000b400U); - WR1_PROG(REG_1600H, 0x00000002U); - - WR1_PROG(REG_1600H, 0x00007c00U); - WR1_PROG(REG_143CH, 0x00600000U); - WR1_PROG(REG_1458H, 0x00000000U); - - if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) - { - r_rsip_func100(bswap_32big(0xdfd99981U), bswap_32big(0xd4a308d7U), bswap_32big(0x328e83b5U), bswap_32big(0x6331a945U)); - WR1_PROG(REG_1408H, 0x00004016U); - for (iLoop = 0U; iLoop < 5U; iLoop++) - { - WAIT_STS(REG_1408H, 30, 1); - RD1_ADDR(REG_1420H, &OutData_MsgDigest[iLoop]); - } - - WR1_PROG(REG_1458H, 0x00000000U); - - r_rsip_func102(bswap_32big(0x02f230c0U), bswap_32big(0x7e3d0402U), bswap_32big(0x7cf07aa7U), bswap_32big(0x0d7cd872U)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12, 0); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) - { - r_rsip_func100(bswap_32big(0x9f247c53U), bswap_32big(0x21f860a7U), bswap_32big(0x9e5bccf7U), bswap_32big(0x5f5ba292U)); - WR1_PROG(REG_1408H, 0x0000401eU); - for (iLoop = 0U; iLoop < 7U; iLoop++) - { - WAIT_STS(REG_1408H, 30, 1); - RD1_ADDR(REG_1420H, &OutData_MsgDigest[iLoop]); - } - - WR1_PROG(REG_1458H, 0x00000000U); - - r_rsip_func102(bswap_32big(0x026ed8ebU), bswap_32big(0x7e3fa35eU), bswap_32big(0x4bd92ca8U), bswap_32big(0x6a1114acU)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12, 0); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) - { - r_rsip_func100(bswap_32big(0xfaaaffb1U), bswap_32big(0x87c613f3U), bswap_32big(0xf021065aU), bswap_32big(0x2923a7e6U)); - WR1_PROG(REG_1408H, 0x00004022U); - for (iLoop = 0U; iLoop < 8U; iLoop++) - { - WAIT_STS(REG_1408H, 30, 1); - RD1_ADDR(REG_1420H, &OutData_MsgDigest[iLoop]); - } - - WR1_PROG(REG_1458H, 0x00000000U); - - r_rsip_func102(bswap_32big(0x6938f984U), bswap_32big(0x8cdbb61aU), bswap_32big(0x55ed2f1aU), bswap_32big(0xa123726aU)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12, 0); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000005U) - { - r_rsip_func100(bswap_32big(0x2e7de48fU), bswap_32big(0x16d7f06bU), bswap_32big(0x1e5549beU), bswap_32big(0xbe20d002U)); - WR1_PROG(REG_1408H, 0x00004032U); - for (iLoop = 0U; iLoop < 12U; iLoop++) - { - WAIT_STS(REG_1408H, 30, 1); - RD1_ADDR(REG_1420H, &OutData_MsgDigest[iLoop]); - } - - WR1_PROG(REG_1458H, 0x00000000U); - - r_rsip_func102(bswap_32big(0x96e45d57U), bswap_32big(0x4710eb89U), bswap_32big(0x661e8bc1U), bswap_32big(0x6069da36U)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12, 0); - } - else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) - { - r_rsip_func100(bswap_32big(0x010601baU), bswap_32big(0x9fd9defeU), bswap_32big(0xf5c220f4U), bswap_32big(0x04bc24b8U)); - WR1_PROG(REG_1408H, 0x00004042U); - for (iLoop = 0U; iLoop < 16U; iLoop++) - { - WAIT_STS(REG_1408H, 30, 1); - RD1_ADDR(REG_1420H, &OutData_MsgDigest[iLoop]); - } - - WR1_PROG(REG_1458H, 0x00000000U); - - r_rsip_func102(bswap_32big(0x1d244f62U), bswap_32big(0x5e06ae9fU), bswap_32big(0xef50dcd9U), bswap_32big(0xd231116bU)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12, 0); - } - } - - return RSIP_RET_PASS; -} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p75f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p75f.c deleted file mode 100644 index c6291765a..000000000 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p75f.c +++ /dev/null @@ -1,259 +0,0 @@ -/* -* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "r_rsip_primitive.h" -#include "r_rsip_reg.h" -#include "r_rsip_util.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Private function prototypes - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Private global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Functions - **********************************************************************************************************************/ - -RSIP_PRV_PRIMITIVE_FUNC - -rsip_ret_t r_rsip_p75f(const uint32_t InData_Cmd[], const uint32_t InData_Msg[], const uint32_t InData_MAC[], const uint32_t InData_length[], uint32_t MAX_CNT, uint32_t OutData_MAC[]) -{ - uint32_t iLoop; - uint32_t jLoop; - uint32_t kLoop; - uint32_t oLoop; - uint32_t oLoop1; - uint32_t OFS_ADR; - (void) iLoop; - (void) jLoop; - (void) kLoop; - (void) oLoop; - (void) oLoop1; - (void) OFS_ADR; - WAIT_STS(REG_2030H, 0U, 1U); - WR1_PROG(REG_1444H, 0x00020064U); - for (iLoop = 0; iLoop < (MAX_CNT & 0xfffffff0U); iLoop = iLoop + 16) - { - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 0]); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 1]); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 2]); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 3]); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 4]); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 5]); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 6]); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 7]); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 8]); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 9]); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 10]); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 11]); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 12]); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 13]); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 14]); - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 15]); - } - WR1_PROG(REG_1458H, 0x00000000U); - WAIT_STS(REG_1444H, 31U, 1U); - for (iLoop = (MAX_CNT & 0xfffffff0U); iLoop < MAX_CNT; iLoop = iLoop + 1) - { - WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 0]); - } - WR1_PROG(REG_1458H, 0x00000000U); - WR1_PROG(REG_1444H, 0x00000000U); - WAIT_STS(REG_2030H, 8U, 0U); - WR1_PROG(REG_143CH, 0x00001600U); - WAIT_STS(REG_2030H, 4U, 1U); - WR1_PROG(REG_1444H, 0x000000c7U); - WR1_PROG(REG_1608H, 0x80010000U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_Cmd[0]); - WR1_PROG(REG_1458H, 0x00000000U); - WR1_PROG(REG_1600H, 0x38000c00U); - WR1_PROG(REG_1608H, 0x00000080U); - WR1_PROG(REG_143CH, 0x00260000U); - r_rsip_func100(bswap_32big(0xc44e575fU), bswap_32big(0xb39d73feU), bswap_32big(0x3129abb9U), bswap_32big(0xefe727d9U)); - WR1_PROG(REG_143CH, 0x00400000U); - if (CHCK_STS(REG_143CH, 22U, 1U)) - { - r_rsip_func100(bswap_32big(0xc47987c4U), bswap_32big(0x77e43a73U), bswap_32big(0xfb0db761U), bswap_32big(0x37e78ca7U)); - WR1_PROG(REG_1600H, 0x00007c04U); - WR1_PROG(REG_143CH, 0x00600000U); - WR1_PROG(REG_1458H, 0x00000000U); - if (0x00000001U == RD1_MASK(REG_1440H, 0xffffffffU)) - { - r_rsip_func100(bswap_32big(0x4387084cU), bswap_32big(0x039b42dcU), bswap_32big(0x91e98272U), bswap_32big(0x64ff31d4U)); - WR1_PROG(REG_1408H, 0x0000401eU); - WAIT_STS(REG_1408H, 30U, 1U); - RD1_ADDR(REG_1420H, &OutData_MAC[0]); - RD1_ADDR(REG_1420H, &OutData_MAC[1]); - RD1_ADDR(REG_1420H, &OutData_MAC[2]); - RD1_ADDR(REG_1420H, &OutData_MAC[3]); - RD1_ADDR(REG_1420H, &OutData_MAC[4]); - RD1_ADDR(REG_1420H, &OutData_MAC[5]); - RD1_ADDR(REG_1420H, &OutData_MAC[6]); - r_rsip_func102(bswap_32big(0xfaa1e43fU), bswap_32big(0x7c268b13U), bswap_32big(0x2e363126U), bswap_32big(0x3bfa9bd2U)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12U, 0U); - } - else if (0x00000002U == RD1_MASK(REG_1440H, 0xffffffffU)) - { - r_rsip_func100(bswap_32big(0x22dc5cd1U), bswap_32big(0x3346fef7U), bswap_32big(0x3a0fbc41U), bswap_32big(0x7009ed0fU)); - WR1_PROG(REG_1408H, 0x00004022U); - WAIT_STS(REG_1408H, 30U, 1U); - RD1_ADDR(REG_1420H, &OutData_MAC[0]); - RD1_ADDR(REG_1420H, &OutData_MAC[1]); - RD1_ADDR(REG_1420H, &OutData_MAC[2]); - RD1_ADDR(REG_1420H, &OutData_MAC[3]); - RD1_ADDR(REG_1420H, &OutData_MAC[4]); - RD1_ADDR(REG_1420H, &OutData_MAC[5]); - RD1_ADDR(REG_1420H, &OutData_MAC[6]); - RD1_ADDR(REG_1420H, &OutData_MAC[7]); - r_rsip_func102(bswap_32big(0x0960b3c3U), bswap_32big(0xacd09037U), bswap_32big(0x3c995204U), bswap_32big(0xb984ea7aU)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12U, 0U); - } - return RSIP_RET_PASS; - } - else - { - r_rsip_func100(bswap_32big(0x4b1aa99eU), bswap_32big(0xeabb1579U), bswap_32big(0x15cbc62eU), bswap_32big(0x6f9236e9U)); - WR1_PROG(REG_1444H, 0x000000c7U); - WR1_PROG(REG_1608H, 0x80010020U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_length[0]); - WR1_PROG(REG_1458H, 0x00000000U); - WR1_PROG(REG_1600H, 0x00000bffU); - WR1_PROG(REG_1600H, 0x00007c04U); - WR1_PROG(REG_143CH, 0x00600000U); - WR1_PROG(REG_1458H, 0x00000000U); - if (0x00000001U == RD1_MASK(REG_1440H, 0xffffffffU)) - { - WR1_PROG(REG_1600H, 0x0000b440U); - WR1_PROG(REG_1600H, 0x0000001cU); - WR1_PROG(REG_1608H, 0x8087001fU); - WR1_PROG(REG_1400H, 0x0345001dU); - WAIT_STS(REG_1404H, 30U, 0U); - WR1_PROG(REG_143CH, 0x00001800U); - r_rsip_func101(bswap_32big(0xef01c17bU), bswap_32big(0x1e70d54eU), bswap_32big(0x3af3aa3eU), bswap_32big(0xd5c09bbfU)); - } - else if (0x00000002U == RD1_MASK(REG_1440H, 0xffffffffU)) - { - WR1_PROG(REG_1600H, 0x0000b440U); - WR1_PROG(REG_1600H, 0x00000020U); - WR1_PROG(REG_1608H, 0x8088001fU); - WR1_PROG(REG_1400H, 0x03450021U); - WAIT_STS(REG_1404H, 30U, 0U); - WR1_PROG(REG_143CH, 0x00001800U); - r_rsip_func101(bswap_32big(0xfd9973baU), bswap_32big(0x4d429b96U), bswap_32big(0x46d79ef3U), bswap_32big(0x018ae101U)); - } - WR1_PROG(REG_1600H, 0x3420a820U); - WR1_PROG(REG_1600H, 0x00000004U); - WR1_PROG(REG_1608H, 0x00000080U); - WR1_PROG(REG_143CH, 0x00260000U); - WR1_PROG(REG_1600H, 0x34202841U); - WR1_PROG(REG_1608H, 0x00000080U); - WR1_PROG(REG_143CH, 0x00260000U); - r_rsip_func100(bswap_32big(0x288cc714U), bswap_32big(0xb2576d89U), bswap_32big(0x51b3dbd5U), bswap_32big(0x74dda411U)); - WR1_PROG(REG_143CH, 0x00400000U); - if (CHCK_STS(REG_143CH, 22U, 1U)) - { - r_rsip_func102(bswap_32big(0xa591d5d6U), bswap_32big(0x0db6ba0aU), bswap_32big(0xc58cd089U), bswap_32big(0xe475a057U)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12U, 0U); - return RSIP_RET_FAIL; - } - else - { - r_rsip_func100(bswap_32big(0x688a64eeU), bswap_32big(0x93798cffU), bswap_32big(0xa26efb8bU), bswap_32big(0x3290d0bbU)); - WR1_PROG(REG_1600H, 0x00000800U); - for (iLoop = 0; iLoop < 32; iLoop = iLoop + 1) - { - WR1_PROG(REG_1600H, 0x3c002be1U); - WR1_PROG(REG_1600H, 0x12003c1fU); - WR1_PROG(REG_1600H, 0x00002fe0U); - } - WR1_PROG(REG_1458H, 0x00000000U); - WR1_PROG(REG_1444H, 0x000003c1U); - WR1_PROG(REG_1824H, 0x08000045U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_MAC[0]); - WR1_ADDR(REG_1420H, &InData_MAC[1]); - WR1_ADDR(REG_1420H, &InData_MAC[2]); - WR1_ADDR(REG_1420H, &InData_MAC[3]); - WR1_PROG(REG_1600H, 0x00007c04U); - WR1_PROG(REG_143CH, 0x00600000U); - WR1_PROG(REG_1458H, 0x00000000U); - if (0x00000001U == RD1_MASK(REG_1440H, 0xffffffffU)) - { - WR1_PROG(REG_1444H, 0x000002c1U); - WR1_PROG(REG_1824H, 0x08000055U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_MAC[4]); - WR1_ADDR(REG_1420H, &InData_MAC[5]); - WR1_ADDR(REG_1420H, &InData_MAC[6]); - WR1_PROG(REG_1444H, 0x000000a1U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); - r_rsip_func101(bswap_32big(0xc8ac7616U), bswap_32big(0x351436c9U), bswap_32big(0xf3f41ccbU), bswap_32big(0xe91d1f24U)); - } - else if (0x00000002U == RD1_MASK(REG_1440H, 0xffffffffU)) - { - WR1_PROG(REG_1444H, 0x000003c1U); - WR1_PROG(REG_1824H, 0x08000055U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_MAC[4]); - WR1_ADDR(REG_1420H, &InData_MAC[5]); - WR1_ADDR(REG_1420H, &InData_MAC[6]); - WR1_ADDR(REG_1420H, &InData_MAC[7]); - r_rsip_func101(bswap_32big(0xf1bd805bU), bswap_32big(0x9ce4677dU), bswap_32big(0xe51a5347U), bswap_32big(0xdcfd9f97U)); - } - WR1_PROG(REG_1824H, 0x9c000005U); - WR1_PROG(REG_1600H, 0x00000bffU); - WR1_PROG(REG_1608H, 0x8188001fU); - WR1_PROG(REG_1400H, 0x00490011U); - WAIT_STS(REG_1404H, 30U, 0U); - WR1_PROG(REG_143CH, 0x00001800U); - WR1_PROG(REG_1824H, 0x9c100005U); - WR1_PROG(REG_1400H, 0x00490011U); - WAIT_STS(REG_1404H, 30U, 0U); - WR1_PROG(REG_143CH, 0x00001800U); - r_rsip_func100(bswap_32big(0xc1b12739U), bswap_32big(0x7fd5ab38U), bswap_32big(0xca5442adU), bswap_32big(0xc9e6552eU)); - WR1_PROG(REG_143CH, 0x00400000U); - if (CHCK_STS(REG_143CH, 22U, 1U)) - { - r_rsip_func102(bswap_32big(0x52899ab2U), bswap_32big(0xfcab71f2U), bswap_32big(0x38b08f52U), bswap_32big(0xba097eefU)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12U, 0U); - return RSIP_RET_FAIL; - } - else - { - r_rsip_func102(bswap_32big(0xc413d555U), bswap_32big(0xa617b5c5U), bswap_32big(0x4b437611U), bswap_32big(0x5e596223U)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12U, 0U); - return RSIP_RET_PASS; - } - } - } -} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p75i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p75i.c deleted file mode 100644 index d8c35200b..000000000 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p75i.c +++ /dev/null @@ -1,190 +0,0 @@ -/* -* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "r_rsip_primitive.h" -#include "r_rsip_reg.h" -#include "r_rsip_util.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Private function prototypes - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Private global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Functions - **********************************************************************************************************************/ - -RSIP_PRV_PRIMITIVE_FUNC - -rsip_ret_t r_rsip_p75i(const uint32_t InData_KeyIndex[], const uint32_t InData_HashType[], const uint32_t InData_MsgLen[]) -{ - uint32_t iLoop; - uint32_t jLoop; - uint32_t kLoop; - uint32_t oLoop; - uint32_t oLoop1; - uint32_t OFS_ADR; - (void) iLoop; - (void) jLoop; - (void) kLoop; - (void) oLoop; - (void) oLoop1; - (void) OFS_ADR; - if (0x0U != RD1_MASK(REG_14BCH, 0x1fU)) - { - return RSIP_RET_RESOURCE_CONFLICT; - } - WR1_PROG(REG_1B00H, 0x00750001U); - WR1_PROG(REG_144CH, 0x00000000U); - WR1_PROG(REG_2000H, 0x00000001U); - WR1_PROG(REG_1444H, 0x000000c7U); - WR1_PROG(REG_1608H, 0x80010080U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_HashType[0]); - WR1_PROG(REG_1458H, 0x00000000U); - WR1_PROG(REG_1600H, 0x38000c84U); - WR1_PROG(REG_1608H, 0x00000080U); - WR1_PROG(REG_143CH, 0x00260000U); - r_rsip_func100(bswap_32big(0x2d865bb4U), bswap_32big(0x73643b86U), bswap_32big(0x5d89599aU), bswap_32big(0x2e5e2b92U)); - WR1_PROG(REG_143CH, 0x00400000U); - if (CHCK_STS(REG_143CH, 22U, 1U)) - { - r_rsip_func102(bswap_32big(0x7155a1a7U), bswap_32big(0x1ba2bb55U), bswap_32big(0x7b41333cU), bswap_32big(0x452ff8b9U)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12U, 0U); - return RSIP_RET_FAIL; - } - else - { - r_rsip_func100(bswap_32big(0xb2423b2cU), bswap_32big(0x407fffe2U), bswap_32big(0x9ffd1181U), bswap_32big(0x17e7247fU)); - WR1_PROG(REG_1600H, 0x3420a880U); - WR1_PROG(REG_1600H, 0x00000003U); - WR1_PROG(REG_1600H, 0x2000b480U); - WR1_PROG(REG_1600H, 0x00000002U); - WR1_PROG(REG_1600H, 0x00007c04U); - WR1_PROG(REG_143CH, 0x00600000U); - WR1_PROG(REG_1458H, 0x00000000U); - if (0x00000001U == RD1_MASK(REG_1440H, 0xffffffffU)) - { - WR1_PROG(REG_1600H, 0x0000b4e0U); - WR1_PROG(REG_1600H, 0x0000001aU); - WR1_PROG(REG_2004H, 0x00000040U); - r_rsip_func101(bswap_32big(0xf78e40adU), bswap_32big(0x67bb45d2U), bswap_32big(0x90e9b4ebU), bswap_32big(0x5f32c75cU)); - } - else if (0x00000002U == RD1_MASK(REG_1440H, 0xffffffffU)) - { - WR1_PROG(REG_1600H, 0x0000b4e0U); - WR1_PROG(REG_1600H, 0x0000001bU); - WR1_PROG(REG_2004H, 0x00000050U); - r_rsip_func101(bswap_32big(0xc681657bU), bswap_32big(0x83bbd9b7U), bswap_32big(0x6adeee4aU), bswap_32big(0x6b6c51c0U)); - } - WR1_PROG(REG_1600H, 0x00003507U); - WR1_PROG(REG_2008H, 0x00000003U); - WR1_PROG(REG_1444H, 0x000000c7U); - WR1_PROG(REG_1608H, 0x800100e0U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_KeyIndex[0]); - WR1_PROG(REG_1458H, 0x00000000U); - WR1_PROG(REG_1444H, 0x000000a7U); - WR1_PROG(REG_1608H, 0x800103a0U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_PROG(REG_1420H, bswap_32big(0x00007501U)); - WR1_PROG(REG_1458H, 0x00000000U); - r_rsip_func101(bswap_32big(0xd64429e9U), bswap_32big(0xbc447adfU), bswap_32big(0xe42feca2U), bswap_32big(0x61878b11U)); - r_rsip_func043(); - WR1_PROG(REG_1600H, 0x000034e8U); - WR1_PROG(REG_1444H, 0x000000a7U); - WR1_PROG(REG_1608H, 0x800103a0U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_PROG(REG_1420H, bswap_32big(0x00007501U)); - WR1_PROG(REG_1458H, 0x00000000U); - r_rsip_func101(bswap_32big(0x1575e632U), bswap_32big(0xd4f917a8U), bswap_32big(0x3f77633aU), bswap_32big(0x4734a1eaU)); - r_rsip_func044(); - WR1_PROG(REG_1444H, 0x000007c2U); - WR1_PROG(REG_1A2CH, 0x40000100U); - WR1_PROG(REG_1A24H, 0xf7009d07U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_KeyIndex[1]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[2]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[3]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[4]); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_KeyIndex[5]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[6]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[7]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[8]); - WR1_PROG(REG_1400H, 0x01420021U); - WAIT_STS(REG_1404H, 30U, 0U); - WR1_PROG(REG_143CH, 0x00001800U); - WR1_PROG(REG_1444H, 0x000003c2U); - WR1_PROG(REG_1A2CH, 0x40000000U); - WR1_PROG(REG_1A24H, 0x07008d05U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_KeyIndex[9]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[10]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[11]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[12]); - WR1_PROG(REG_1A24H, 0x9c100005U); - WR1_PROG(REG_1400H, 0x00820011U); - WAIT_STS(REG_1404H, 30U, 0U); - WR1_PROG(REG_143CH, 0x00001800U); - r_rsip_func100(bswap_32big(0x309228f2U), bswap_32big(0x0f8d7183U), bswap_32big(0x9283fff1U), bswap_32big(0x1196d251U)); - WR1_PROG(REG_143CH, 0x00400000U); - if (CHCK_STS(REG_143CH, 22U, 1U)) - { - r_rsip_func102(bswap_32big(0xdeaf2dabU), bswap_32big(0x32a1bcedU), bswap_32big(0x3fd3b3edU), bswap_32big(0xc01b26adU)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12U, 0U); - return RSIP_RET_KEY_FAIL; - } - else - { - if ((InData_MsgLen[0] == 0) && (InData_MsgLen[1] == 0)) - { - WR1_PROG(REG_1444H, 0x00000020U); - WR1_PROG(REG_2014H, 0x00000000U); - WR1_PROG(REG_1444H, 0x00000020U); - WR1_PROG(REG_2010H, 0x00000080U); - WR1_PROG(REG_200CH, 0x00000001U); - WAIT_STS(REG_2030H, 8U, 0U); - WR1_PROG(REG_1444H, 0x00000020U); - WR1_PROG(REG_2014H, 0x00000000U); - WR1_PROG(REG_1444H, 0x00000020U); - WR1_PROG(REG_2010H, 0x00000000U); - WR1_PROG(REG_200CH, 0x00000100U); - r_rsip_func101(bswap_32big(0xc8649dcbU), bswap_32big(0xb510208bU), bswap_32big(0xe49cdaebU), bswap_32big(0xa9f112d2U)); - } - else - { - WR1_PROG(REG_1444H, 0x00000040U); - WR1_ADDR(REG_2014H, &InData_MsgLen[0]); - WR1_PROG(REG_1444H, 0x00000040U); - WR1_ADDR(REG_2010H, &InData_MsgLen[1]); - WR1_PROG(REG_200CH, 0x00000001U); - r_rsip_func101(bswap_32big(0x1906935bU), bswap_32big(0x7dad35a9U), bswap_32big(0x2e3cfda0U), bswap_32big(0x3646e844U)); - } - return RSIP_RET_PASS; - } - } -} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p75r.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p75r.c deleted file mode 100644 index a79645ac8..000000000 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p75r.c +++ /dev/null @@ -1,177 +0,0 @@ -/* -* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "r_rsip_primitive.h" -#include "r_rsip_reg.h" -#include "r_rsip_util.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Private function prototypes - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Private global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Functions - **********************************************************************************************************************/ - -RSIP_PRV_PRIMITIVE_FUNC - -rsip_ret_t r_rsip_p75r(const uint32_t InData_KeyIndex[], const uint32_t InData_HashType[], const uint32_t InData_State[]) -{ - uint32_t iLoop; - uint32_t jLoop; - uint32_t kLoop; - uint32_t oLoop; - uint32_t oLoop1; - uint32_t OFS_ADR; - (void) iLoop; - (void) jLoop; - (void) kLoop; - (void) oLoop; - (void) oLoop1; - (void) OFS_ADR; - if (0x0U != RD1_MASK(REG_14BCH, 0x1fU)) - { - return RSIP_RET_RESOURCE_CONFLICT; - } - WR1_PROG(REG_1B00H, 0x00750001U); - WR1_PROG(REG_144CH, 0x00000000U); - WR1_PROG(REG_2000H, 0x00000001U); - WR1_PROG(REG_1444H, 0x000000c7U); - WR1_PROG(REG_1608H, 0x80010080U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_HashType[0]); - WR1_PROG(REG_1458H, 0x00000000U); - WR1_PROG(REG_1600H, 0x38000c84U); - WR1_PROG(REG_1608H, 0x00000080U); - WR1_PROG(REG_143CH, 0x00260000U); - r_rsip_func100(bswap_32big(0x2d865bb4U), bswap_32big(0x73643b86U), bswap_32big(0x5d89599aU), bswap_32big(0x2e5e2b92U)); - WR1_PROG(REG_143CH, 0x00400000U); - if (CHCK_STS(REG_143CH, 22U, 1U)) - { - r_rsip_func102(bswap_32big(0x7155a1a7U), bswap_32big(0x1ba2bb55U), bswap_32big(0x7b41333cU), bswap_32big(0x452ff8b9U)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12U, 0U); - return RSIP_RET_FAIL; - } - else - { - r_rsip_func100(bswap_32big(0xb2423b2cU), bswap_32big(0x407fffe2U), bswap_32big(0x9ffd1181U), bswap_32big(0x17e7247fU)); - WR1_PROG(REG_1600H, 0x3420a880U); - WR1_PROG(REG_1600H, 0x00000003U); - WR1_PROG(REG_1600H, 0x2000b480U); - WR1_PROG(REG_1600H, 0x00000002U); - WR1_PROG(REG_1600H, 0x00007c04U); - WR1_PROG(REG_143CH, 0x00600000U); - WR1_PROG(REG_1458H, 0x00000000U); - if (0x00000001U == RD1_MASK(REG_1440H, 0xffffffffU)) - { - WR1_PROG(REG_1600H, 0x0000b4e0U); - WR1_PROG(REG_1600H, 0x0000001aU); - WR1_PROG(REG_2004H, 0x00001040U); - r_rsip_func101(bswap_32big(0xf3544007U), bswap_32big(0xba4ad4cfU), bswap_32big(0x21b26b22U), bswap_32big(0xc1bc5da0U)); - } - else if (0x00000002U == RD1_MASK(REG_1440H, 0xffffffffU)) - { - WR1_PROG(REG_1600H, 0x0000b4e0U); - WR1_PROG(REG_1600H, 0x0000001bU); - WR1_PROG(REG_2004H, 0x00001050U); - r_rsip_func101(bswap_32big(0x1f47458eU), bswap_32big(0x42ab380eU), bswap_32big(0xdb5516d2U), bswap_32big(0x51dcdae3U)); - } - WR1_PROG(REG_1600H, 0x00003507U); - WR1_PROG(REG_2008H, 0x00000003U); - WR1_PROG(REG_1444H, 0x000000c7U); - WR1_PROG(REG_1608H, 0x800100e0U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_KeyIndex[0]); - WR1_PROG(REG_1458H, 0x00000000U); - WR1_PROG(REG_1444H, 0x000000a7U); - WR1_PROG(REG_1608H, 0x800103a0U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_PROG(REG_1420H, bswap_32big(0x00007502U)); - WR1_PROG(REG_1458H, 0x00000000U); - r_rsip_func101(bswap_32big(0xbd3267e8U), bswap_32big(0x5e5da4cfU), bswap_32big(0xd5c60fa0U), bswap_32big(0x7c0fa9f2U)); - r_rsip_func043(); - WR1_PROG(REG_1600H, 0x000034e8U); - WR1_PROG(REG_1444H, 0x000000a7U); - WR1_PROG(REG_1608H, 0x800103a0U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_PROG(REG_1420H, bswap_32big(0x00007502U)); - WR1_PROG(REG_1458H, 0x00000000U); - r_rsip_func101(bswap_32big(0xa40cfdadU), bswap_32big(0xd4bba867U), bswap_32big(0xce92d859U), bswap_32big(0xb392ebd1U)); - r_rsip_func044(); - WR1_PROG(REG_1444H, 0x000007c2U); - WR1_PROG(REG_1A2CH, 0x40000100U); - WR1_PROG(REG_1A24H, 0xf7009d07U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_KeyIndex[1]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[2]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[3]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[4]); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_KeyIndex[5]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[6]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[7]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[8]); - WR1_PROG(REG_1400H, 0x01420021U); - WAIT_STS(REG_1404H, 30U, 0U); - WR1_PROG(REG_143CH, 0x00001800U); - WR1_PROG(REG_1444H, 0x000003c2U); - WR1_PROG(REG_1A2CH, 0x40000000U); - WR1_PROG(REG_1A24H, 0x07008d05U); - WAIT_STS(REG_1444H, 31U, 1U); - WR1_ADDR(REG_1420H, &InData_KeyIndex[9]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[10]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[11]); - WR1_ADDR(REG_1420H, &InData_KeyIndex[12]); - WR1_PROG(REG_1A24H, 0x9c100005U); - WR1_PROG(REG_1400H, 0x00820011U); - WAIT_STS(REG_1404H, 30U, 0U); - WR1_PROG(REG_143CH, 0x00001800U); - r_rsip_func100(bswap_32big(0xaf1f0ab0U), bswap_32big(0x71076ce8U), bswap_32big(0x461a186aU), bswap_32big(0x1a6977dbU)); - WR1_PROG(REG_143CH, 0x00400000U); - if (CHCK_STS(REG_143CH, 22U, 1U)) - { - r_rsip_func102(bswap_32big(0x9ae15959U), bswap_32big(0x52c937efU), bswap_32big(0x176408b9U), bswap_32big(0x49c08728U)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12U, 0U); - return RSIP_RET_KEY_FAIL; - } - else - { - WR1_PROG(REG_1444H, 0x00000040U); - WR1_ADDR(REG_2014H, &InData_State[18]); - WR1_PROG(REG_1444H, 0x00000040U); - WR1_ADDR(REG_2010H, &InData_State[19]); - for (iLoop = 0; iLoop < 18; iLoop = iLoop + 1) - { - WR1_PROG(REG_1444H, 0x00000040U); - WR1_ADDR(REG_2028H, &InData_State[iLoop + 0]); - } - WR1_PROG(REG_1458H, 0x00000000U); - r_rsip_func101(bswap_32big(0x9cc277aaU), bswap_32big(0xdbf3f5aaU), bswap_32big(0xb4224ad9U), bswap_32big(0x3d89446bU)); - return RSIP_RET_PASS; - } - } -} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p75s.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p75s.c deleted file mode 100644 index 01ca9edc2..000000000 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p75s.c +++ /dev/null @@ -1,65 +0,0 @@ -/* -* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "r_rsip_primitive.h" -#include "r_rsip_reg.h" -#include "r_rsip_util.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Private function prototypes - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Private global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Functions - **********************************************************************************************************************/ - -RSIP_PRV_PRIMITIVE_FUNC - -rsip_ret_t r_rsip_p75s(uint32_t OutData_State[]) -{ - uint32_t iLoop; - uint32_t jLoop; - uint32_t kLoop; - uint32_t oLoop; - uint32_t oLoop1; - uint32_t OFS_ADR; - (void) iLoop; - (void) jLoop; - (void) kLoop; - (void) oLoop; - (void) oLoop1; - (void) OFS_ADR; - for (iLoop = 0; iLoop < 18; iLoop = iLoop + 1) - { - RD1_ADDR(REG_202CH, &OutData_State[iLoop]); - } - WR1_PROG(REG_1458H, 0x00000000U); - RD1_ADDR(REG_2014H, &OutData_State[18]); - RD1_ADDR(REG_2010H, &OutData_State[19]); - r_rsip_func102(bswap_32big(0x28daed97U), bswap_32big(0x1af21c2aU), bswap_32big(0x8392cfe7U), bswap_32big(0x895daae5U)); - WR1_PROG(REG_14BCH, 0x00000040U); - WAIT_STS(REG_142CH, 12U, 0U); - return RSIP_RET_PASS; -} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/ra_rsip_e5xx/r_rsip_private.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/ra_rsip_e5xx/r_rsip_private.c deleted file mode 100644 index 2ab6ace43..000000000 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/ra_rsip_e5xx/r_rsip_private.c +++ /dev/null @@ -1,1187 +0,0 @@ -/* -* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "r_rsip_private.h" -#include "r_rsip_wrapper.h" -#include "r_rsip_primitive.h" -#include "r_rsip_api.h" -#include "r_rsip_reg.h" -#include "r_rsip_addr.h" -#include "r_rsip_util.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ -#define MSTP_SECURITY R_MSTP->MSTPCRC_b.MSTPC31 - -/* For SHA, HMAC-SHA */ -#define RSIP_PRV_SHA_INIT_VAL1 (0x80000000U) -#define RSIP_PRV_SHA_INIT_VAL2 (0x00000000U) -#define RSIP_PRV_CMD_INIT_TO_FINAL (0U) -#define RSIP_PRV_CMD_INIT_TO_SUSPEND (1U) -#define RSIP_PRV_CMD_RESUME_TO_SUSPEND (2U) -#define RSIP_PRV_CMD_RESUME_TO_FINAL (3U) -#define RSIP_PRV_CMD_INIT_TO_COMP_FINAL (4U) -#define RSIP_PRV_CMD_RESUME_TO_COMP_FINAL (5U) -#define RSIP_PRV_CMD_SHA_256 (2U) -#define RSIP_PRV_CMD_SHA_384 (5U) -#define RSIP_PRV_CMD_SHA_512 (6U) -#define RSIP_PRV_WORD_SIZE_HMAC_MAC_BUFFER (8U) - -/* Primitive function names */ -#if RSIP_CFG_AES_128_ENABLE - #define RSIP_PRV_FUNC_KEY_GENERATE_AES_128 r_rsip_p07 - #define RSIP_PRV_FUNC_KEY_WRAP_AES_128 r_rsip_wrapper_p6f_aes128 - #define RSIP_PRV_FUNC_RFC3394_AES_128_KEY_WRAP r_rsip_wrapper_p8f_aes128 - #define RSIP_PRV_FUNC_RFC3394_AES_128_KEY_UNWRAP r_rsip_wrapper_p90_aes128 - #define RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_128 r_rsip_p2c - #if RSIP_CFG_AES_ECB_CBC_CTR_ENABLE - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_128 r_rsip_wrapper_p47i_aes128ecb_encrypt - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_128 r_rsip_wrapper_p47i_aes128ecb_decrypt - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_128 r_rsip_wrapper_p47i_aes128cbc_encrypt - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_128 r_rsip_wrapper_p47i_aes128cbc_decrypt - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_128 r_rsip_wrapper_p47i_aes128ctr_crypt - #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_128 r_rsip_p47u - #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_128 r_rsip_p47f - #else - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_128 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_128 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_128 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_128 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_128 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_128 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_128 NULL - #endif -#else - #define RSIP_PRV_FUNC_KEY_GENERATE_AES_128 NULL - #define RSIP_PRV_FUNC_KEY_WRAP_AES_128 NULL - #define RSIP_PRV_FUNC_RFC3394_AES_128_KEY_WRAP NULL - #define RSIP_PRV_FUNC_RFC3394_AES_128_KEY_UNWRAP NULL - #define RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_128 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_128 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_128 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_128 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_128 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_128 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_128 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_128 NULL -#endif -#if RSIP_CFG_AES_GCM_ENABLE - #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_128 r_rsip_wrapper_p29i_aes128gcm_encrypt - #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_128 r_rsip_p29a - #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_128 r_rsip_p29t - #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_128 r_rsip_p29u - #define RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_128 r_rsip_p29f - #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_128 r_rsip_wrapper_p32i_aes128gcm_decrypt - #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_128 r_rsip_p32a - #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_128 r_rsip_p32t - #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_128 r_rsip_p32u - #define RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_128 r_rsip_p32f -#else - #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_128 NULL - #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_128 NULL - #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_128 NULL - #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_128 NULL - #define RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_128 NULL - #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_128 NULL - #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_128 NULL - #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_128 NULL - #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_128 NULL - #define RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_128 NULL -#endif -#if RSIP_CFG_AES_CCM_ENABLE - #define RSIP_PRV_FUNC_AES_CCM_ENC_INIT_128 r_rsip_wrapper_p95i_aes128ccm_encrypt - #define RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_128 r_rsip_p95u - #define RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_128 r_rsip_wrapper_p95f_aes128ccm_encrypt - #define RSIP_PRV_FUNC_AES_CCM_DEC_INIT_128 r_rsip_wrapper_p98i_aes128ccm_decrypt - #define RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_128 r_rsip_p98u - #define RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_128 r_rsip_wrapper_p98f_aes128ccm_decrypt -#else - #define RSIP_PRV_FUNC_AES_CCM_ENC_INIT_128 NULL - #define RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_128 NULL - #define RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_128 NULL - #define RSIP_PRV_FUNC_AES_CCM_DEC_INIT_128 NULL - #define RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_128 NULL - #define RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_128 NULL -#endif -#if RSIP_CFG_AES_CMAC_ENABLE - #define RSIP_PRV_FUNC_AES_MAC_INIT_128 r_rsip_wrapper_p41i_aes128mac - #define RSIP_PRV_FUNC_AES_MAC_UPDATE_128 r_rsip_p41u - #define RSIP_PRV_FUNC_AES_MAC_GENERATE_FINAL_128 r_rsip_wrapper_p41f_aes128mac_generate - #define RSIP_PRV_FUNC_AES_MAC_VERIFY_FINAL_128 r_rsip_wrapper_p41f_aes128mac_verify -#else - #define RSIP_PRV_FUNC_AES_MAC_INIT_128 NULL - #define RSIP_PRV_FUNC_AES_MAC_UPDATE_128 NULL - #define RSIP_PRV_FUNC_AES_MAC_GENERATE_FINAL_128 NULL - #define RSIP_PRV_FUNC_AES_MAC_VERIFY_FINAL_128 NULL -#endif - -#if RSIP_CFG_AES_256_ENABLE - #define RSIP_PRV_FUNC_KEY_GENERATE_AES_256 r_rsip_p08 - #define RSIP_PRV_FUNC_KEY_WRAP_AES_256 r_rsip_wrapper_p6f_aes256 - #define RSIP_PRV_FUNC_RFC3394_AES_256_KEY_WRAP r_rsip_wrapper_p8f_aes256 - #define RSIP_PRV_FUNC_RFC3394_AES_256_KEY_UNWRAP r_rsip_wrapper_p90_aes256 - #define RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_256 r_rsip_p2e - #if RSIP_CFG_AES_ECB_CBC_CTR_ENABLE - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_256 r_rsip_wrapper_p50i_aes256ecb_encrypt - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_256 r_rsip_wrapper_p50i_aes256ecb_decrypt - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_256 r_rsip_wrapper_p50i_aes256cbc_encrypt - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_256 r_rsip_wrapper_p50i_aes256cbc_decrypt - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_256 r_rsip_wrapper_p50i_aes256ctr_crypt - #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_256 r_rsip_p50u - #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_256 r_rsip_p50f - #else - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_256 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_256 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_256 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_256 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_256 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_256 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_256 NULL - #endif -#else - #define RSIP_PRV_FUNC_KEY_GENERATE_AES_256 NULL - #define RSIP_PRV_FUNC_KEY_WRAP_AES_256 NULL - #define RSIP_PRV_FUNC_RFC3394_AES_256_KEY_WRAP NULL - #define RSIP_PRV_FUNC_RFC3394_AES_256_KEY_UNWRAP NULL - #define RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_256 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_256 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_256 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_256 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_256 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_256 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_256 NULL - #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_256 NULL -#endif -#if RSIP_CFG_AES_GCM_ENABLE - #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_256 r_rsip_wrapper_p34i_aes256gcm_encrypt - #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_256 r_rsip_p34a - #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_256 r_rsip_p34t - #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_256 r_rsip_p34u - #define RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_256 r_rsip_p34f - #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_256 r_rsip_wrapper_p36i_aes256gcm_decrypt - #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_256 r_rsip_p36a - #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_256 r_rsip_p36t - #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_256 r_rsip_p36u - #define RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_256 r_rsip_p36f -#else - #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_256 NULL - #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_256 NULL - #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_256 NULL - #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_256 NULL - #define RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_256 NULL - #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_256 NULL - #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_256 NULL - #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_256 NULL - #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_256 NULL - #define RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_256 NULL -#endif -#if RSIP_CFG_AES_CCM_ENABLE - #define RSIP_PRV_FUNC_AES_CCM_ENC_INIT_256 r_rsip_wrapper_pa1i_aes256ccm_encrypt - #define RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_256 r_rsip_pa1u - #define RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_256 r_rsip_pa1f - #define RSIP_PRV_FUNC_AES_CCM_DEC_INIT_256 r_rsip_wrapper_pa4i_aes256ccm_decrypt - #define RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_256 r_rsip_pa4u - #define RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_256 r_rsip_pa4f -#else - #define RSIP_PRV_FUNC_AES_CCM_ENC_INIT_256 NULL - #define RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_256 NULL - #define RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_256 NULL - #define RSIP_PRV_FUNC_AES_CCM_DEC_INIT_256 NULL - #define RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_256 NULL - #define RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_256 NULL -#endif -#if RSIP_CFG_AES_CMAC_ENABLE - #define RSIP_PRV_FUNC_AES_MAC_INIT_256 r_rsip_wrapper_p44i_aes256mac - #define RSIP_PRV_FUNC_AES_MAC_UPDATE_256 r_rsip_p44u - #define RSIP_PRV_FUNC_AES_MAC_GENERATE_FINAL_256 r_rsip_wrapper_p44f_aes256mac_generate - #define RSIP_PRV_FUNC_AES_MAC_VERIFY_FINAL_256 r_rsip_wrapper_p44f_aes256mac_verify -#else - #define RSIP_PRV_FUNC_AES_MAC_INIT_256 NULL - #define RSIP_PRV_FUNC_AES_MAC_UPDATE_256 NULL - #define RSIP_PRV_FUNC_AES_MAC_GENERATE_FINAL_256 NULL - #define RSIP_PRV_FUNC_AES_MAC_VERIFY_FINAL_256 NULL -#endif - -#if RSIP_CFG_XTS_AES_128_ENABLE - #define RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_128 r_rsip_p16 - #define RSIP_PRV_FUNC_KEY_WRAP_XTS_AES_128 r_rsip_wrapper_p6f_aes128xts - #if RSIP_CFG_AES_XTS_ENABLE - #define RSIP_PRV_FUNC_XTS_AES_ENC_INIT_128 r_rsip_pb3i - #define RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_128 r_rsip_pb3u - #define RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_128 r_rsip_pb3f - #define RSIP_PRV_FUNC_XTS_AES_DEC_INIT_128 r_rsip_pb6i - #define RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_128 r_rsip_pb6u - #define RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_128 r_rsip_pb6f - #else - #define RSIP_PRV_FUNC_XTS_AES_ENC_INIT_128 NULL - #define RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_128 NULL - #define RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_128 NULL - #define RSIP_PRV_FUNC_XTS_AES_DEC_INIT_128 NULL - #define RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_128 NULL - #define RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_128 NULL - #endif -#else - #define RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_128 NULL - #define RSIP_PRV_FUNC_KEY_WRAP_XTS_AES_128 NULL - - #define RSIP_PRV_FUNC_XTS_AES_ENC_INIT_128 NULL - #define RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_128 NULL - #define RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_128 NULL - #define RSIP_PRV_FUNC_XTS_AES_DEC_INIT_128 NULL - #define RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_128 NULL - #define RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_128 NULL -#endif - -#if RSIP_CFG_XTS_AES_256_ENABLE - #define RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_256 r_rsip_p17 - #define RSIP_PRV_FUNC_KEY_WRAP_XTS_AES_256 r_rsip_wrapper_p6f_aes256xts - #if RSIP_CFG_AES_XTS_ENABLE - #define RSIP_PRV_FUNC_XTS_AES_ENC_INIT_256 r_rsip_pb9i - #define RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_256 r_rsip_pb9u - #define RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_256 r_rsip_pb9f - #define RSIP_PRV_FUNC_XTS_AES_DEC_INIT_256 r_rsip_pc2i - #define RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_256 r_rsip_pc2u - #define RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_256 r_rsip_pc2f - #else - #define RSIP_PRV_FUNC_XTS_AES_ENC_INIT_256 NULL - #define RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_256 NULL - #define RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_256 NULL - #define RSIP_PRV_FUNC_XTS_AES_DEC_INIT_256 NULL - #define RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_256 NULL - #define RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_256 NULL - #endif -#else - #define RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_256 NULL - #define RSIP_PRV_FUNC_KEY_WRAP_XTS_AES_256 NULL - - #define RSIP_PRV_FUNC_XTS_AES_ENC_INIT_256 NULL - #define RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_256 NULL - #define RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_256 NULL - #define RSIP_PRV_FUNC_XTS_AES_DEC_INIT_256 NULL - #define RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_256 NULL - #define RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_256 NULL -#endif - -#if RSIP_CFG_ECC_SECP256R1_ENABLE - #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP256R1 r_rsip_wrapper_pf4_secp256r1 - #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP256R1_PUBLIC r_rsip_wrapper_p6f_secp256r1_pub - #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP256R1_PRIVATE r_rsip_wrapper_p6f_secp256r1_priv - - #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP256R1 r_rsip_wrapper_pf0_secp256r1 - #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP256R1 r_rsip_wrapper_pf1_secp256r1 -#else - #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP256R1 NULL - #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP256R1_PUBLIC NULL - #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP256R1_PRIVATE NULL - - #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP256R1 NULL - #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP256R1 NULL -#endif - -#if RSIP_CFG_ECC_SECP384R1_ENABLE - #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP384R1 r_rsip_wrapper_pf9_secp384r1 - #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP384R1_PUBLIC r_rsip_wrapper_p6f_secp384r1_pub - #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP384R1_PRIVATE r_rsip_wrapper_p6f_secp384r1_priv - - #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP384R1 r_rsip_wrapper_pf5_secp384r1 - #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP384R1 r_rsip_wrapper_pf6_secp384r1 -#else - #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP384R1 NULL - #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP384R1_PUBLIC NULL - #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP384R1_PRIVATE NULL - - #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP384R1 NULL - #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP384R1 NULL -#endif - -#if RSIP_CFG_ECC_SECP521R1_ENABLE - #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP521R1 r_rsip_wrapper_p13_secp521r1 - #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP521R1_PUBLIC r_rsip_wrapper_p6f_secp521r1_pub - #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP521R1_PRIVATE r_rsip_wrapper_p6f_secp521r1_priv - - #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP521R1 r_rsip_wrapper_p11_secp521r1 - #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP521R1 r_rsip_wrapper_p12_secp521r1 -#else - #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP521R1 NULL - #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP521R1_PUBLIC NULL - #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP521R1_PRIVATE NULL - - #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP521R1 NULL - #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP521R1 NULL -#endif - -#if RSIP_CFG_RSA_2048_ENABLE - #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_2048 r_rsip_wrapper_p2b_rsa2048 - #define RSIP_PRV_FUNC_KEY_WRAP_RSA_2048_PUBLIC r_rsip_wrapper_p6f_rsa2048_pub - #define RSIP_PRV_FUNC_KEY_WRAP_RSA_2048_PRIVATE r_rsip_wrapper_p6f_rsa2048_priv - - #define RSIP_PRV_FUNC_RSA_ENCRYPT_2048 r_rsip_p56 - #define RSIP_PRV_FUNC_RSA_DECRYPT_2048 r_rsip_p57 -#else - #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_2048 NULL - #define RSIP_PRV_FUNC_KEY_WRAP_RSA_2048_PUBLIC NULL - #define RSIP_PRV_FUNC_KEY_WRAP_RSA_2048_PRIVATE NULL - - #define RSIP_PRV_FUNC_RSA_ENCRYPT_2048 NULL - #define RSIP_PRV_FUNC_RSA_DECRYPT_2048 NULL -#endif - -#if RSIP_CFG_RSA_3072_ENABLE - #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_3072 r_rsip_wrapper_p3a_rsa3072 - #define RSIP_PRV_FUNC_KEY_WRAP_RSA_3072_PUBLIC r_rsip_wrapper_p6f_rsa3072_pub - #define RSIP_PRV_FUNC_KEY_WRAP_RSA_3072_PRIVATE r_rsip_wrapper_p6f_rsa3072_priv - - #define RSIP_PRV_FUNC_RSA_ENCRYPT_3072 r_rsip_p79 - #define RSIP_PRV_FUNC_RSA_DECRYPT_3072 r_rsip_p7a -#else - #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_3072 NULL - #define RSIP_PRV_FUNC_KEY_WRAP_RSA_3072_PUBLIC NULL - #define RSIP_PRV_FUNC_KEY_WRAP_RSA_3072_PRIVATE NULL - - #define RSIP_PRV_FUNC_RSA_ENCRYPT_3072 NULL - #define RSIP_PRV_FUNC_RSA_DECRYPT_3072 NULL -#endif - -#if RSIP_CFG_RSA_4096_ENABLE - #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_4096 r_rsip_wrapper_p3b_rsa4096 - #define RSIP_PRV_FUNC_KEY_WRAP_RSA_4096_PUBLIC r_rsip_wrapper_p6f_rsa4096_pub - #define RSIP_PRV_FUNC_KEY_WRAP_RSA_4096_PRIVATE r_rsip_wrapper_p6f_rsa4096_priv - - #define RSIP_PRV_FUNC_RSA_ENCRYPT_4096 r_rsip_p7b - #define RSIP_PRV_FUNC_RSA_DECRYPT_4096 r_rsip_p7c -#else - #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_4096 NULL - #define RSIP_PRV_FUNC_KEY_WRAP_RSA_4096_PUBLIC NULL - #define RSIP_PRV_FUNC_KEY_WRAP_RSA_4096_PRIVATE NULL - - #define RSIP_PRV_FUNC_RSA_ENCRYPT_4096 NULL - #define RSIP_PRV_FUNC_RSA_DECRYPT_4096 NULL -#endif - -#if RSIP_CFG_HMAC_SHA256_ENABLE - #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA256 r_rsip_p0b - #define RSIP_PRV_FUNC_KEY_WRAP_HMAC_SHA256 r_rsip_wrapper_p6f_hmacsha256 -#else - #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA256 NULL - #define RSIP_PRV_FUNC_KEY_WRAP_HMAC_SHA256 NULL -#endif - -#define RSIP_PRV_FUNC_RANDOM_NUMBER_GENERATE r_rsip_p20 -#define RSIP_PRV_FUNC_GHASH_COMPUTE r_rsip_p21 - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -typedef enum e_rsip_sha_cmd -{ - RSIP_SHA_CMD_INIT_TO_FINAL, - RSIP_SHA_CMD_INIT_TO_SUSPEND, - RSIP_SHA_CMD_RESUME_TO_SUSPEND, - RSIP_SHA_CMD_RESUME_TO_FINAL, - RSIP_SHA_CMD_INIT_TO_COMP_FINAL, - RSIP_SHA_CMD_RESUME_TO_COMP_FINAL, -} rsip_sha_cmd_t; - -typedef enum e_rsip_hmac_cmd -{ - RSIP_HMAC_CMD_SIGN = 0U, - RSIP_HMAC_CMD_VERIFY = 1U, -} rsip_hmac_cmd_t; - -/*********************************************************************************************************************** - * Private function prototypes - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Private global variables - **********************************************************************************************************************/ -const bool g_sha_enabled[RSIP_HASH_TYPE_NUM] = -{ - [RSIP_HASH_TYPE_SHA256] = RSIP_CFG_SHA256_ENABLE, - [RSIP_HASH_TYPE_SHA384] = RSIP_CFG_SHA384_ENABLE, - [RSIP_HASH_TYPE_SHA512] = RSIP_CFG_SHA512_ENABLE -}; - -static const uint32_t gs_cmd_hash_type[] = -{ - [RSIP_HASH_TYPE_SHA256] = RSIP_PRV_CMD_SHA_256, - [RSIP_HASH_TYPE_SHA384] = RSIP_PRV_CMD_SHA_384, - [RSIP_HASH_TYPE_SHA512] = RSIP_PRV_CMD_SHA_512, -}; - -static const uint32_t gs_hmac_hash_type[] = -{ - [RSIP_KEY_HMAC_SHA256] = BSWAP_32BIG_C(2U) -}; - -static const uint32_t gs_hmac_cmd[] = -{ - [RSIP_HMAC_CMD_SIGN] = BSWAP_32BIG_C(0U), - [RSIP_HMAC_CMD_VERIFY] = BSWAP_32BIG_C(1U), -}; - -static const uint32_t gs_cmd_sha_cmd[] = -{ - [RSIP_SHA_CMD_INIT_TO_FINAL] = RSIP_PRV_CMD_INIT_TO_FINAL, - [RSIP_SHA_CMD_INIT_TO_SUSPEND] = RSIP_PRV_CMD_INIT_TO_SUSPEND, - [RSIP_SHA_CMD_RESUME_TO_SUSPEND] = RSIP_PRV_CMD_RESUME_TO_SUSPEND, - [RSIP_SHA_CMD_RESUME_TO_FINAL] = RSIP_PRV_CMD_RESUME_TO_FINAL, - [RSIP_SHA_CMD_INIT_TO_COMP_FINAL] = RSIP_PRV_CMD_INIT_TO_COMP_FINAL, - [RSIP_SHA_CMD_RESUME_TO_COMP_FINAL] = RSIP_PRV_CMD_RESUME_TO_COMP_FINAL, -}; - -static const uint32_t gs_sha_msg_len_multi[2] = -{ - RSIP_PRV_SHA_INIT_VAL1, RSIP_PRV_SHA_INIT_VAL2 -}; - -/*********************************************************************************************************************** - * Global variables - **********************************************************************************************************************/ - -const bool g_hmac_enabled[RSIP_KEY_HMAC_NUM] = -{ - [RSIP_KEY_HMAC_SHA256] = RSIP_CFG_HMAC_SHA256_ENABLE -}; - -const rsip_func_t g_func = -{ - .p_key_generate_aes = - { - [RSIP_KEY_AES_128] = RSIP_PRV_FUNC_KEY_GENERATE_AES_128, - [RSIP_KEY_AES_256] = RSIP_PRV_FUNC_KEY_GENERATE_AES_256 - }, - .p_key_generate_xts_aes = - { - [RSIP_KEY_AES_128] = RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_128, - [RSIP_KEY_AES_256] = RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_256 - }, - .p_key_generate_hmac = - { - [RSIP_KEY_HMAC_SHA256] = RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA256 - }, - .p_key_pair_generate_ecc = - { - [RSIP_KEY_ECC_SECP256R1] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP256R1, - [RSIP_KEY_ECC_SECP384R1] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP384R1, - [RSIP_KEY_ECC_SECP521R1] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP521R1 - }, - .p_key_pair_generate_rsa = - { - [RSIP_KEY_RSA_2048] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_2048, - [RSIP_KEY_RSA_3072] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_3072, - [RSIP_KEY_RSA_4096] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_4096 - }, - - .p_encrypted_key_wrap_aes = - { - [RSIP_KEY_AES_128] = RSIP_PRV_FUNC_KEY_WRAP_AES_128, - [RSIP_KEY_AES_256] = RSIP_PRV_FUNC_KEY_WRAP_AES_256 - }, - .p_encrypted_key_wrap_xts_aes = - { - [RSIP_KEY_AES_128] = RSIP_PRV_FUNC_KEY_WRAP_XTS_AES_128, - [RSIP_KEY_AES_256] = RSIP_PRV_FUNC_KEY_WRAP_XTS_AES_256 - }, - .p_encrypted_key_wrap_ecc_pub = - { - [RSIP_KEY_ECC_SECP256R1] = RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP256R1_PUBLIC, - [RSIP_KEY_ECC_SECP384R1] = RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP384R1_PUBLIC, - [RSIP_KEY_ECC_SECP521R1] = RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP521R1_PUBLIC - }, - .p_encrypted_key_wrap_ecc_priv = - { - [RSIP_KEY_ECC_SECP256R1] = RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP256R1_PRIVATE, - [RSIP_KEY_ECC_SECP384R1] = RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP384R1_PRIVATE, - [RSIP_KEY_ECC_SECP521R1] = RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP521R1_PRIVATE - }, - .p_encrypted_key_wrap_rsa_pub = - { - [RSIP_KEY_RSA_2048] = RSIP_PRV_FUNC_KEY_WRAP_RSA_2048_PUBLIC, - [RSIP_KEY_RSA_3072] = RSIP_PRV_FUNC_KEY_WRAP_RSA_3072_PUBLIC, - [RSIP_KEY_RSA_4096] = RSIP_PRV_FUNC_KEY_WRAP_RSA_4096_PUBLIC - }, - .p_encrypted_key_wrap_rsa_priv = - { - [RSIP_KEY_RSA_2048] = RSIP_PRV_FUNC_KEY_WRAP_RSA_2048_PRIVATE, - [RSIP_KEY_RSA_3072] = RSIP_PRV_FUNC_KEY_WRAP_RSA_3072_PRIVATE, - [RSIP_KEY_RSA_4096] = RSIP_PRV_FUNC_KEY_WRAP_RSA_4096_PRIVATE - }, - .p_rfc3394_key_wrap = - { - [RSIP_KEY_AES_128] = RSIP_PRV_FUNC_RFC3394_AES_128_KEY_WRAP, - [RSIP_KEY_AES_256] = RSIP_PRV_FUNC_RFC3394_AES_256_KEY_WRAP - }, - .p_rfc3394_key_unwrap = - { - [RSIP_KEY_AES_128] = RSIP_PRV_FUNC_RFC3394_AES_128_KEY_UNWRAP, - [RSIP_KEY_AES_256] = RSIP_PRV_FUNC_RFC3394_AES_256_KEY_UNWRAP - }, - .p_rsa_public = - { - [RSIP_KEY_RSA_2048] = RSIP_PRV_FUNC_RSA_ENCRYPT_2048, - [RSIP_KEY_RSA_3072] = RSIP_PRV_FUNC_RSA_ENCRYPT_3072, - [RSIP_KEY_RSA_4096] = RSIP_PRV_FUNC_RSA_ENCRYPT_4096 - }, - .p_rsa_private = - { - [RSIP_KEY_RSA_2048] = RSIP_PRV_FUNC_RSA_DECRYPT_2048, - [RSIP_KEY_RSA_3072] = RSIP_PRV_FUNC_RSA_DECRYPT_3072, - [RSIP_KEY_RSA_4096] = RSIP_PRV_FUNC_RSA_DECRYPT_4096 - }, - .p_aes_cipher = - { - [RSIP_KEY_AES_128] = - { - .p_init_ecb_enc = RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_128, - .p_init_ecb_dec = RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_128, - .p_init_cbc_enc = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_128, - .p_init_cbc_dec = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_128, - .p_init_ctr = RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_128, - .p_update = RSIP_PRV_FUNC_AES_CIPHER_UPDATE_128, - .p_final = RSIP_PRV_FUNC_AES_CIPHER_FINAL_128, - }, - [RSIP_KEY_AES_256] = - { - .p_init_ecb_enc = RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_256, - .p_init_ecb_dec = RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_256, - .p_init_cbc_enc = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_256, - .p_init_cbc_dec = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_256, - .p_init_ctr = RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_256, - .p_update = RSIP_PRV_FUNC_AES_CIPHER_UPDATE_256, - .p_final = RSIP_PRV_FUNC_AES_CIPHER_FINAL_256, - } - }, - - .p_aes_xts_enc = - { - [RSIP_KEY_AES_128] = - { - .p_init = RSIP_PRV_FUNC_XTS_AES_ENC_INIT_128, - .p_update = RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_128, - .p_final = RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_128 - }, - [RSIP_KEY_AES_256] = - { - .p_init = RSIP_PRV_FUNC_XTS_AES_ENC_INIT_256, - .p_update = RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_256, - .p_final = RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_256 - } - }, - .p_aes_xts_dec = - { - [RSIP_KEY_AES_128] = - { - .p_init = RSIP_PRV_FUNC_XTS_AES_DEC_INIT_128, - .p_update = RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_128, - .p_final = RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_128 - }, - [RSIP_KEY_AES_256] = - { - .p_init = RSIP_PRV_FUNC_XTS_AES_DEC_INIT_256, - .p_update = RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_256, - .p_final = RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_256 - } - }, - - .p_aes_gcm_enc = - { - [RSIP_KEY_AES_128] = - { - .p_init = RSIP_PRV_FUNC_AES_GCM_ENC_INIT_128, - .p_updateAad = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_128, - .p_updateTransition = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_128, - .p_update = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_128, - .p_encryptFinal = RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_128 - }, - [RSIP_KEY_AES_256] = - { - .p_init = RSIP_PRV_FUNC_AES_GCM_ENC_INIT_256, - .p_updateAad = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_256, - .p_updateTransition = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_256, - .p_update = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_256, - .p_encryptFinal = RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_256 - } - }, - .p_aes_gcm_dec = - { - [RSIP_KEY_AES_128] = - { - .p_init = RSIP_PRV_FUNC_AES_GCM_DEC_INIT_128, - .p_updateAad = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_128, - .p_updateTransition = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_128, - .p_update = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_128, - .p_decryptFinal = RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_128 - }, - [RSIP_KEY_AES_256] = - { - .p_init = RSIP_PRV_FUNC_AES_GCM_DEC_INIT_256, - .p_updateAad = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_256, - .p_updateTransition = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_256, - .p_update = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_256, - .p_decryptFinal = RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_256 - } - }, - .p_aes_ccm_enc = - { - [RSIP_KEY_AES_128] = - { - .p_encryptInit = RSIP_PRV_FUNC_AES_CCM_ENC_INIT_128, - .p_update = RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_128, - .p_encryptFinal = RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_128 - }, - [RSIP_KEY_AES_256] = - { - .p_encryptInit = RSIP_PRV_FUNC_AES_CCM_ENC_INIT_256, - .p_update = RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_256, - .p_encryptFinal = RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_256 - } - }, - .p_aes_ccm_dec = - { - [RSIP_KEY_AES_128] = - { - .p_decryptInit = RSIP_PRV_FUNC_AES_CCM_DEC_INIT_128, - .p_update = RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_128, - .p_decryptFinal = RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_128 - }, - [RSIP_KEY_AES_256] = - { - .p_decryptInit = RSIP_PRV_FUNC_AES_CCM_DEC_INIT_256, - .p_update = RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_256, - .p_decryptFinal = RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_256 - } - }, - - .p_aes_mac = - { - [RSIP_KEY_AES_128] = - { - .p_init = RSIP_PRV_FUNC_AES_MAC_INIT_128, - .p_update = RSIP_PRV_FUNC_AES_MAC_UPDATE_128, - .p_generateFinal = RSIP_PRV_FUNC_AES_MAC_GENERATE_FINAL_128, - .p_verifyFinal = RSIP_PRV_FUNC_AES_MAC_VERIFY_FINAL_128 - }, - [RSIP_KEY_AES_256] = - { - .p_init = RSIP_PRV_FUNC_AES_MAC_INIT_256, - .p_update = RSIP_PRV_FUNC_AES_MAC_UPDATE_256, - .p_generateFinal = RSIP_PRV_FUNC_AES_MAC_GENERATE_FINAL_256, - .p_verifyFinal = RSIP_PRV_FUNC_AES_MAC_VERIFY_FINAL_256 - } - }, - .p_ecdsa_sign = - { - [RSIP_KEY_ECC_SECP256R1] = RSIP_PRV_FUNC_ECDSA_SIGN_SECP256R1, - [RSIP_KEY_ECC_SECP384R1] = RSIP_PRV_FUNC_ECDSA_SIGN_SECP384R1, - [RSIP_KEY_ECC_SECP521R1] = RSIP_PRV_FUNC_ECDSA_SIGN_SECP521R1, - }, - .p_ecdsa_verify = - { - [RSIP_KEY_ECC_SECP256R1] = RSIP_PRV_FUNC_ECDSA_VERIFY_SECP256R1, - [RSIP_KEY_ECC_SECP384R1] = RSIP_PRV_FUNC_ECDSA_VERIFY_SECP384R1, - [RSIP_KEY_ECC_SECP521R1] = RSIP_PRV_FUNC_ECDSA_VERIFY_SECP521R1, - }, - .p_encrypted_key_wrap_hmac = - { - [RSIP_KEY_HMAC_SHA256] = RSIP_PRV_FUNC_KEY_WRAP_HMAC_SHA256 - }, - .p_func_otf = - { - [RSIP_OTF_CHANNEL_0] = - { - [RSIP_KEY_AES_128] = RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_128, - [RSIP_KEY_AES_192] = NULL, - [RSIP_KEY_AES_256] = RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_256 - }, - [RSIP_OTF_CHANNEL_1] = - { - [RSIP_KEY_AES_128] = NULL, - [RSIP_KEY_AES_192] = NULL, - [RSIP_KEY_AES_256] = NULL - } - }, - .p_rng = RSIP_PRV_FUNC_RANDOM_NUMBER_GENERATE, - .p_ghash_compute = RSIP_PRV_FUNC_GHASH_COMPUTE -}; - -/*********************************************************************************************************************** - * Functions - **********************************************************************************************************************/ - -rsip_ret_t r_rsip_open (void) -{ - uint32_t LC[1] = {0}; - rsip_ret_t rsip_ret = RSIP_RET_FAIL; - - R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); - - /* Casting structure pointer is used for address. */ - MSTP_SECURITY = 0U; - R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); - - r_rsip_p00(); - - rsip_ret = r_rsip_p81(); - - if (RSIP_RET_PASS == rsip_ret) - { - WR1_PROG(REG_1424H, RSIP_PRV_CMD_REG_1424H); - WR1_PROG(REG_1428H, RSIP_PRV_CMD_REG_1428H); - rsip_ret = r_rsip_p82(); - if (RSIP_RET_RETRY == rsip_ret) - { - rsip_ret = r_rsip_p82(); - if (RSIP_RET_RETRY == rsip_ret) - { - rsip_ret = r_rsip_p82(); - } - } - } - - if (RSIP_RET_PASS == rsip_ret) - { - LC[0] = (R_PSCU->DLMMON); - rsip_ret = r_rsip_p40(LC); - } - - return rsip_ret; -} - -rsip_ret_t r_rsip_close (void) -{ - r_rsip_p00(); - - R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); - - /* Casting structure pointer is used for address. */ - MSTP_SECURITY = 1U; - R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); - - return RSIP_RET_PASS; -} - -void r_rsip_kuk_store (const uint8_t * p_key_update_key_value) -{ - memcpy(S_INST2, p_key_update_key_value, sizeof(S_INST2)); -} - -/*********************************************************************************************************************** - * Private Functions - **********************************************************************************************************************/ - -rsip_ret_t r_rsip_sha1sha2_compute_single (const uint32_t in_data_msg[], - uint32_t out_data_msg_digest[], - rsip_hash_type_t hash_type, - uint32_t message_length) -{ - uint32_t in_data_hash_type[1] = - { - bswap_32big(gs_cmd_hash_type[hash_type]) - }; - uint32_t in_data_msg_len[2] = - { - in_data_msg_len[0] = r_rsip_byte_to_bit_convert_upper(message_length), - in_data_msg_len[1] = r_rsip_byte_to_bit_convert_lower(message_length) - }; - - /* MAX_CNT: message length in word order */ - uint32_t max_cnt = r_rsip_byte_to_word_convert(message_length); - - /** Call primitive (cast to match the argument type with the primitive function) */ - return r_rsip_p31(in_data_hash_type, in_data_msg, in_data_msg_len, out_data_msg_digest, max_cnt); -} - -rsip_ret_t r_rsip_sha1sha2_init_update (rsip_hash_type_t hash_type, - const uint8_t * p_message, - uint64_t message_length, - uint32_t * internal_state) -{ - /* Call primitive (cast to match the argument type with the primitive function) */ - uint32_t in_data_hasg_type[1] = - { - bswap_32big(gs_cmd_hash_type[hash_type]) - }; - - uint32_t in_data_cmd[1] = - { - bswap_32big(gs_cmd_sha_cmd[RSIP_SHA_CMD_INIT_TO_SUSPEND]) - }; - - return r_rsip_p72(in_data_hasg_type, - in_data_cmd, - (const uint32_t *) p_message, - gs_sha_msg_len_multi, - NULL, - NULL, - internal_state, - r_rsip_byte_to_word_convert((uint32_t) message_length)); -} - -rsip_ret_t r_rsip_sha1sha2_resume_update (rsip_hash_type_t hash_type, - const uint8_t * p_message, - uint64_t message_length, - uint32_t * internal_state) -{ - uint32_t in_data_hash_type[1] = - { - bswap_32big(gs_cmd_hash_type[hash_type]) - }; - - uint32_t in_data_cmd[1] = - { - bswap_32big(gs_cmd_sha_cmd[RSIP_SHA_CMD_RESUME_TO_SUSPEND]) - }; - - return r_rsip_p72(in_data_hash_type, - in_data_cmd, - (const uint32_t *) p_message, - NULL, - internal_state, - NULL, - internal_state, - r_rsip_byte_to_word_convert((uint32_t) message_length)); -} - -rsip_ret_t r_rsip_sha1sha2_update (rsip_hash_type_t hash_type, - const uint8_t * p_message, - uint64_t message_length, - uint32_t * internal_state) -{ - return r_rsip_sha1sha2_resume_update(hash_type, p_message, message_length, internal_state); -} - -rsip_ret_t r_rsip_sha1sha2_suspend (uint32_t * internal_state) -{ - - /* Call primitive (cast to match the argument type with the primitive function) */ - return r_rsip_p73s(internal_state); -} - -rsip_ret_t r_rsip_sha1sha2_init_final (rsip_hash_type_t hash_type, - const uint8_t * p_message, - uint64_t message_length, - uint8_t * p_digest) -{ - uint32_t in_data_hash_type[1] = - { - bswap_32big(gs_cmd_hash_type[hash_type]) - }; - uint32_t msg_len[2] = - { - r_rsip_byte_to_bit_convert_upper(message_length), - r_rsip_byte_to_bit_convert_lower(message_length) - }; - - uint32_t in_data_cmd[1] = - { - bswap_32big(gs_cmd_sha_cmd[RSIP_SHA_CMD_INIT_TO_FINAL]) - }; - - return r_rsip_p72(in_data_hash_type, - in_data_cmd, - (const uint32_t *) p_message, - msg_len, - NULL, - (uint32_t *) p_digest, - NULL, - r_rsip_byte_to_word_convert((uint32_t) message_length)); -} - -rsip_ret_t r_rsip_sha1sha2_resume_final (rsip_hash_type_t hash_type, - const uint8_t * p_message, - uint64_t message_length, - uint64_t total_message_length, - uint8_t * p_digest, - uint32_t * internal_state) -{ - /* Overwrite internal state */ - internal_state[16] = r_rsip_byte_to_bit_convert_lower(total_message_length); - internal_state[17] = r_rsip_byte_to_bit_convert_upper(total_message_length); - internal_state[18] = r_rsip_byte_to_bit_convert_upper(message_length); - internal_state[19] = r_rsip_byte_to_bit_convert_lower(message_length); - - uint32_t in_data_hash_type[1] = - { - bswap_32big(gs_cmd_hash_type[hash_type]) - }; - - uint32_t in_data_cmd[1] = - { - bswap_32big(gs_cmd_sha_cmd[RSIP_SHA_CMD_RESUME_TO_FINAL]) - }; - - return r_rsip_p72(in_data_hash_type, - in_data_cmd, - (const uint32_t *) p_message, - NULL, - internal_state, - (uint32_t *) p_digest, - NULL, - r_rsip_byte_to_word_convert((uint32_t) message_length)); -} - -rsip_ret_t r_rsip_sha1sha2_final (rsip_hash_type_t hash_type, - const uint8_t * p_message, - uint64_t message_length, - uint64_t total_message_length, - uint8_t * p_digest, - uint32_t * internal_state) -{ - return r_rsip_sha1sha2_resume_final(hash_type, - p_message, - message_length, - total_message_length, - p_digest, - internal_state); -} - -rsip_ret_t r_rsip_hmac_init_update (const rsip_wrapped_key_t * p_wrapped_key, - const uint8_t * p_message, - uint64_t message_length, - uint32_t * internal_state) -{ - FSP_PARAMETER_NOT_USED(internal_state); - - /* Call primitive (cast to match the argument type with the primitive function) */ - rsip_ret_t rsip_ret = r_rsip_p75i((uint32_t *) p_wrapped_key->value, - &gs_hmac_hash_type[p_wrapped_key->subtype], - gs_sha_msg_len_multi); - if (RSIP_RET_PASS == rsip_ret) - { - rsip_ret = r_rsip_p75u((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); - } - - return rsip_ret; -} - -rsip_ret_t r_rsip_hmac_resume_update (const rsip_wrapped_key_t * p_wrapped_key, - const uint8_t * p_message, - uint64_t message_length, - uint32_t * internal_state) -{ - /* Call primitive (cast to match the argument type with the primitive function) */ - rsip_ret_t rsip_ret = r_rsip_p75r((uint32_t *) p_wrapped_key->value, - &gs_hmac_hash_type[p_wrapped_key->subtype], - internal_state); - if (RSIP_RET_PASS == rsip_ret) - { - rsip_ret = r_rsip_p75u((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); - } - - return rsip_ret; -} - -rsip_ret_t r_rsip_hmac_update (const rsip_wrapped_key_t * p_wrapped_key, - const uint8_t * p_message, - uint64_t message_length, - uint32_t * internal_state) -{ - FSP_PARAMETER_NOT_USED(p_wrapped_key); - FSP_PARAMETER_NOT_USED(internal_state); - - /* Call primitive (cast to match the argument type with the primitive function) */ - return r_rsip_p75u((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); -} - -rsip_ret_t r_rsip_hmac_suspend (uint32_t * internal_state) -{ - - /* Call primitive (cast to match the argument type with the primitive function) */ - return r_rsip_p75s(internal_state); -} - -rsip_ret_t r_rsip_hmac_init_final (const rsip_wrapped_key_t * p_wrapped_key, - const uint8_t * p_message, - uint64_t message_length, - uint8_t * p_mac) -{ - uint32_t msg_len[2] = - { - r_rsip_byte_to_bit_convert_upper(message_length), - r_rsip_byte_to_bit_convert_lower(message_length) - }; - - /* Call primitive (cast to match the argument type with the primitive function) */ - rsip_ret_t rsip_ret = r_rsip_p75i((uint32_t *) p_wrapped_key->value, - &gs_hmac_hash_type[p_wrapped_key->subtype], - msg_len); - if (RSIP_RET_PASS == rsip_ret) - { - rsip_ret = - r_rsip_p75f(&gs_hmac_cmd[RSIP_HMAC_CMD_SIGN], - (const uint32_t *) p_message, - NULL, - NULL, - r_rsip_byte_to_word_convert((uint32_t) message_length), - (uint32_t *) p_mac); - } - - return rsip_ret; -} - -rsip_ret_t r_rsip_hmac_resume_final (const rsip_wrapped_key_t * p_wrapped_key, - const uint8_t * p_message, - uint64_t message_length, - uint64_t total_message_length, - uint8_t * p_mac, - uint32_t * internal_state) -{ - /* Overwrite internal state */ - internal_state[16] = r_rsip_byte_to_bit_convert_lower(total_message_length); - internal_state[17] = r_rsip_byte_to_bit_convert_upper(total_message_length); - internal_state[18] = r_rsip_byte_to_bit_convert_upper(message_length); - internal_state[19] = r_rsip_byte_to_bit_convert_lower(message_length); - - /* Call primitive (cast to match the argument type with the primitive function) */ - rsip_ret_t rsip_ret = r_rsip_p75r((uint32_t *) p_wrapped_key->value, - &gs_hmac_hash_type[p_wrapped_key->subtype], - internal_state); - if (RSIP_RET_PASS == rsip_ret) - { - rsip_ret = - r_rsip_p75f(&gs_hmac_cmd[RSIP_HMAC_CMD_SIGN], - (const uint32_t *) p_message, - NULL, - NULL, - r_rsip_byte_to_word_convert((uint32_t) message_length), - (uint32_t *) p_mac); - } - - return rsip_ret; -} - -rsip_ret_t r_rsip_hmac_final (const rsip_wrapped_key_t * p_wrapped_key, - const uint8_t * p_message, - uint64_t message_length, - uint64_t total_message_length, - uint8_t * p_mac, - uint32_t * internal_state) -{ - /* Call primitive (cast to match the argument type with the primitive function) */ - rsip_ret_t rsip_ret = r_rsip_p75s(internal_state); - if (RSIP_RET_PASS == rsip_ret) - { - rsip_ret = r_rsip_hmac_resume_final(p_wrapped_key, - p_message, - message_length, - total_message_length, - p_mac, - internal_state); - } - - return rsip_ret; -} - -rsip_ret_t r_rsip_hmac_init_verify (const rsip_wrapped_key_t * p_wrapped_key, - const uint8_t * p_message, - uint64_t message_length, - const uint8_t * p_mac, - uint32_t mac_length) -{ - uint32_t msg_len[2] = - { - r_rsip_byte_to_bit_convert_upper(message_length), - r_rsip_byte_to_bit_convert_lower(message_length) - }; - uint32_t InData_MAC[RSIP_PRV_WORD_SIZE_HMAC_MAC_BUFFER] = - { - 0 - }; - memcpy(InData_MAC, p_mac, mac_length); - uint32_t mac_len[1] = - { - bswap_32big(mac_length) - }; - - /* Call primitive (cast to match the argument type with the primitive function) */ - rsip_ret_t rsip_ret = r_rsip_p75i((uint32_t *) p_wrapped_key->value, - &gs_hmac_hash_type[p_wrapped_key->subtype], - msg_len); - if (RSIP_RET_PASS == rsip_ret) - { - rsip_ret = - r_rsip_p75f(&gs_hmac_cmd[RSIP_HMAC_CMD_VERIFY], - (const uint32_t *) p_message, - InData_MAC, - mac_len, - r_rsip_byte_to_word_convert((uint32_t) message_length), - (uint32_t *) NULL); - } - - return rsip_ret; -} - -rsip_ret_t r_rsip_hmac_resume_verify (const rsip_wrapped_key_t * p_wrapped_key, - const uint8_t * p_message, - uint64_t message_length, - uint64_t total_message_length, - const uint8_t * p_mac, - uint32_t mac_length, - uint32_t * internal_state) -{ - /* Overwrite internal state */ - internal_state[16] = r_rsip_byte_to_bit_convert_lower(total_message_length); - internal_state[17] = r_rsip_byte_to_bit_convert_upper(total_message_length); - internal_state[18] = r_rsip_byte_to_bit_convert_upper(message_length); - internal_state[19] = r_rsip_byte_to_bit_convert_lower(message_length); - - uint32_t InData_MAC[RSIP_PRV_WORD_SIZE_HMAC_MAC_BUFFER] = - { - 0 - }; - memcpy(InData_MAC, p_mac, mac_length); - uint32_t mac_len[1] = - { - bswap_32big(mac_length) - }; - - /* Call primitive (cast to match the argument type with the primitive function) */ - rsip_ret_t rsip_ret = r_rsip_p75r((uint32_t *) p_wrapped_key->value, - &gs_hmac_hash_type[p_wrapped_key->subtype], - internal_state); - if (RSIP_RET_PASS == rsip_ret) - { - rsip_ret = - r_rsip_p75f(&gs_hmac_cmd[RSIP_HMAC_CMD_VERIFY], - (const uint32_t *) p_message, - InData_MAC, - mac_len, - r_rsip_byte_to_word_convert((uint32_t) message_length), - (uint32_t *) NULL); - } - - return rsip_ret; -} - -rsip_ret_t r_rsip_hmac_verify (const rsip_wrapped_key_t * p_wrapped_key, - const uint8_t * p_message, - uint64_t message_length, - uint64_t total_message_length, - const uint8_t * p_mac, - uint32_t mac_length, - uint32_t * internal_state) -{ - /* Call primitive (cast to match the argument type with the primitive function) */ - rsip_ret_t rsip_ret = r_rsip_p75s(internal_state); - if (RSIP_RET_PASS == rsip_ret) - { - rsip_ret = r_rsip_hmac_resume_verify(p_wrapped_key, - p_message, - message_length, - total_message_length, - p_mac, - mac_length, - internal_state); - } - - return rsip_ret; -} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/inc/instances/ra/r_rsip.h b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/inc/instances/r_rsip.h similarity index 99% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/inc/instances/ra/r_rsip.h rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/inc/instances/r_rsip.h index 61de586f2..2a3198f92 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/inc/instances/ra/r_rsip.h +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/inc/instances/r_rsip.h @@ -209,9 +209,6 @@ fsp_err_t R_RSIP_AES_MAC_SignFinish(rsip_ctrl_t * const p_ctrl, uint8_t * const fsp_err_t R_RSIP_AES_MAC_VerifyFinish(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_mac, uint32_t const mac_length); -fsp_err_t R_RSIP_AES_MAC_VerifyFinish(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_mac, - uint32_t const mac_length); - /* r_rsip_ecc.c */ fsp_err_t R_RSIP_ECDSA_Sign(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_private_key, diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/ra_rsip_e5xx/r_rsip_addr.h b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_addr.h similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/ra_rsip_e5xx/r_rsip_addr.h rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_addr.h diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_data.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_data.c similarity index 99% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_data.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_data.c index 979c2bd01..26a8615cf 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_data.c +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_data.c @@ -16,7 +16,7 @@ uint32_t S_RAM[RSIP_PRV_WORD_SIZE_S_RAM]; uint32_t S_HEAP[RSIP_PRV_WORD_SIZE_S_HEAP]; -uint32_t S_INST2[RSIP_PRV_WORD_SIZE_S_INST2]; +uint32_t const * S_INST2; uint32_t INST_DATA_SIZE; uint32_t KEY_INDEX_SIZE; uint32_t WRAPPED_KEY_SIZE; diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_data.h b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_data.h similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_data.h rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_data.h diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func016.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func016.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func016.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func016.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func017.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func017.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func017.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func017.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func027.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func027.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func027.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func027.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func028.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func028.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func028.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func028.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func030.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func030.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func030.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func030.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func031.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func031.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func031.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func031.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func040.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func040.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func040.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func040.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func043.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func043.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func043.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func043.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func044.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func044.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func044.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func044.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func048.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func048.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func048.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func048.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func049.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func049.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func049.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func049.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func052.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func052.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func052.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func052.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func053.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func053.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func053.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func053.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func054.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func054.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func054.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func054.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func055.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func055.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func055.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func055.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func057.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func057.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func057.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func057.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func059.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func059.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func059.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func059.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func061.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func061.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func061.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func061.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func062.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func062.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func062.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func062.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func063.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func063.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func063.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func063.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func065.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func065.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func065.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func065.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func068.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func068.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func068.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func068.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func070.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func070.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func070.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func070.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func071.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func071.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func071.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func071.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func073.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func073.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func073.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func073.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func074.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func074.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func074.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func074.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func075.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func075.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func075.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func075.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func076.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func076.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func076.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func076.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func077.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func077.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func077.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func077.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func081.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func081.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func081.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func081.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func086.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func086.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func086.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func086.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func087.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func087.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func087.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func087.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func088.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func088.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func088.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func088.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func089.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func089.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func089.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func089.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func091.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func091.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func091.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func091.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func092.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func092.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func092.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func092.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func100.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func100.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func100.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func100.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func101.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func101.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func101.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func101.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func102.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func102.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func102.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func102.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func103.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func103.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func103.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func103.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func202.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func202.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func202.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func202.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func214.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func214.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func214.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func214.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func215.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func215.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func215.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func215.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func216.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func216.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func216.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func216.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func302.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func302.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func302.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func302.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func303.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func303.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func303.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func303.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func304.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func304.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func304.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func304.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func305.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func305.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func305.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func305.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func310.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func310.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func310.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func310.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func311.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func311.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func311.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func311.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func312.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func312.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func312.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func312.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func313.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func313.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func313.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func313.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func314.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func314.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func314.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func314.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func315.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func315.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func315.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func315.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func316.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func316.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func316.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func316.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func317.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func317.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func317.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func317.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func318.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func318.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func318.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func318.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func319.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func319.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func319.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func319.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func320.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func320.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func320.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func320.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func321.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func321.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func321.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func321.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func322.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func322.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func322.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func322.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func323.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func323.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func323.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func323.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func324.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func324.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_func324.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func324.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p00.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p00.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p00.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p00.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p07.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p07.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p07.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p07.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p08.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p08.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p08.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p08.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p0b.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0b.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p0b.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0b.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p11.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p11.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p11.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p11.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p12.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p12.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p12.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p12.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p13.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p13.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p13.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p13.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p16.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p16.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p16.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p16.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p17.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p17.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p17.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p17.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p20.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p20.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p20.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p20.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p21.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p21.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p21.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p21.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p29a.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29a.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p29a.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29a.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p29f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p29f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p29i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p29i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p29t.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29t.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p29t.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29t.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p29u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p29u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p2b.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2b.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p2b.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2b.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p2c.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2c.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p2c.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2c.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p2e.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2e.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p2e.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2e.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p31.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p31.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p31.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p31.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p32a.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32a.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p32a.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32a.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p32f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p32f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p32i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p32i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p32t.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32t.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p32t.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32t.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p32u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p32u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p34a.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34a.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p34a.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34a.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p34f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p34f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p34i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p34i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p34t.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34t.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p34t.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34t.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p34u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p34u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p36a.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36a.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p36a.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36a.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p36f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p36f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p36i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p36i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p36t.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36t.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p36t.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36t.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p36u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p36u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p3a.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3a.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p3a.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3a.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p3b.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3b.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p3b.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3b.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3c.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3c.c new file mode 100644 index 000000000..8fc56e0b1 --- /dev/null +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3c.c @@ -0,0 +1,136 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p3c (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x003c0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + r_rsip_func100(bswap_32big(0xe1345bbdU), bswap_32big(0x627b08baU), bswap_32big(0xcf8038c7U), bswap_32big(0xce9bfb46U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000003cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6283d9e7U), bswap_32big(0xec9b9279U), bswap_32big(0x6350c8f1U), bswap_32big(0x31fdfe94U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000028U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000003cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3005eeb3U), bswap_32big(0xc5c575ceU), bswap_32big(0x0b9279efU), bswap_32big(0xa4611eb6U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x7b221004U), bswap_32big(0x0b91fa37U), bswap_32big(0xdc1bb9aaU), bswap_32big(0xd4288633U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + r_rsip_func100(bswap_32big(0x9a12633dU), bswap_32big(0x6f747070U), bswap_32big(0x93c0588dU), bswap_32big(0x500994d2U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x800c0000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x5d2c1c96U), bswap_32big(0xc928bd30U), bswap_32big(0xbb81e703U), bswap_32big(0xb775075aU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xdce7ad52U), bswap_32big(0xe7b8b79eU), bswap_32big(0x56ee6050U), bswap_32big(0xc074bea4U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x374481caU), bswap_32big(0xe0af9993U), bswap_32big(0x0ce2afb6U), bswap_32big(0x92697422U)); + + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d47U); + WR1_PROG(REG_1608H, 0x810c0000U); + WR1_PROG(REG_1400H, 0x00890031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[9]); + + r_rsip_func100(bswap_32big(0xbef06c3dU), bswap_32big(0xf4715feeU), bswap_32big(0xa2989941U), bswap_32big(0x4a2626caU)); + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00000000U), bswap_32big(0x00000000U), bswap_32big(0x00000000U), bswap_32big(0x00000003U)); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[13]); + + r_rsip_func102(bswap_32big(0x5c0f31dfU), bswap_32big(0xeffe05efU), bswap_32big(0x663bb762U), bswap_32big(0x3c8465e4U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3d.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3d.c new file mode 100644 index 000000000..faa457c70 --- /dev/null +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3d.c @@ -0,0 +1,152 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p3d (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x003d0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + r_rsip_func100(bswap_32big(0x014b865eU), bswap_32big(0x565ed7b4U), bswap_32big(0xb85bc1d7U), bswap_32big(0xde5060b7U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000003dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc3468222U), bswap_32big(0xdc984914U), bswap_32big(0x5e69ab7fU), bswap_32big(0x64f942feU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000029U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000003dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5c8c5894U), bswap_32big(0x8eddff6fU), bswap_32big(0x5c9a9cdeU), bswap_32big(0x81c99ba5U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xdfb6d899U), bswap_32big(0x22212bb7U), bswap_32big(0x1e6ea182U), bswap_32big(0x9e6d4806U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + r_rsip_func100(bswap_32big(0x03546844U), bswap_32big(0x4b5b18afU), bswap_32big(0x89a2cc18U), bswap_32big(0x305f9b4bU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80100000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x8252322aU), bswap_32big(0x865df057U), bswap_32big(0x73fb1997U), bswap_32big(0xbe0d8ab6U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x57e025bcU), bswap_32big(0x397e249cU), bswap_32big(0xe3b3e99dU), bswap_32big(0x7dbcb81eU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x635fd04dU), bswap_32big(0x25599c6dU), bswap_32big(0xd5c20ed4U), bswap_32big(0x4ecd20acU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x66bb6182U), bswap_32big(0xdd0fcd5eU), bswap_32big(0xf2a4a3a2U), bswap_32big(0xe5b66e10U)); + + WR1_PROG(REG_1A2CH, 0x40000300U); + WR1_PROG(REG_1A24H, 0xe7009d47U); + WR1_PROG(REG_1608H, 0x81100000U); + WR1_PROG(REG_1400H, 0x00890031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[9]); + + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x47aa9897U), bswap_32big(0xcd6c617dU), bswap_32big(0xd95a00dfU), bswap_32big(0xec8a6e0bU)); + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00000000U), bswap_32big(0x00000000U), bswap_32big(0x00000000U), bswap_32big(0x00000004U)); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[13]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[17]); + + r_rsip_func102(bswap_32big(0x79b0da9cU), bswap_32big(0x94d7157dU), bswap_32big(0x72d198f9U), bswap_32big(0xf51ca384U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p40.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p40.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p40.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p40.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p41f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p41f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p41i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p41i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p41u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p41u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p44f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p44f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p44i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p44i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p44u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p44u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p47f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p47f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p47i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p47i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p47u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p47u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p50f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p50f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p50i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p50i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p50u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p50u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p56.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p56.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p56.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p56.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p57.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p57.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p57.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p57.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p6f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p6f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p6f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p6f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73f.c new file mode 100644 index 000000000..0c302c81b --- /dev/null +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73f.c @@ -0,0 +1,193 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +rsip_ret_t r_rsip_p73f(const uint32_t InData_Msg[], uint32_t MAX_CNT, uint32_t OutData_MsgDigest[]) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WAIT_STS(REG_2030H, 0U, 1U); + WR1_PROG(REG_1444H, 0x00020064U); + for (iLoop = 0; iLoop < (MAX_CNT & 0xfffffff0U); iLoop = iLoop + 16) + { + WAIT_STS(REG_1444H, 31U, 1U); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 0]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 1]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 2]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 3]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 4]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 5]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 6]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 7]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 8]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 9]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 10]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 11]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 12]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 13]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 14]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 15]); + } + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31U, 1U); + for (iLoop = (MAX_CNT & 0xfffffff0U); iLoop < MAX_CNT; iLoop = iLoop + 1) + { + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 0]); + } + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_2030H, 8U, 0U); + WR1_PROG(REG_143CH, 0x00001600U); + WAIT_STS(REG_2030H, 4U, 1U); + r_rsip_func100(bswap_32big(0x613b57a1U), bswap_32big(0x38d28e4fU), bswap_32big(0x4b09cd77U), bswap_32big(0x8bfdc1d0U)); + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x1000b400U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x1000b400U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + if (0x00000000U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + r_rsip_func100(bswap_32big(0xc75eca98U), bswap_32big(0x1508e263U), bswap_32big(0x8f4ec345U), bswap_32big(0x120a26f4U)); + WR1_PROG(REG_1408H, 0x00004016U); + WAIT_STS(REG_1408H, 30U, 1U); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[0]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[1]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[2]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[3]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[4]); + r_rsip_func102(bswap_32big(0x69817aadU), bswap_32big(0x2fb02a70U), bswap_32big(0x66054079U), bswap_32big(0xef752c92U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12U, 0U); + } + else if (0x00000001U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + r_rsip_func100(bswap_32big(0x847fb73eU), bswap_32big(0xb646991bU), bswap_32big(0x14997e83U), bswap_32big(0x4395df73U)); + WR1_PROG(REG_1408H, 0x0000401eU); + WAIT_STS(REG_1408H, 30U, 1U); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[0]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[1]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[2]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[3]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[4]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[5]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[6]); + r_rsip_func102(bswap_32big(0xf1554fc6U), bswap_32big(0x172cf756U), bswap_32big(0xc99402ccU), bswap_32big(0x1f826902U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12U, 0U); + } + else if (0x00000002U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + r_rsip_func100(bswap_32big(0xcffad43aU), bswap_32big(0x6a8ffd50U), bswap_32big(0xf5113be8U), bswap_32big(0x74dcf42aU)); + WR1_PROG(REG_1408H, 0x00004022U); + WAIT_STS(REG_1408H, 30U, 1U); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[0]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[1]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[2]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[3]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[4]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[5]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[6]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[7]); + r_rsip_func102(bswap_32big(0x7333795fU), bswap_32big(0x1b3df1e3U), bswap_32big(0xfbad3912U), bswap_32big(0x873b50f8U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12U, 0U); + } + else if (0x00000005U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + r_rsip_func100(bswap_32big(0xeccf52aaU), bswap_32big(0xcfe6d35aU), bswap_32big(0xab729384U), bswap_32big(0x91f8352fU)); + WR1_PROG(REG_1408H, 0x00004032U); + WAIT_STS(REG_1408H, 30U, 1U); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[0]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[1]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[2]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[3]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[4]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[5]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[6]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[7]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[8]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[9]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[10]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[11]); + r_rsip_func102(bswap_32big(0x02b2d092U), bswap_32big(0xa0f3ae9eU), bswap_32big(0xbf85d244U), bswap_32big(0xd2000f8cU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12U, 0U); + } + else if (0x00000006U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + r_rsip_func100(bswap_32big(0xa5cbf736U), bswap_32big(0x790cf329U), bswap_32big(0xb2d617c5U), bswap_32big(0xfdd5d816U)); + WR1_PROG(REG_1408H, 0x00004042U); + WAIT_STS(REG_1408H, 30U, 1U); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[0]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[1]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[2]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[3]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[4]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[5]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[6]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[7]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[8]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[9]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[10]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[11]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[12]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[13]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[14]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[15]); + r_rsip_func102(bswap_32big(0x857b2da2U), bswap_32big(0x1c05c7d2U), bswap_32big(0xc96239a2U), bswap_32big(0xc51438b2U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12U, 0U); + } + return RSIP_RET_PASS; +} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73i.c new file mode 100644 index 000000000..a0878a720 --- /dev/null +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73i.c @@ -0,0 +1,123 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +rsip_ret_t r_rsip_p73i(const uint32_t InData_HashType[], const uint32_t InData_MsgLen[]) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + if (0x0U != RD1_MASK(REG_14BCH, 0x1fU)) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + WR1_PROG(REG_1B00H, 0x00730001U); + WR1_PROG(REG_144CH, 0x00000000U); + r_rsip_func100(bswap_32big(0x10536e75U), bswap_32big(0x331466a8U), bswap_32big(0x7eefde91U), bswap_32big(0xe28e803fU)); + WR1_PROG(REG_2000H, 0x00000001U); + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_ADDR(REG_1420H, &InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1600H, 0x2000b400U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + if (0x00000000U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00000000U); + r_rsip_func101(bswap_32big(0xd96bfc9eU), bswap_32big(0x487c02b2U), bswap_32big(0xfc75625fU), bswap_32big(0x6053b6c3U)); + } + else if (0x00000001U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00000040U); + r_rsip_func101(bswap_32big(0xd82c8e37U), bswap_32big(0x57edf2f6U), bswap_32big(0x44321c10U), bswap_32big(0x9549981fU)); + } + else if (0x00000002U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00000050U); + r_rsip_func101(bswap_32big(0x3aa12cabU), bswap_32big(0x7b307f76U), bswap_32big(0x8d4e154cU), bswap_32big(0x61e17003U)); + } + else if (0x00000003U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00000080U); + r_rsip_func101(bswap_32big(0xf197febfU), bswap_32big(0x0acf8d75U), bswap_32big(0x65ffcf05U), bswap_32big(0xca09fd44U)); + } + else if (0x00000004U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00000090U); + r_rsip_func101(bswap_32big(0xf34ef58fU), bswap_32big(0x907ea3cfU), bswap_32big(0xa313eeecU), bswap_32big(0x2445166eU)); + } + else if (0x00000005U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x000000a0U); + r_rsip_func101(bswap_32big(0x98d7fc97U), bswap_32big(0xa91c8662U), bswap_32big(0xb76231c5U), bswap_32big(0xff218a00U)); + } + else if (0x00000006U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x000000b0U); + r_rsip_func101(bswap_32big(0xd91630c6U), bswap_32big(0x254dddb8U), bswap_32big(0x87ef4539U), bswap_32big(0x831051b2U)); + } + if ((InData_MsgLen[0] == 0) && (InData_MsgLen[1] == 0)) + { + WR1_PROG(REG_200CH, 0x00000100U); + r_rsip_func101(bswap_32big(0xd7e4dd58U), bswap_32big(0x6deb38e7U), bswap_32big(0x38547147U), bswap_32big(0xcea045caU)); + } + else + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_ADDR(REG_2014H, &InData_MsgLen[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_ADDR(REG_2010H, &InData_MsgLen[1]); + r_rsip_func101(bswap_32big(0xe64467f0U), bswap_32big(0x1ec38968U), bswap_32big(0xace088cfU), bswap_32big(0xa6ae0529U)); + } + return RSIP_RET_PASS; +} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73r.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73r.c new file mode 100644 index 000000000..ed468005c --- /dev/null +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73r.c @@ -0,0 +1,121 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +rsip_ret_t r_rsip_p73r(const uint32_t InData_HashType[], const uint32_t InData_State[]) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + if (0x0U != RD1_MASK(REG_14BCH, 0x1fU)) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + WR1_PROG(REG_1B00H, 0x00730001U); + WR1_PROG(REG_144CH, 0x00000000U); + r_rsip_func100(bswap_32big(0x10536e75U), bswap_32big(0x331466a8U), bswap_32big(0x7eefde91U), bswap_32big(0xe28e803fU)); + WR1_PROG(REG_2000H, 0x00000001U); + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_ADDR(REG_1420H, &InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1600H, 0x2000b400U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + if (0x00000000U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00001000U); + r_rsip_func101(bswap_32big(0x2e718b88U), bswap_32big(0xdb4b75c2U), bswap_32big(0xb3a8b0acU), bswap_32big(0xf3e09da0U)); + } + else if (0x00000001U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00001040U); + r_rsip_func101(bswap_32big(0xe379ab73U), bswap_32big(0x404c8b84U), bswap_32big(0xe6897dedU), bswap_32big(0xf7ab42c5U)); + } + else if (0x00000002U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00001050U); + r_rsip_func101(bswap_32big(0x2316ff0eU), bswap_32big(0xc5fde60dU), bswap_32big(0x863172d9U), bswap_32big(0xf9cc187eU)); + } + else if (0x00000003U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00001080U); + r_rsip_func101(bswap_32big(0x11f65666U), bswap_32big(0x499bd4a0U), bswap_32big(0xd344b1f9U), bswap_32big(0xf2a866a5U)); + } + else if (0x00000004U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00001090U); + r_rsip_func101(bswap_32big(0xac484580U), bswap_32big(0xdefd0225U), bswap_32big(0x8430b2c6U), bswap_32big(0xfbf4d22fU)); + } + else if (0x00000005U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x000010a0U); + r_rsip_func101(bswap_32big(0xf2ac21deU), bswap_32big(0xa6584e00U), bswap_32big(0xd0dcec5cU), bswap_32big(0xac5f5b57U)); + } + else if (0x00000006U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x000010b0U); + r_rsip_func101(bswap_32big(0x20311c6cU), bswap_32big(0xfaa52075U), bswap_32big(0x4cabf318U), bswap_32big(0xecbb34e5U)); + } + WR1_PROG(REG_1444H, 0x00000040U); + WR1_ADDR(REG_2014H, &InData_State[18]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_ADDR(REG_2010H, &InData_State[19]); + for (iLoop = 0; iLoop < 18; iLoop = iLoop + 1) + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_ADDR(REG_2028H, &InData_State[iLoop + 0]); + } + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xafa17b39U), bswap_32big(0x8c4f9b53U), bswap_32big(0x049691c3U), bswap_32big(0x4a78e698U)); + return RSIP_RET_PASS; +} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p73s.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73s.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p73s.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73s.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p75u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73u.c similarity index 94% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p75u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73u.c index d328460bd..bd91cd133 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p75u.c +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73u.c @@ -37,7 +37,7 @@ RSIP_PRV_PRIMITIVE_FUNC -rsip_ret_t r_rsip_p75u(const uint32_t InData_Msg[], uint32_t MAX_CNT) +rsip_ret_t r_rsip_p73u(const uint32_t InData_Msg[], uint32_t MAX_CNT) { uint32_t iLoop; uint32_t jLoop; @@ -77,6 +77,6 @@ rsip_ret_t r_rsip_p75u(const uint32_t InData_Msg[], uint32_t MAX_CNT) WR1_PROG(REG_1444H, 0x00000000U); WAIT_STS(REG_2030H, 8U, 0U); WR1_PROG(REG_143CH, 0x00001600U); - r_rsip_func101(bswap_32big(0x255d49a9U), bswap_32big(0xbbbf843fU), bswap_32big(0xd81296bfU), bswap_32big(0x827440e9U)); + r_rsip_func101(bswap_32big(0x80c0ee56U), bswap_32big(0xc2fa20dcU), bswap_32big(0x8bb2b171U), bswap_32big(0xecb4fa8dU)); return RSIP_RET_PASS; } diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75f.c new file mode 100644 index 000000000..b4df116f8 --- /dev/null +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75f.c @@ -0,0 +1,313 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p75f (const uint32_t InData_Cmd[], + const uint32_t InData_Msg[], + const uint32_t InData_MAC[], + const uint32_t InData_length[], + uint32_t MAX_CNT, + uint32_t OutData_MAC[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + WAIT_STS(REG_2030H, 0, 1); + + WR1_PROG(REG_1444H, 0x00020064U); + + for (iLoop = 0U; iLoop < (MAX_CNT & 0xfffffff0U); ) + { + WAIT_STS(REG_1444H, 31, 1); + WR16_ADDR(REG_1420H, &InData_Msg[iLoop]); + iLoop = iLoop + 16U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = (MAX_CNT & 0xfffffff0U); iLoop < MAX_CNT; iLoop++) + { + WR1_PROG(REG_1420H, InData_Msg[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_2030H, 8, 0); + WR1_PROG(REG_143CH, 0x00001600U); + + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xc44e575fU), bswap_32big(0xb39d73feU), bswap_32big(0x3129abb9U), bswap_32big(0xefe727d9U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0xc47987c4U), bswap_32big(0x77e43a73U), bswap_32big(0xfb0db761U), bswap_32big(0x37e78ca7U)); + + WR1_PROG(REG_1600H, 0x00007c04U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func100(bswap_32big(0x4387084cU), bswap_32big(0x039b42dcU), bswap_32big(0x91e98272U), bswap_32big(0x64ff31d4U)); + WR1_PROG(REG_1408H, 0x0000401eU); + WAIT_STS(REG_1408H, 30, 1); + RD7_ADDR(REG_1420H, &OutData_MAC[0]); + + r_rsip_func102(bswap_32big(0xfaa1e43fU), bswap_32big(0x7c268b13U), bswap_32big(0x2e363126U), bswap_32big(0x3bfa9bd2U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + r_rsip_func100(bswap_32big(0x22dc5cd1U), bswap_32big(0x3346fef7U), bswap_32big(0x3a0fbc41U), bswap_32big(0x7009ed0fU)); + WR1_PROG(REG_1408H, 0x00004022U); + WAIT_STS(REG_1408H, 30, 1); + RD8_ADDR(REG_1420H, &OutData_MAC[0]); + + r_rsip_func102(bswap_32big(0x0960b3c3U), bswap_32big(0xacd09037U), bswap_32big(0x3c995204U), bswap_32big(0xb984ea7aU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000005U) + { + r_rsip_func100(bswap_32big(0x90ed49e7U), bswap_32big(0x098bd813U), bswap_32big(0xa6d6f145U), bswap_32big(0x235ebf98U)); + WR1_PROG(REG_1408H, 0x00004032U); + WAIT_STS(REG_1408H, 30, 1); + RD12_ADDR(REG_1420H, &OutData_MAC[0]); + + r_rsip_func102(bswap_32big(0x352f38c8U), bswap_32big(0xee4e235fU), bswap_32big(0xd2dbdcb1U), bswap_32big(0xc84455c8U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) + { + r_rsip_func100(bswap_32big(0x4a510798U), bswap_32big(0xfc029359U), bswap_32big(0x290d7027U), bswap_32big(0xf32f787aU)); + WR1_PROG(REG_1408H, 0x00004042U); + WAIT_STS(REG_1408H, 30, 1); + RD16_ADDR(REG_1420H, &OutData_MAC[0]); + + r_rsip_func102(bswap_32big(0xc15fdafaU), bswap_32big(0x628a9928U), bswap_32big(0x29f19258U), bswap_32big(0x4e26e728U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + + return RSIP_RET_PASS; + } + else + { + r_rsip_func100(bswap_32big(0x935beb89U), bswap_32big(0x093d4062U), bswap_32big(0xf3193d07U), bswap_32big(0x377e81c4U)); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010020U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_length[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c04U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1600H, 0x0000b440U); + WR1_PROG(REG_1600H, 0x0000001cU); + + r_rsip_func101(bswap_32big(0x39248654U), bswap_32big(0x2b2ead69U), bswap_32big(0x51bf0030U), bswap_32big(0x0af1a03cU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1600H, 0x0000b440U); + WR1_PROG(REG_1600H, 0x00000020U); + + r_rsip_func101(bswap_32big(0x015e4f5eU), bswap_32big(0x93ac7d35U), bswap_32big(0x505b42c2U), bswap_32big(0xe78a74abU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000005U) + { + WR1_PROG(REG_1600H, 0x0000b440U); + WR1_PROG(REG_1600H, 0x00000030U); + + r_rsip_func101(bswap_32big(0x0f420d9cU), bswap_32big(0x67696037U), bswap_32big(0xa556cea6U), bswap_32big(0xf938003dU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) + { + WR1_PROG(REG_1600H, 0x0000b440U); + WR1_PROG(REG_1600H, 0x00000040U); + + r_rsip_func101(bswap_32big(0x445b7f11U), bswap_32big(0x7dfda686U), bswap_32big(0xd59d7715U), bswap_32big(0x0c6b8496U)); + } + + WR1_PROG(REG_1600H, 0x3420a820U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x34202841U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x288cc714U), bswap_32big(0xb2576d89U), bswap_32big(0x51b3dbd5U), bswap_32big(0x74dda411U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xa591d5d6U), bswap_32big(0x0db6ba0aU), bswap_32big(0xc58cd089U), bswap_32big(0xe475a057U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x8baea9e4U), bswap_32big(0x7d429282U), bswap_32big(0x074aeb80U), bswap_32big(0xbe27aba0U)); + + WR1_PROG(REG_1600H, 0x000008c6U); + + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1600H, 0x0000a440U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1600H, 0x00046842U); + WR1_PROG(REG_1600H, 0x00026c42U); + + WR1_PROG(REG_1608H, 0x81010040U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; ) + { + r_rsip_func100(bswap_32big(0xda719471U), bswap_32big(0x7b6e23daU), bswap_32big(0x84d9cf3bU), bswap_32big(0x9e8619abU)); + + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1600H, 0x00000863U); + + WR1_PROG(REG_1600H, 0x380088c0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x2000d060U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1600H, 0x2000d060U); + + WR1_PROG(REG_1600H, 0x00007c03U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1608H, 0x80830007U); + WR1_PROG(REG_1400H, 0x0345000dU); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000002c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR3_ADDR(REG_1420H, &InData_MAC[iLoop]); + WR1_PROG(REG_1444H, 0x000000a1U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func101(bswap_32big(0x29f7ab0aU), bswap_32big(0xad41feb8U), bswap_32big(0x65713280U), bswap_32big(0xfd39715eU)); + } + else + { + WR1_PROG(REG_1608H, 0x80840007U); + WR1_PROG(REG_1400H, 0x03450011U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MAC[iLoop]); + + r_rsip_func101(bswap_32big(0x771de06aU), bswap_32big(0x427323c3U), bswap_32big(0x5f6f85f0U), bswap_32big(0x57bd697cU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000800U); + for (jLoop = 0U; jLoop < 16U; jLoop++) + { + WR1_PROG(REG_1600H, 0x3c0028a1U); + WR1_PROG(REG_1600H, 0x12003c07U); + WR1_PROG(REG_1600H, 0x00002ce0U); + WR1_PROG(REG_1600H, 0x00002ca0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1824H, 0x9c000005U); + WR1_PROG(REG_1600H, 0x000008e7U); + WR1_PROG(REG_1608H, 0x81840007U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a4c0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0x298e2ab0U), bswap_32big(0x9a2d1b27U), bswap_32big(0xec3c2ceaU), bswap_32big(0xd524cbf6U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1600H, 0x000008c2U); + + WR1_PROG(REG_1600H, 0x00007c06U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xaf6f5e67U), bswap_32big(0x773f2216U), bswap_32big(0x094b1d18U), bswap_32big(0x8548d3f2U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x252b31a1U), bswap_32big(0x91cc3fbfU), bswap_32big(0x7447417eU), bswap_32big(0x435514d4U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0x5b1ad2ecU), bswap_32big(0x7e0c8e9cU), bswap_32big(0x85adf7f4U), bswap_32big(0xe831d6deU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } +} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75i.c new file mode 100644 index 000000000..3ca0830ba --- /dev/null +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75i.c @@ -0,0 +1,250 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p75i (const uint32_t InData_KeyIndex[], const uint32_t InData_HashType[], const uint32_t InData_MsgLen[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00750001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x3d9c6768U), bswap_32big(0xeed11688U), bswap_32big(0xb81e4821U), bswap_32big(0x13e0f0b1U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xe043b90dU), bswap_32big(0xa2048907U), bswap_32big(0xfdb526a5U), bswap_32big(0x557b06cdU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x40809cadU), bswap_32big(0x8fb81e4fU), bswap_32big(0xf3fa3df5U), bswap_32big(0x51b4fc88U)); + WR1_PROG(REG_1600H, 0x3420a880U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1600H, 0x2000b480U); + WR1_PROG(REG_1600H, 0x00000006U); + + WR1_PROG(REG_1600H, 0x00007c04U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x0000001aU); + + WR1_PROG(REG_2004H, 0x00000040U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0xbf9e5542U), bswap_32big(0x7d579b0dU), bswap_32big(0xc6aed1dfU), bswap_32big(0x589be1dbU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x0000001bU); + + WR1_PROG(REG_2004H, 0x00000050U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0x4623c1f6U), bswap_32big(0x6d8f740fU), bswap_32big(0x2c3b2f07U), bswap_32big(0x22da1d59U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000005U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000028U); + + WR1_PROG(REG_2004H, 0x000000a0U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000000cU); + + r_rsip_func101(bswap_32big(0x66326bfbU), bswap_32big(0x0f5f9954U), bswap_32big(0xdb3700c1U), bswap_32big(0xd5ac02daU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000029U); + + WR1_PROG(REG_2004H, 0x000000b0U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000010U); + + r_rsip_func101(bswap_32big(0xd8fc71b8U), bswap_32big(0x5c272856U), bswap_32big(0x9e4ae5d9U), bswap_32big(0x5e5c3df8U)); + } + + WR1_PROG(REG_2008H, 0x00000003U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007501U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3526cf5cU), bswap_32big(0x5cd9659cU), bswap_32big(0xa7a6c9e7U), bswap_32big(0xd54caea0U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x000034e5U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007501U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xcf3bb4bdU), bswap_32big(0x5f4b1c1eU), bswap_32big(0x2015072bU), bswap_32big(0xadd68673U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x000008e7U); + + for (iLoop = 0U; iLoop < KEY_INDEX_SIZE - 5; ) + { + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1400H, 0x01420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a4e0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0x8f90b383U), bswap_32big(0x5eb9a5a9U), bswap_32big(0x9d5d27cfU), bswap_32big(0x58810b56U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x380008e3U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x3df2ca0dU), bswap_32big(0x9f76b229U), bswap_32big(0x321840daU), bswap_32big(0x929577afU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xb02910c8U), bswap_32big(0x3c497f61U), bswap_32big(0x29dfba2dU), bswap_32big(0x69d830ccU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + if ((InData_MsgLen[0] == 0) && (InData_MsgLen[1] == 0)) + { + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000080U); + + WR1_PROG(REG_200CH, 0x00000001U); + + WAIT_STS(REG_2030H, 8, 0); + + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000000U); + + WR1_PROG(REG_200CH, 0x00000100U); + + r_rsip_func101(bswap_32big(0x35007ef2U), bswap_32big(0xeae17f70U), bswap_32big(0x5941fe37U), bswap_32big(0x02799ba3U)); + } + else + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, InData_MsgLen[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, InData_MsgLen[1]); + + WR1_PROG(REG_200CH, 0x00000001U); + + r_rsip_func101(bswap_32big(0xee738e30U), bswap_32big(0x088a20d8U), bswap_32big(0x78bb2b09U), bswap_32big(0x7a2eb843U)); + } + + return RSIP_RET_PASS; + } + } +} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75r.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75r.c new file mode 100644 index 000000000..68162ee00 --- /dev/null +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75r.c @@ -0,0 +1,233 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p75r (const uint32_t InData_KeyIndex[], const uint32_t InData_HashType[], const uint32_t InData_State[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00750001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x3d9c6768U), bswap_32big(0xeed11688U), bswap_32big(0xb81e4821U), bswap_32big(0x13e0f0b1U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xe043b90dU), bswap_32big(0xa2048907U), bswap_32big(0xfdb526a5U), bswap_32big(0x557b06cdU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x40809cadU), bswap_32big(0x8fb81e4fU), bswap_32big(0xf3fa3df5U), bswap_32big(0x51b4fc88U)); + WR1_PROG(REG_1600H, 0x3420a880U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1600H, 0x2000b480U); + WR1_PROG(REG_1600H, 0x00000006U); + + WR1_PROG(REG_1600H, 0x00007c04U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x0000001aU); + + WR1_PROG(REG_2004H, 0x00001040U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0xe8603735U), bswap_32big(0x475b57ccU), bswap_32big(0xba493135U), bswap_32big(0x4dff4c43U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x0000001bU); + + WR1_PROG(REG_2004H, 0x00001050U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0x491797b0U), bswap_32big(0x16ebb4fbU), bswap_32big(0xe3618953U), bswap_32big(0x43e5f95eU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000005U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000028U); + + WR1_PROG(REG_2004H, 0x000010a0U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000000cU); + + r_rsip_func101(bswap_32big(0x5bd7bc8aU), bswap_32big(0x2697558cU), bswap_32big(0x2ae29db1U), bswap_32big(0x63c89718U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000029U); + + WR1_PROG(REG_2004H, 0x000010b0U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000010U); + + r_rsip_func101(bswap_32big(0xd1fb1242U), bswap_32big(0xa76bb5f3U), bswap_32big(0x49db6405U), bswap_32big(0xef8046b3U)); + } + + WR1_PROG(REG_2008H, 0x00000003U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007502U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x881a15b7U), bswap_32big(0x04c57eddU), bswap_32big(0x9ca1bc1aU), bswap_32big(0xb7f036dcU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x000034e5U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007502U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xff774896U), bswap_32big(0x5f32303dU), bswap_32big(0x6ccc1b06U), bswap_32big(0x6c1e1a70U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x000008e7U); + + for (iLoop = 0U; iLoop < KEY_INDEX_SIZE - 5; ) + { + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1400H, 0x01420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a4e0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0xa39a5550U), bswap_32big(0xec37e9e5U), bswap_32big(0x17b1b88dU), bswap_32big(0x421e19a0U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x380008e3U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x42c7d303U), bswap_32big(0x269e96a5U), bswap_32big(0xfd7d36f3U), bswap_32big(0x71865308U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd87d9593U), bswap_32big(0x990073e2U), bswap_32big(0x77b02d52U), bswap_32big(0xaefa97d8U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, InData_State[18]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, InData_State[19]); + + for (iLoop = 0U; iLoop < 18U; iLoop++) + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2028H, InData_State[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf843ec47U), bswap_32big(0x58697af4U), bswap_32big(0x62f1f47cU), bswap_32big(0xb7f44d3cU)); + + return RSIP_RET_PASS; + } + } +} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75s.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75s.c new file mode 100644 index 000000000..2ba595eed --- /dev/null +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75s.c @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p75s (uint32_t OutData_State[]) +{ + uint32_t iLoop = 0U; + + for (iLoop = 0U; iLoop < 18U; iLoop++) + { + RD1_ADDR(REG_202CH, &OutData_State[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + RD1_ADDR(REG_2014H, &OutData_State[18]); + RD1_ADDR(REG_2010H, &OutData_State[19]); + + r_rsip_func102(bswap_32big(0x28daed97U), bswap_32big(0x1af21c2aU), bswap_32big(0x8392cfe7U), bswap_32big(0x895daae5U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75u.c new file mode 100644 index 000000000..c0f4fd66b --- /dev/null +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75u.c @@ -0,0 +1,42 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p75u (const uint32_t InData_Msg[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WAIT_STS(REG_2030H, 0, 1); + + WR1_PROG(REG_1444H, 0x00020064U); + + for (iLoop = 0U; iLoop < (MAX_CNT & 0xfffffff0U); ) + { + WAIT_STS(REG_1444H, 31, 1); + WR16_ADDR(REG_1420H, &InData_Msg[iLoop]); + iLoop = iLoop + 16U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_2030H, 8, 0); + WR1_PROG(REG_143CH, 0x00001600U); + + r_rsip_func101(bswap_32big(0x255d49a9U), bswap_32big(0xbbbf843fU), bswap_32big(0xd81296bfU), bswap_32big(0x827440e9U)); + + return RSIP_RET_PASS; +} diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p79.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p79.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p79.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p79.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p7a.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7a.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p7a.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7a.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p7b.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7b.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p7b.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7b.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p7c.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7c.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p7c.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7c.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p81.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p81.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p81.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p81.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p82.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p82.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p82.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p82.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p8f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p8f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p8f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p8f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p90.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p90.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p90.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p90.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p95f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p95f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p95i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p95i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p95u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p95u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p98f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98f.c similarity index 99% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p98f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98f.c index 3d31417f6..c2a9cd0b6 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p98f.c +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98f.c @@ -172,7 +172,7 @@ rsip_ret_t r_rsip_p98f (const uint32_t InData_Text[], const uint32_t InData_MAC[ WR1_PROG(REG_14BCH, 0x00000040U); WAIT_STS(REG_142CH, 12, 0); - return RSIP_RET_FAIL; + return RSIP_RET_AUTH_FAIL; } else { diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p98i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p98i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p98u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_p98u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pa1f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pa1f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pa1i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pa1i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pa1u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pa1u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pa4f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4f.c similarity index 99% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pa4f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4f.c index 43b9503e2..d726d6e7f 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pa4f.c +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4f.c @@ -189,7 +189,7 @@ rsip_ret_t r_rsip_pa4f (const uint32_t InData_Text[], WR1_PROG(REG_14BCH, 0x00000040U); WAIT_STS(REG_142CH, 12, 0); - return RSIP_RET_FAIL; + return RSIP_RET_AUTH_FAIL; } else { diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pa4i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pa4i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pa4u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pa4u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb3f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb3f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb3i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb3i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb3u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb3u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb6f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb6f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb6i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb6i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb6u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb6u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb9f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb9f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb9i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb9i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb9u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pb9u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pc2f.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2f.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pc2f.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2f.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pc2i.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2i.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pc2i.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2i.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pc2u.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2u.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pc2u.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2u.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pf0.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf0.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pf0.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf0.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pf1.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf1.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pf1.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf1.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pf4.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf4.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pf4.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf4.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pf5.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf5.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pf5.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf5.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pf6.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf6.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pf6.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf6.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pf9.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf9.c similarity index 100% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_pf9.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf9.c diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_primitive.h b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_primitive.h similarity index 96% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_primitive.h rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_primitive.h index a2ffbcef4..d7da83a37 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/primitive/ra_rsip_e51a/r_rsip_primitive.h +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_primitive.h @@ -14,16 +14,15 @@ **********************************************************************************************************************/ #define RSIP_PRV_WORD_SIZE_S_RAM (32U) -#define RSIP_PRV_WORD_SIZE_S_INST2 (16U) #define RSIP_PRV_WORD_SIZE_S_HEAP (940U) /********************************************************************************************************************** * Exported global variables **********************************************************************************************************************/ -extern uint32_t S_RAM[RSIP_PRV_WORD_SIZE_S_RAM]; -extern uint32_t S_INST2[RSIP_PRV_WORD_SIZE_S_INST2]; -extern uint32_t S_HEAP[RSIP_PRV_WORD_SIZE_S_HEAP]; +extern uint32_t S_RAM[RSIP_PRV_WORD_SIZE_S_RAM]; +extern uint32_t S_HEAP[RSIP_PRV_WORD_SIZE_S_HEAP]; +extern uint32_t const * S_INST2; extern uint32_t const DomainParam_NIST_P192[]; extern uint32_t const DomainParam_NIST_P224[]; @@ -151,7 +150,11 @@ rsip_ret_t r_rsip_p50f(void); rsip_ret_t r_rsip_p50i(const uint32_t InData_KeyType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); rsip_ret_t r_rsip_p20(uint32_t OutData_Text[]); rsip_ret_t r_rsip_p6f(const uint32_t InData_LC[], const uint32_t InData_Cmd[], const uint32_t InData_IV[], const uint32_t InData_InstData[], uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_p73i(const uint32_t InData_HashType[], const uint32_t InData_MsgLen[]); +rsip_ret_t r_rsip_p73r(const uint32_t InData_HashType[], const uint32_t InData_State[]); +rsip_ret_t r_rsip_p73u(const uint32_t InData_Msg[], uint32_t MAX_CNT); rsip_ret_t r_rsip_p73s(uint32_t OutData_State[]); +rsip_ret_t r_rsip_p73f(const uint32_t InData_Msg[], uint32_t MAX_CNT, uint32_t OutData_MsgDigest[]); rsip_ret_t r_rsip_p81(void); rsip_ret_t r_rsip_p82(void); rsip_ret_t r_rsip_p95f(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t OutData_MAC[]); @@ -177,12 +180,13 @@ rsip_ret_t r_rsip_pc2f(const uint32_t InData_TextBitLen[], const uint32_t InData rsip_ret_t r_rsip_pc2i(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); void r_rsip_pc2u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); rsip_ret_t r_rsip_p21(const uint32_t InData_HV[], const uint32_t InData_IV[], const uint32_t InData_Text[], uint32_t OutData_DataT[], uint32_t MAX_CNT); -rsip_ret_t r_rsip_p72(const uint32_t InData_HashType[], const uint32_t InData_Cmd[], const uint32_t InData_Msg[], const uint32_t InData_MsgLen[], const uint32_t InData_State[], uint32_t OutData_MsgDigest[], uint32_t OutData_State[], uint32_t MAX_CNT); rsip_ret_t r_rsip_p07(uint32_t OutData_KeyIndex[]); rsip_ret_t r_rsip_p08(uint32_t OutData_KeyIndex[]); rsip_ret_t r_rsip_p16(uint32_t OutData_KeyIndex[]); rsip_ret_t r_rsip_p17(uint32_t OutData_KeyIndex[]); rsip_ret_t r_rsip_p0b(uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_p3c(uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_p3d(uint32_t OutData_KeyIndex[]); rsip_ret_t r_rsip_p56(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); rsip_ret_t r_rsip_p57(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); rsip_ret_t r_rsip_p79(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_private_internal.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_private_internal.c new file mode 100644 index 000000000..aff1ff012 --- /dev/null +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_private_internal.c @@ -0,0 +1,504 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_private.h" +#include "r_rsip_primitive.h" +#include "r_rsip_util.h" +#include "r_rsip_reg.h" +#include "r_rsip_wrapper.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define MSTP_SECURITY R_MSTP->MSTPCRC_b.MSTPC31 + +/* For SHA, HMAC-SHA */ +#define RSIP_PRV_SHA_INIT_VAL1 (0x80000000U) +#define RSIP_PRV_SHA_INIT_VAL2 (0x00000000U) +#define RSIP_PRV_WORD_SIZE_HMAC_MAC_BUFFER (16U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +typedef enum e_rsip_hmac_cmd +{ + RSIP_HMAC_CMD_SIGN = 0U, + RSIP_HMAC_CMD_VERIFY = 1U, +} rsip_hmac_cmd_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +static const uint32_t gs_sha_hash_type[] = +{ + [RSIP_HASH_TYPE_SHA1] = BSWAP_32BIG_C(0U), + [RSIP_HASH_TYPE_SHA224] = BSWAP_32BIG_C(1U), + [RSIP_HASH_TYPE_SHA256] = BSWAP_32BIG_C(2U), + [RSIP_HASH_TYPE_SHA384] = BSWAP_32BIG_C(5U), + [RSIP_HASH_TYPE_SHA512] = BSWAP_32BIG_C(6U), + [RSIP_HASH_TYPE_SHA512_224] = BSWAP_32BIG_C(3U), + [RSIP_HASH_TYPE_SHA512_256] = BSWAP_32BIG_C(4U), +}; + +static const uint32_t gs_hmac_hash_type[] = +{ + [RSIP_KEY_HMAC_SHA256] = BSWAP_32BIG_C(2U), + [RSIP_KEY_HMAC_SHA384] = BSWAP_32BIG_C(5U), + [RSIP_KEY_HMAC_SHA512] = BSWAP_32BIG_C(6U), +}; + +static const uint32_t gs_hmac_cmd[] = +{ + [RSIP_HMAC_CMD_SIGN] = BSWAP_32BIG_C(0U), + [RSIP_HMAC_CMD_VERIFY] = BSWAP_32BIG_C(1U), +}; + +static const uint32_t gs_sha_msg_len_multi[2] = +{ + RSIP_PRV_SHA_INIT_VAL1, RSIP_PRV_SHA_INIT_VAL2 +}; + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_open (void) +{ + uint32_t LC[1] = {0}; + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Casting structure pointer is used for address. */ + MSTP_SECURITY = 0U; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); + + r_rsip_p00(); + + rsip_ret = r_rsip_p81(); + + if (RSIP_RET_PASS == rsip_ret) + { + WR1_PROG(REG_1424H, RSIP_PRV_CMD_REG_1424H); + WR1_PROG(REG_1428H, RSIP_PRV_CMD_REG_1428H); + rsip_ret = r_rsip_p82(); + if (RSIP_RET_RETRY == rsip_ret) + { + rsip_ret = r_rsip_p82(); + if (RSIP_RET_RETRY == rsip_ret) + { + rsip_ret = r_rsip_p82(); + } + } + } + + if (RSIP_RET_PASS == rsip_ret) + { + LC[0] = (R_PSCU->DLMMON); + rsip_ret = r_rsip_p40(LC); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_close (void) +{ + r_rsip_p00(); + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Casting structure pointer is used for address. */ + MSTP_SECURITY = 1U; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); + + return RSIP_RET_PASS; +} + +void r_rsip_kuk_set (const uint8_t * p_key_update_key_value) +{ + S_INST2 = (uint32_t *) p_key_update_key_value; +} + +rsip_ret_t r_rsip_sha1sha2_init_update (rsip_hash_type_t hash_type, + const uint8_t * p_message, + uint64_t message_length, + uint32_t * internal_state) +{ + FSP_PARAMETER_NOT_USED(internal_state); + + /* Call primitive (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = r_rsip_p73i(&gs_sha_hash_type[hash_type], gs_sha_msg_len_multi); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = r_rsip_p73u((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_sha1sha2_resume_update (rsip_hash_type_t hash_type, + const uint8_t * p_message, + uint64_t message_length, + uint32_t * internal_state) +{ + /* Call primitive (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = r_rsip_p73r(&gs_sha_hash_type[hash_type], internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = r_rsip_p73u((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_sha1sha2_update (rsip_hash_type_t hash_type, + const uint8_t * p_message, + uint64_t message_length, + uint32_t * internal_state) +{ + FSP_PARAMETER_NOT_USED(hash_type); + FSP_PARAMETER_NOT_USED(internal_state); + + /* Call primitive (cast to match the argument type with the primitive function) */ + return r_rsip_p73u((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); +} + +rsip_ret_t r_rsip_sha1sha2_suspend (uint32_t * internal_state) +{ + + /* Call primitive (cast to match the argument type with the primitive function) */ + return r_rsip_p73s(internal_state); +} + +rsip_ret_t r_rsip_sha1sha2_init_final (rsip_hash_type_t hash_type, + const uint8_t * p_message, + uint64_t message_length, + uint8_t * p_digest) +{ + uint32_t msg_len[2] = + { + r_rsip_byte_to_bit_convert_upper(message_length), + r_rsip_byte_to_bit_convert_lower(message_length) + }; + + /* Call primitive (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = r_rsip_p73i(&gs_sha_hash_type[hash_type], msg_len); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + r_rsip_p73f((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length), + (uint32_t *) p_digest); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_sha1sha2_resume_final (rsip_hash_type_t hash_type, + const uint8_t * p_message, + uint64_t message_length, + uint64_t total_message_length, + uint8_t * p_digest, + uint32_t * internal_state) +{ + /* Overwrite internal state */ + internal_state[16] = r_rsip_byte_to_bit_convert_lower(total_message_length); + internal_state[17] = r_rsip_byte_to_bit_convert_upper(total_message_length); + internal_state[18] = r_rsip_byte_to_bit_convert_upper(message_length); + internal_state[19] = r_rsip_byte_to_bit_convert_lower(message_length); + + /* Call primitive (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = r_rsip_p73r(&gs_sha_hash_type[hash_type], internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + r_rsip_p73f((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length), + (uint32_t *) p_digest); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_sha1sha2_final (rsip_hash_type_t hash_type, + const uint8_t * p_message, + uint64_t message_length, + uint64_t total_message_length, + uint8_t * p_digest, + uint32_t * internal_state) +{ + /* Call primitive (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = r_rsip_p73s(internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = r_rsip_sha1sha2_resume_final(hash_type, + p_message, + message_length, + total_message_length, + p_digest, + internal_state); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_init_update (const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_message, + uint64_t message_length, + uint32_t * internal_state) +{ + FSP_PARAMETER_NOT_USED(internal_state); + + /* Call primitive (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = r_rsip_wrapper_p75i(p_wrapped_key, + &gs_hmac_hash_type[p_wrapped_key->subtype], + gs_sha_msg_len_multi); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = r_rsip_p75u((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_resume_update (const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_message, + uint64_t message_length, + uint32_t * internal_state) +{ + /* Call primitive (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = r_rsip_wrapper_p75r(p_wrapped_key, + &gs_hmac_hash_type[p_wrapped_key->subtype], + internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = r_rsip_p75u((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_update (const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_message, + uint64_t message_length, + uint32_t * internal_state) +{ + FSP_PARAMETER_NOT_USED(p_wrapped_key); + FSP_PARAMETER_NOT_USED(internal_state); + + /* Call primitive (cast to match the argument type with the primitive function) */ + return r_rsip_p75u((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); +} + +rsip_ret_t r_rsip_hmac_suspend (uint32_t * internal_state) +{ + + /* Call primitive (cast to match the argument type with the primitive function) */ + return r_rsip_p75s(internal_state); +} + +rsip_ret_t r_rsip_hmac_init_final (const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_message, + uint64_t message_length, + uint8_t * p_mac) +{ + uint32_t msg_len[2] = + { + r_rsip_byte_to_bit_convert_upper(message_length), + r_rsip_byte_to_bit_convert_lower(message_length) + }; + + /* Call primitive (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = r_rsip_wrapper_p75i(p_wrapped_key, + &gs_hmac_hash_type[p_wrapped_key->subtype], + msg_len); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + r_rsip_p75f(&gs_hmac_cmd[RSIP_HMAC_CMD_SIGN], + (const uint32_t *) p_message, + NULL, + NULL, + r_rsip_byte_to_word_convert((uint32_t) message_length), + (uint32_t *) p_mac); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_resume_final (const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_message, + uint64_t message_length, + uint64_t total_message_length, + uint8_t * p_mac, + uint32_t * internal_state) +{ + /* Overwrite internal state */ + internal_state[16] = r_rsip_byte_to_bit_convert_lower(total_message_length); + internal_state[17] = r_rsip_byte_to_bit_convert_upper(total_message_length); + internal_state[18] = r_rsip_byte_to_bit_convert_upper(message_length); + internal_state[19] = r_rsip_byte_to_bit_convert_lower(message_length); + + /* Call primitive (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = r_rsip_wrapper_p75r(p_wrapped_key, + &gs_hmac_hash_type[p_wrapped_key->subtype], + internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + r_rsip_p75f(&gs_hmac_cmd[RSIP_HMAC_CMD_SIGN], + (const uint32_t *) p_message, + NULL, + NULL, + r_rsip_byte_to_word_convert((uint32_t) message_length), + (uint32_t *) p_mac); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_final (const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_message, + uint64_t message_length, + uint64_t total_message_length, + uint8_t * p_mac, + uint32_t * internal_state) +{ + /* Call primitive (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = r_rsip_p75s(internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = r_rsip_hmac_resume_final(p_wrapped_key, + p_message, + message_length, + total_message_length, + p_mac, + internal_state); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_init_verify (const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_message, + uint64_t message_length, + const uint8_t * p_mac, + uint32_t mac_length) +{ + uint32_t msg_len[2] = + { + r_rsip_byte_to_bit_convert_upper(message_length), + r_rsip_byte_to_bit_convert_lower(message_length) + }; + uint32_t InData_MAC[RSIP_PRV_WORD_SIZE_HMAC_MAC_BUFFER] = + { + 0 + }; + memcpy(InData_MAC, p_mac, mac_length); + uint32_t mac_len[1] = + { + bswap_32big(mac_length) + }; + + /* Call primitive (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = r_rsip_wrapper_p75i(p_wrapped_key, + &gs_hmac_hash_type[p_wrapped_key->subtype], + msg_len); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + r_rsip_p75f(&gs_hmac_cmd[RSIP_HMAC_CMD_VERIFY], + (const uint32_t *) p_message, + InData_MAC, + mac_len, + r_rsip_byte_to_word_convert((uint32_t) message_length), + (uint32_t *) NULL); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_resume_verify (const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_message, + uint64_t message_length, + uint64_t total_message_length, + const uint8_t * p_mac, + uint32_t mac_length, + uint32_t * internal_state) +{ + /* Overwrite internal state */ + internal_state[16] = r_rsip_byte_to_bit_convert_lower(total_message_length); + internal_state[17] = r_rsip_byte_to_bit_convert_upper(total_message_length); + internal_state[18] = r_rsip_byte_to_bit_convert_upper(message_length); + internal_state[19] = r_rsip_byte_to_bit_convert_lower(message_length); + + uint32_t InData_MAC[RSIP_PRV_WORD_SIZE_HMAC_MAC_BUFFER] = + { + 0 + }; + memcpy(InData_MAC, p_mac, mac_length); + uint32_t mac_len[1] = + { + bswap_32big(mac_length) + }; + + /* Call primitive (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = r_rsip_wrapper_p75r(p_wrapped_key, + &gs_hmac_hash_type[p_wrapped_key->subtype], + internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + r_rsip_p75f(&gs_hmac_cmd[RSIP_HMAC_CMD_VERIFY], + (const uint32_t *) p_message, + InData_MAC, + mac_len, + r_rsip_byte_to_word_convert((uint32_t) message_length), + (uint32_t *) NULL); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_verify (const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_message, + uint64_t message_length, + uint64_t total_message_length, + const uint8_t * p_mac, + uint32_t mac_length, + uint32_t * internal_state) +{ + /* Call primitive (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = r_rsip_p75s(internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = r_rsip_hmac_resume_verify(p_wrapped_key, + p_message, + message_length, + total_message_length, + p_mac, + mac_length, + internal_state); + } + + return rsip_ret; +} + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/ra_rsip_e5xx/r_rsip_wrapper.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_wrapper.c similarity index 84% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/ra_rsip_e5xx/r_rsip_wrapper.c rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_wrapper.c index 4a42596bc..a51dec926 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/ra_rsip_e5xx/r_rsip_wrapper.c +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_wrapper.c @@ -53,6 +53,10 @@ #define RSIP_PRV_WORD_SIZE_RFC3394_WRAPPED_KEY_AES_128 (6U) #define RSIP_PRV_WORD_SIZE_RFC3394_WRAPPED_KEY_AES_256 (10U) +/* For ECC */ +#define RSIP_PRV_WORD_SIZE_SIGNATURE_ECC_521 (40U) +#define RSIP_PRV_BYTE_SIZE_SIGNATURE_PAD_ECC_521 (14U) + /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ @@ -134,6 +138,7 @@ typedef enum e_rsip_rfc3394_key_wrap_type static rsip_ret_t select_rfc3394_key_wrap_mode (const rsip_key_type_t key_type, uint32_t WrappedKeyType[]); +static rsip_ret_t select_hmac_key_index_size (const rsip_wrapped_key_t * p_wrapped_key); /*********************************************************************************************************************** * Private global variables @@ -211,9 +216,26 @@ rsip_ret_t r_rsip_wrapper_p11_secp521r1 (const uint32_t InData_KeyIndex[], const uint32_t InData_MsgDgst[], uint32_t OutData_Signature[]) { + rsip_ret_t rsip_ret; const uint32_t * InData_DomainParam = DomainParam_NIST_P521; + uint32_t Signature[RSIP_PRV_WORD_SIZE_SIGNATURE_ECC_521] = {0}; + const uint32_t signature_r_pad_byte = RSIP_PRV_BYTE_SIZE_SIGNATURE_PAD_ECC_521; + const uint32_t signature_s_pad_byte = RSIP_PRV_BYTE_SIZE_SIGNATURE_PAD_ECC_521 + + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM + + RSIP_PRV_BYTE_SIZE_SIGNATURE_PAD_ECC_521; + + rsip_ret = r_rsip_p11(InData_KeyIndex, InData_MsgDgst, InData_DomainParam, Signature); + if (RSIP_RET_PASS == rsip_ret) + { + memcpy((uint8_t*)OutData_Signature, + (uint8_t*)Signature + signature_r_pad_byte, + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM); + memcpy((uint8_t*)OutData_Signature + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM, + (uint8_t*)Signature + signature_s_pad_byte, + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM); + } - return r_rsip_p11(InData_KeyIndex, InData_MsgDgst, InData_DomainParam, OutData_Signature); + return rsip_ret; } rsip_ret_t r_rsip_wrapper_p12_secp521r1 (const uint32_t InData_KeyIndex[], @@ -221,8 +243,17 @@ rsip_ret_t r_rsip_wrapper_p12_secp521r1 (const uint32_t InData_KeyIndex[], const uint32_t InData_Signature[]) { const uint32_t * InData_DomainParam = DomainParam_NIST_P521; + uint32_t Signature[RSIP_PRV_WORD_SIZE_SIGNATURE_ECC_521] = {0}; + const uint32_t signature_r_pad_byte = RSIP_PRV_BYTE_SIZE_SIGNATURE_PAD_ECC_521; + const uint32_t signature_s_pad_byte = RSIP_PRV_BYTE_SIZE_SIGNATURE_PAD_ECC_521 + + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM + + RSIP_PRV_BYTE_SIZE_SIGNATURE_PAD_ECC_521; + + memcpy((uint8_t*)Signature + signature_r_pad_byte, (uint8_t*)InData_Signature, RSIP_PRV_BYTE_SIZE_ECC_521_PARAM); + memcpy((uint8_t*)Signature + signature_s_pad_byte, (uint8_t*)InData_Signature + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM, + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM); - return r_rsip_p12(InData_KeyIndex, InData_MsgDgst, InData_Signature, InData_DomainParam); + return r_rsip_p12(InData_KeyIndex, InData_MsgDgst, Signature, InData_DomainParam); } rsip_ret_t r_rsip_wrapper_p13_secp521r1 (uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) @@ -451,6 +482,56 @@ rsip_ret_t r_rsip_wrapper_p6f_hmacsha256 (const uint32_t InData_IV[], return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); } +rsip_ret_t r_rsip_wrapper_p6f_hmacsha384 (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_HMAC_SHA384)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_HMAC_SHA384_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_hmacsha512 (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_HMAC_SHA512)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_HMAC_SHA512_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p75i (const rsip_wrapped_key_t * p_wrapped_key, + const uint32_t InData_HashType[], + const uint32_t InData_MsgLen[]) +{ + rsip_ret_t rsip_ret = select_hmac_key_index_size(p_wrapped_key); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = r_rsip_p75i((uint32_t *) p_wrapped_key->value, InData_HashType, InData_MsgLen); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_wrapper_p75r (const rsip_wrapped_key_t * p_wrapped_key, + const uint32_t InData_HashType[], + const uint32_t InData_State[]) +{ + rsip_ret_t rsip_ret = select_hmac_key_index_size(p_wrapped_key); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = r_rsip_p75r((uint32_t *) p_wrapped_key->value, InData_HashType, InData_State); + } + + return rsip_ret; +} + rsip_ret_t r_rsip_wrapper_p8f_aes128 (const uint32_t InData_KeyIndex[], const rsip_key_type_t key_type, const uint32_t InData_WrappedKeyIndex[], @@ -459,13 +540,13 @@ rsip_ret_t r_rsip_wrapper_p8f_aes128 (const uint32_t InData_KeyIndex[], uint32_t InData_Cmd[1] = {bswap_32big(0)}; uint32_t InData_WrappedKeyType[1]; - rsip_ret_t err = select_rfc3394_key_wrap_mode(key_type, InData_WrappedKeyType); - if (RSIP_RET_PASS == err) + rsip_ret_t rsip_ret = select_rfc3394_key_wrap_mode(key_type, InData_WrappedKeyType); + if (RSIP_RET_PASS == rsip_ret) { - err = r_rsip_p8f(InData_Cmd, InData_KeyIndex, InData_WrappedKeyType, InData_WrappedKeyIndex, OutData_Text); + rsip_ret = r_rsip_p8f(InData_Cmd, InData_KeyIndex, InData_WrappedKeyType, InData_WrappedKeyIndex, OutData_Text); } - return err; + return rsip_ret; } rsip_ret_t r_rsip_wrapper_p8f_aes256 (const uint32_t InData_KeyIndex[], @@ -476,13 +557,13 @@ rsip_ret_t r_rsip_wrapper_p8f_aes256 (const uint32_t InData_KeyIndex[], uint32_t InData_Cmd[1] = {bswap_32big(1)}; uint32_t InData_WrappedKeyType[1]; - rsip_ret_t err = select_rfc3394_key_wrap_mode(key_type, InData_WrappedKeyType); - if (RSIP_RET_PASS == err) + rsip_ret_t rsip_ret = select_rfc3394_key_wrap_mode(key_type, InData_WrappedKeyType); + if (RSIP_RET_PASS == rsip_ret) { - err = r_rsip_p8f(InData_Cmd, InData_KeyIndex, InData_WrappedKeyType, InData_WrappedKeyIndex, OutData_Text); + rsip_ret = r_rsip_p8f(InData_Cmd, InData_KeyIndex, InData_WrappedKeyType, InData_WrappedKeyIndex, OutData_Text); } - return err; + return rsip_ret; } rsip_ret_t r_rsip_wrapper_p90_aes128 (const uint32_t InData_KeyIndex[], @@ -494,13 +575,13 @@ rsip_ret_t r_rsip_wrapper_p90_aes128 (const uint32_t InData_KeyIndex[], uint32_t InData_Cmd[1] = {bswap_32big(0)}; uint32_t InData_WrappedKeyType[1]; - rsip_ret_t err = select_rfc3394_key_wrap_mode(key_type, InData_WrappedKeyType); - if (RSIP_RET_PASS == err) + rsip_ret_t rsip_ret = select_rfc3394_key_wrap_mode(key_type, InData_WrappedKeyType); + if (RSIP_RET_PASS == rsip_ret) { - err = r_rsip_p90(InData_KeyType, InData_Cmd, InData_KeyIndex, InData_WrappedKeyType, InData_Text, OutData_KeyIndex); + rsip_ret = r_rsip_p90(InData_KeyType, InData_Cmd, InData_KeyIndex, InData_WrappedKeyType, InData_Text, OutData_KeyIndex); } - return err; + return rsip_ret; } rsip_ret_t r_rsip_wrapper_p90_aes256 (const uint32_t InData_KeyIndex[], @@ -512,13 +593,13 @@ rsip_ret_t r_rsip_wrapper_p90_aes256 (const uint32_t InData_KeyIndex[], uint32_t InData_Cmd[1] = {bswap_32big(1)}; uint32_t InData_WrappedKeyType[1]; - rsip_ret_t err = select_rfc3394_key_wrap_mode(key_type, InData_WrappedKeyType); - if (RSIP_RET_PASS == err) + rsip_ret_t rsip_ret = select_rfc3394_key_wrap_mode(key_type, InData_WrappedKeyType); + if (RSIP_RET_PASS == rsip_ret) { - err = r_rsip_p90(InData_KeyType, InData_Cmd, InData_KeyIndex, InData_WrappedKeyType, InData_Text, OutData_KeyIndex); + rsip_ret = r_rsip_p90(InData_KeyType, InData_Cmd, InData_KeyIndex, InData_WrappedKeyType, InData_Text, OutData_KeyIndex); } - return err; + return rsip_ret; } rsip_ret_t r_rsip_wrapper_p47i_aes128ecb_encrypt (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) @@ -818,10 +899,10 @@ rsip_ret_t r_rsip_wrapper_p44f_aes256mac_verify (const uint32_t * InData_Text, static rsip_ret_t select_rfc3394_key_wrap_mode (const rsip_key_type_t key_type, uint32_t WrappedKeyType[]) { - rsip_alg_t alg = r_rsip_key_type_to_alg(key_type); - uint32_t subtype = r_rsip_key_type_to_subtype(key_type); + uint8_t alg = r_rsip_key_type_to_alg(key_type); + uint32_t subtype = r_rsip_key_type_to_subtype(key_type); - rsip_ret_t err = RSIP_RET_PASS; + rsip_ret_t rsip_ret = RSIP_RET_PASS; switch (alg) { case RSIP_ALG_AES: @@ -846,7 +927,51 @@ static rsip_ret_t select_rfc3394_key_wrap_mode (const rsip_key_type_t key_type, default: { - err = RSIP_RET_KEY_FAIL; + rsip_ret = RSIP_RET_KEY_FAIL; + } + } + break; + } + + default: + { + rsip_ret = RSIP_RET_KEY_FAIL; + } + } + + return rsip_ret; +} + +static rsip_ret_t select_hmac_key_index_size (const rsip_wrapped_key_t * p_wrapped_key) +{ + rsip_ret_t rsip_ret = RSIP_RET_PASS; + switch (p_wrapped_key->alg) + { + case RSIP_ALG_HMAC: + { + switch (p_wrapped_key->subtype) + { + case RSIP_KEY_HMAC_SHA256: + { + KEY_INDEX_SIZE = r_rsip_byte_to_word_convert(RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_HMAC_SHA256); + break; + } + + case RSIP_KEY_HMAC_SHA384: + { + KEY_INDEX_SIZE = r_rsip_byte_to_word_convert(RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_HMAC_SHA384); + break; + } + + case RSIP_KEY_HMAC_SHA512: + { + KEY_INDEX_SIZE = r_rsip_byte_to_word_convert(RSIP_CFG_BYTE_SIZE_WRAPPED_KEY_VALUE_HMAC_SHA512); + break; + } + + default: + { + rsip_ret = RSIP_RET_KEY_FAIL; } } break; @@ -854,9 +979,9 @@ static rsip_ret_t select_rfc3394_key_wrap_mode (const rsip_key_type_t key_type, default: { - err = RSIP_RET_KEY_FAIL; + rsip_ret = RSIP_RET_KEY_FAIL; } } - return err; + return rsip_ret; } diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/ra_rsip_e5xx/r_rsip_wrapper.h b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_wrapper.h similarity index 56% rename from ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/ra_rsip_e5xx/r_rsip_wrapper.h rename to ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_wrapper.h index 0d98aa967..803d00fa5 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/private/ra_rsip_e5xx/r_rsip_wrapper.h +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_wrapper.h @@ -7,9 +7,132 @@ #ifndef R_RSIP_WRAPPER_H #define R_RSIP_WRAPPER_H +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ +/* Primitive function names */ +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_AES_128 r_rsip_p07 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_AES_128 r_rsip_wrapper_p6f_aes128 +#define RSIP_PRV_FUNC_NAME_RFC3394_AES_128_KEY_WRAP r_rsip_wrapper_p8f_aes128 +#define RSIP_PRV_FUNC_NAME_RFC3394_AES_128_KEY_UNWRAP r_rsip_wrapper_p90_aes128 +#define RSIP_PRV_FUNC_NAME_OTF_CHANNEL_0_AES_128 r_rsip_p2c +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_ENC_128 r_rsip_wrapper_p47i_aes128ecb_encrypt +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_DEC_128 r_rsip_wrapper_p47i_aes128ecb_decrypt +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_128 r_rsip_wrapper_p47i_aes128cbc_encrypt +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_128 r_rsip_wrapper_p47i_aes128cbc_decrypt +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CTR_128 r_rsip_wrapper_p47i_aes128ctr_crypt +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_UPDATE_128 r_rsip_p47u +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_FINAL_128 r_rsip_p47f +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_128 r_rsip_wrapper_p29i_aes128gcm_encrypt +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_AAD_128 r_rsip_p29a +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_TRANSITION_128 r_rsip_p29t +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_128 r_rsip_p29u +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_FINAL_128 r_rsip_p29f +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_128 r_rsip_wrapper_p32i_aes128gcm_decrypt +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_AAD_128 r_rsip_p32a +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_TRANSITION_128 r_rsip_p32t +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_128 r_rsip_p32u +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_FINAL_128 r_rsip_p32f +#define RSIP_PRV_FUNC_NAME_AES_CCM_ENC_INIT_128 r_rsip_wrapper_p95i_aes128ccm_encrypt +#define RSIP_PRV_FUNC_NAME_AES_CCM_ENC_UPDATE_128 r_rsip_p95u +#define RSIP_PRV_FUNC_NAME_AES_CCM_ENC_FINAL_128 r_rsip_wrapper_p95f_aes128ccm_encrypt +#define RSIP_PRV_FUNC_NAME_AES_CCM_DEC_INIT_128 r_rsip_wrapper_p98i_aes128ccm_decrypt +#define RSIP_PRV_FUNC_NAME_AES_CCM_DEC_UPDATE_128 r_rsip_p98u +#define RSIP_PRV_FUNC_NAME_AES_CCM_DEC_FINAL_128 r_rsip_wrapper_p98f_aes128ccm_decrypt +#define RSIP_PRV_FUNC_NAME_AES_CMAC_INIT_128 r_rsip_wrapper_p41i_aes128mac +#define RSIP_PRV_FUNC_NAME_AES_CMAC_UPDATE_128 r_rsip_p41u +#define RSIP_PRV_FUNC_NAME_AES_CMAC_GENERATE_FINAL_128 r_rsip_wrapper_p41f_aes128mac_generate +#define RSIP_PRV_FUNC_NAME_AES_CMAC_VERIFY_FINAL_128 r_rsip_wrapper_p41f_aes128mac_verify +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_AES_256 r_rsip_p08 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_AES_256 r_rsip_wrapper_p6f_aes256 +#define RSIP_PRV_FUNC_NAME_RFC3394_AES_256_KEY_WRAP r_rsip_wrapper_p8f_aes256 +#define RSIP_PRV_FUNC_NAME_RFC3394_AES_256_KEY_UNWRAP r_rsip_wrapper_p90_aes256 +#define RSIP_PRV_FUNC_NAME_OTF_CHANNEL_0_AES_256 r_rsip_p2e +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_ENC_256 r_rsip_wrapper_p50i_aes256ecb_encrypt +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_DEC_256 r_rsip_wrapper_p50i_aes256ecb_decrypt +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_256 r_rsip_wrapper_p50i_aes256cbc_encrypt +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_256 r_rsip_wrapper_p50i_aes256cbc_decrypt +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CTR_256 r_rsip_wrapper_p50i_aes256ctr_crypt +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_UPDATE_256 r_rsip_p50u +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_FINAL_256 r_rsip_p50f +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_256 r_rsip_wrapper_p34i_aes256gcm_encrypt +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_AAD_256 r_rsip_p34a +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_TRANSITION_256 r_rsip_p34t +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_256 r_rsip_p34u +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_FINAL_256 r_rsip_p34f +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_256 r_rsip_wrapper_p36i_aes256gcm_decrypt +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_AAD_256 r_rsip_p36a +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_TRANSITION_256 r_rsip_p36t +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_256 r_rsip_p36u +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_FINAL_256 r_rsip_p36f +#define RSIP_PRV_FUNC_NAME_AES_CCM_ENC_INIT_256 r_rsip_wrapper_pa1i_aes256ccm_encrypt +#define RSIP_PRV_FUNC_NAME_AES_CCM_ENC_UPDATE_256 r_rsip_pa1u +#define RSIP_PRV_FUNC_NAME_AES_CCM_ENC_FINAL_256 r_rsip_pa1f +#define RSIP_PRV_FUNC_NAME_AES_CCM_DEC_INIT_256 r_rsip_wrapper_pa4i_aes256ccm_decrypt +#define RSIP_PRV_FUNC_NAME_AES_CCM_DEC_UPDATE_256 r_rsip_pa4u +#define RSIP_PRV_FUNC_NAME_AES_CCM_DEC_FINAL_256 r_rsip_pa4f +#define RSIP_PRV_FUNC_NAME_AES_CMAC_INIT_256 r_rsip_wrapper_p44i_aes256mac +#define RSIP_PRV_FUNC_NAME_AES_CMAC_UPDATE_256 r_rsip_p44u +#define RSIP_PRV_FUNC_NAME_AES_CMAC_GENERATE_FINAL_256 r_rsip_wrapper_p44f_aes256mac_generate +#define RSIP_PRV_FUNC_NAME_AES_CMAC_VERIFY_FINAL_256 r_rsip_wrapper_p44f_aes256mac_verify +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_XTS_AES_128 r_rsip_p16 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_XTS_AES_128 r_rsip_wrapper_p6f_aes128xts +#define RSIP_PRV_FUNC_NAME_XTS_AES_ENC_INIT_128 r_rsip_pb3i +#define RSIP_PRV_FUNC_NAME_XTS_AES_ENC_UPDATE_128 r_rsip_pb3u +#define RSIP_PRV_FUNC_NAME_XTS_AES_ENC_FINAL_128 r_rsip_pb3f +#define RSIP_PRV_FUNC_NAME_XTS_AES_DEC_INIT_128 r_rsip_pb6i +#define RSIP_PRV_FUNC_NAME_XTS_AES_DEC_UPDATE_128 r_rsip_pb6u +#define RSIP_PRV_FUNC_NAME_XTS_AES_DEC_FINAL_128 r_rsip_pb6f +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_XTS_AES_256 r_rsip_p17 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_XTS_AES_256 r_rsip_wrapper_p6f_aes256xts +#define RSIP_PRV_FUNC_NAME_XTS_AES_ENC_INIT_256 r_rsip_pb9i +#define RSIP_PRV_FUNC_NAME_XTS_AES_ENC_UPDATE_256 r_rsip_pb9u +#define RSIP_PRV_FUNC_NAME_XTS_AES_ENC_FINAL_256 r_rsip_pb9f +#define RSIP_PRV_FUNC_NAME_XTS_AES_DEC_INIT_256 r_rsip_pc2i +#define RSIP_PRV_FUNC_NAME_XTS_AES_DEC_UPDATE_256 r_rsip_pc2u +#define RSIP_PRV_FUNC_NAME_XTS_AES_DEC_FINAL_256 r_rsip_pc2f +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_SECP256R1 r_rsip_wrapper_pf4_secp256r1 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP256R1_PUBLIC r_rsip_wrapper_p6f_secp256r1_pub +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP256R1_PRIVATE r_rsip_wrapper_p6f_secp256r1_priv +#define RSIP_PRV_FUNC_NAME_ECDSA_SIGN_SECP256R1 r_rsip_wrapper_pf0_secp256r1 +#define RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_SECP256R1 r_rsip_wrapper_pf1_secp256r1 +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_SECP384R1 r_rsip_wrapper_pf9_secp384r1 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP384R1_PUBLIC r_rsip_wrapper_p6f_secp384r1_pub +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP384R1_PRIVATE r_rsip_wrapper_p6f_secp384r1_priv +#define RSIP_PRV_FUNC_NAME_ECDSA_SIGN_SECP384R1 r_rsip_wrapper_pf5_secp384r1 +#define RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_SECP384R1 r_rsip_wrapper_pf6_secp384r1 +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_SECP521R1 r_rsip_wrapper_p13_secp521r1 +#define RSIP_PRV_FUNC_NAME_KEY_WRAP_ECC_SECP521R1_PUBLIC r_rsip_wrapper_p6f_secp521r1_pub +#define RSIP_PRV_FUNC_NAME_KEY_WRAP_ECC_SECP521R1_PRIVATE r_rsip_wrapper_p6f_secp521r1_priv +#define RSIP_PRV_FUNC_NAME_ECDSA_SIGN_SECP521R1 r_rsip_wrapper_p11_secp521r1 +#define RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_SECP521R1 r_rsip_wrapper_p12_secp521r1 +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_RSA_2048 r_rsip_wrapper_p2b_rsa2048 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_2048_PUBLIC r_rsip_wrapper_p6f_rsa2048_pub +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_2048_PRIVATE r_rsip_wrapper_p6f_rsa2048_priv +#define RSIP_PRV_FUNC_NAME_RSA_ENCRYPT_2048 r_rsip_p56 +#define RSIP_PRV_FUNC_NAME_RSA_DECRYPT_2048 r_rsip_p57 +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_RSA_3072 r_rsip_wrapper_p3a_rsa3072 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_3072_PUBLIC r_rsip_wrapper_p6f_rsa3072_pub +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_3072_PRIVATE r_rsip_wrapper_p6f_rsa3072_priv +#define RSIP_PRV_FUNC_NAME_RSA_ENCRYPT_3072 r_rsip_p79 +#define RSIP_PRV_FUNC_NAME_RSA_DECRYPT_3072 r_rsip_p7a +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_RSA_4096 r_rsip_wrapper_p3b_rsa4096 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_4096_PUBLIC r_rsip_wrapper_p6f_rsa4096_pub +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_4096_PRIVATE r_rsip_wrapper_p6f_rsa4096_priv +#define RSIP_PRV_FUNC_NAME_RSA_ENCRYPT_4096 r_rsip_p7b +#define RSIP_PRV_FUNC_NAME_RSA_DECRYPT_4096 r_rsip_p7c +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA256 r_rsip_p0b +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA256 r_rsip_wrapper_p6f_hmacsha256 +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA384 r_rsip_p3c +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA384 r_rsip_wrapper_p6f_hmacsha384 +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA512 r_rsip_p3d +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA512 r_rsip_wrapper_p6f_hmacsha512 +#define RSIP_PRV_FUNC_NAME_RANDOM_NUMBER_GENERATE r_rsip_p20 +#define RSIP_PRV_FUNC_NAME_GHASH_COMPUTE r_rsip_p21 /* Key update inst data word */ #define RSIP_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD (0) @@ -26,6 +149,8 @@ #define RSIP_OEM_KEY_SIZE_ECC_SECP521R1_PRIVATE_KEY_INST_DATA_WORD (24) #define RSIP_OEM_KEY_SIZE_HMAC_SHA256_KEY_INST_DATA_WORD (12) +#define RSIP_OEM_KEY_SIZE_HMAC_SHA384_KEY_INST_DATA_WORD (16) +#define RSIP_OEM_KEY_SIZE_HMAC_SHA512_KEY_INST_DATA_WORD (20) #define RSIP_OEM_KEY_SIZE_RSA2048_PUBLIC_KEY_INST_DATA_WORD (72) #define RSIP_OEM_KEY_SIZE_RSA2048_PRIVATE_KEY_INST_DATA_WORD (132) @@ -126,6 +251,18 @@ rsip_ret_t r_rsip_wrapper_p6f_rsa4096_priv(const uint32_t InData_IV[], rsip_ret_t r_rsip_wrapper_p6f_hmacsha256(const uint32_t InData_IV[], const uint32_t InData_InstData[], uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_hmacsha384(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_hmacsha512(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p75i (const rsip_wrapped_key_t * p_wrapped_key, + const uint32_t InData_HashType[], + const uint32_t InData_MsgLen[]); +rsip_ret_t r_rsip_wrapper_p75r (const rsip_wrapped_key_t * p_wrapped_key, + const uint32_t InData_HashType[], + const uint32_t InData_State[]); rsip_ret_t r_rsip_wrapper_p8f_aes128 (const uint32_t InData_KeyIndex[], const rsip_key_type_t key_type, const uint32_t InData_WrappedKeyIndex[], diff --git a/ra/fsp/src/r_rtc/r_rtc.c b/ra/fsp/src/r_rtc/r_rtc.c index 5391a0a50..4dda2b179 100644 --- a/ra/fsp/src/r_rtc/r_rtc.c +++ b/ra/fsp/src/r_rtc/r_rtc.c @@ -223,6 +223,12 @@ fsp_err_t R_RTC_Open (rtc_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg) } #endif +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + + /* Enable the RTC Register Read/Write clock if it was disabled in startup. */ + bsp_prv_rtc_register_clock_set(true); +#endif + p_instance_ctrl->carry_isr_triggered = false; #if RTC_CFG_OPEN_SET_CLOCK_SOURCE @@ -294,6 +300,12 @@ fsp_err_t R_RTC_Close (rtc_ctrl_t * const p_ctrl) R_FSP_IsrContextSet(p_instance_ctrl->p_cfg->carry_irq, NULL); } +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + + /* Disable the RTC Register Read/Write clock. */ + bsp_prv_rtc_register_clock_set(false); +#endif + p_instance_ctrl->open = 0U; return FSP_SUCCESS; @@ -1613,6 +1625,12 @@ void rtc_alarm_periodic_isr (void) IRQn_Type irq = R_FSP_CurrentIrqGet(); rtc_instance_ctrl_t * p_ctrl = (rtc_instance_ctrl_t *) R_FSP_IsrContextGet(irq); +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + + /* Enable the RTC Register Read/Write clock if it was disabled prior to entering LPM. */ + bsp_prv_rtc_register_clock_set(true); +#endif + /* Call the callback routine if one is available */ if (NULL != p_ctrl->p_callback) { @@ -1659,6 +1677,12 @@ void rtc_carry_isr (void) IRQn_Type irq = R_FSP_CurrentIrqGet(); rtc_instance_ctrl_t * p_ctrl = (rtc_instance_ctrl_t *) R_FSP_IsrContextGet(irq); +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + + /* Enable the RTC Register Read/Write clock if it was disabled prior to entering LPM. */ + bsp_prv_rtc_register_clock_set(true); +#endif + p_ctrl->carry_isr_triggered = true; /* Clear the IR flag in the ICU */ diff --git a/ra/fsp/src/r_sau_i2c/r_sau_i2c.c b/ra/fsp/src/r_sau_i2c/r_sau_i2c.c index b5820b115..a66656f99 100644 --- a/ra/fsp/src/r_sau_i2c/r_sau_i2c.c +++ b/ra/fsp/src/r_sau_i2c/r_sau_i2c.c @@ -896,8 +896,9 @@ static void r_sau_i2c_hw_stop (sau_i2c_instance_ctrl_t * const p_ctrl) p_reg->SOE &= (uint16_t) ~(1 << SAU_I2C_PRV_CHANNEL); /* Clear SDA and set SCL */ - p_reg->SO = (p_reg->SO & (uint16_t) ~(SAU_I2C_SO_SDA_HIGH << SAU_I2C_PRV_CHANNEL)) | - (uint16_t) (SAU_I2C_SO_SCL_HIGH << SAU_I2C_PRV_CHANNEL); + p_reg->SO &= (uint16_t) ~(SAU_I2C_SO_SDA_HIGH << SAU_I2C_PRV_CHANNEL); + + p_reg->SO |= (uint16_t) (SAU_I2C_SO_SCL_HIGH << SAU_I2C_PRV_CHANNEL); SAU_I2C_CRITICAL_SECTION_EXIT(); diff --git a/ra/fsp/src/r_sau_spi/r_sau_spi.c b/ra/fsp/src/r_sau_spi/r_sau_spi.c index 971d62459..cce8cc3e1 100644 --- a/ra/fsp/src/r_sau_spi/r_sau_spi.c +++ b/ra/fsp/src/r_sau_spi/r_sau_spi.c @@ -10,42 +10,99 @@ #include #include "r_sau_spi.h" #include "r_sau_spi_cfg.h" +#if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + #include "r_dtc.h" +#endif /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define SAU_SPI_SCR_RX_MSK (0x4000U) -#define SAU_SPI_SCR_TX_MSK (0x8000U) -#define R_SAU0_SCR_DCP1_Pos (13U) - -#define SAU_REG_SIZE (R_SAU1_BASE - R_SAU0_BASE) -#define SAU_SPI_SMR_INIT_VALUE (0x0020U) -#define SAU_SPI_SCR_INIT_VALUE (0x0007U) - -#define SAU0_SPS_REG_INIT ((BSP_CFG_SAU_CK01_DIV << R_SAU0_SPS_PRS1_Pos) | BSP_CFG_SAU_CK00_DIV) -#define SAU1_SPS_REG_INIT ((BSP_CFG_SAU_CK11_DIV << R_SAU0_SPS_PRS1_Pos) | BSP_CFG_SAU_CK10_DIV) - -#define SAU_SPI_PSR_MIN_DIV_2 (2U) -#define SAU_SPI_PSR_MIN_DIV_4 (4U) -#define SAU_SPI_SDR_STCLK_MAX_DIV (256U) -#define SAU_SPI_PSR_MAX_DIV (32768U) -#define R_SAU_SDR_DUMMY_DATA (0xFFU) -#define SAU_SPI_STCLK_MAX (127) - -#if SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE == 1 - #define SAU_REG (R_SAU0) - #define SAU_SPS_REG_INIT (SAU0_SPS_REG_INIT) -#elif SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE == 2 - #define SAU_REG (R_SAU1) - #define SAU_SPS_REG_INIT (SAU1_SPS_REG_INIT) +#define R_SAU0_SCR_DCP1_Pos (13U) +#define SAU_SPI_PRV_DTC_RX_FOR_READ_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << \ + TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_CHAIN_MODE_EACH << \ + TRANSFER_SETTINGS_CHAIN_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << \ + TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << \ + TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define SAU_SPI_PRV_DTC_TX_FOR_READ_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << \ + TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_CHAIN_MODE_DISABLED << \ + TRANSFER_SETTINGS_CHAIN_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << \ + TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << \ + TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define SAU_SPI_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << \ + TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_CHAIN_MODE_DISABLED << \ + TRANSFER_SETTINGS_CHAIN_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << \ + TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << \ + TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define SAU_REG_SIZE (R_SAU1_BASE - R_SAU0_BASE) +#define SAU_SPI_SMR_INIT_VALUE (0x0020U) +#define SAU_SPI_SCR_INIT_VALUE (0x0007U | \ + (SAU_SPI_TRANSFER_OPERATION_MODE << R_SAU0_SCR_TRXE_Pos)) +#define SAU0_SPS_REG_INIT ((BSP_CFG_SAU_CK01_DIV << R_SAU0_SPS_PRS1_Pos) | \ + BSP_CFG_SAU_CK00_DIV) +#define SAU1_SPS_REG_INIT ((BSP_CFG_SAU_CK11_DIV << R_SAU0_SPS_PRS1_Pos) | \ + BSP_CFG_SAU_CK10_DIV) + +#define SAU_SPI_PSR_MIN_DIV_2 (2U) +#define SAU_SPI_PSR_MIN_DIV_4 (4U) +#define SAU_SPI_SDR_STCLK_MAX_DIV (256U) +#define SAU_SPI_PSR_MAX_DIV (32768U) +#define R_SAU_SDR_DUMMY_DATA (0xFFU) +#define SAU_SPI_STCLK_MAX (127) + +#if 0 == SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE /* Only SPI00 used (Unit 0 Channel 0) */ + #define SAU_SPI_PRV_CHANNEL (0) + #define SAU_SPI_PRV_UNIT (0) + #define SAU_REG (R_SAU0) + #define SAU_SPS_REG_INIT (SAU0_SPS_REG_INIT) +#elif 20 == SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE /* Only SPI20 used (Unit 1 Channel 0) */ + #define SAU_SPI_PRV_CHANNEL (0) + #define SAU_SPI_PRV_UNIT (1) + #define SAU_REG (R_SAU1) + #define SAU_SPS_REG_INIT (SAU1_SPS_REG_INIT) +#elif 11 == SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE /* Only SPI11 used (Unit 0 Channel 3) */ + #define SAU_SPI_PRV_CHANNEL (3) + #define SAU_SPI_PRV_UNIT (0) + #define SAU_REG (R_SAU0) + #define SAU_SPS_REG_INIT (SAU0_SPS_REG_INIT) +#endif + +#if -1 == SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE /* Single channel configuration disabled. */ + #define SAU_REG (p_ctrl->p_reg) + #define SAU_SPI_PRV_UNIT (p_extend->sau_unit) + #define SAU_SPI_PRV_CHANNEL_DECLARATION uint8_t channel = p_ctrl->p_cfg->channel + #define SAU_SPI_PRV_CHANNEL (channel) + #define SAU_SPS_REG_INIT (SAU_SPI_PRV_UNIT ? SAU1_SPS_REG_INIT : SAU0_SPS_REG_INIT) #else - #define SAU_REG (p_ctrl->p_reg) - #define SAU_SPS_REG_INIT ((p_extend->sau_unit) ? SAU1_SPS_REG_INIT : SAU0_SPS_REG_INIT) + #define SAU_SPI_PRV_CHANNEL_DECLARATION #endif /** "SAU" in ASCII, used to determine if channel is open. */ -#define SAU_SPI_OPEN (0x53415553ULL) +#define SAU_SPI_OPEN (0x53415553ULL) /*********************************************************************************************************************** * Private global variables. @@ -69,6 +126,20 @@ const spi_api_t g_spi_on_sau = * Private function declarations. **********************************************************************************************************************/ +#if SAU_SPI_CFG_DTC_SUPPORT_ENABLE == 1 + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION || \ + SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION + +/* constant used as the source location for the DTC dummy write */ +static const uint8_t g_dummy_write_data_for_read_op = R_SAU_SDR_DUMMY_DATA; + #endif +static fsp_err_t r_sau_spi_transfer_config(sau_spi_instance_ctrl_t * const p_ctrl); +static void r_sau_spi_reconfigure_for_transfer(sau_spi_instance_ctrl_t * const p_ctrl, uint8_t const length); + + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION +static uint8_t dummy_rx; + #endif +#endif static void r_sau_spi_hw_config(sau_spi_instance_ctrl_t * const p_ctrl); static fsp_err_t r_sau_spi_write_read_common(sau_spi_instance_ctrl_t * const p_ctrl, @@ -91,15 +162,16 @@ static void r_sau_spi_receive(sau_spi_instance_ctrl_t * p_ctrl); static void r_sau_spi_call_callback(sau_spi_instance_ctrl_t * p_ctrl, spi_event_t event); #if (SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION) -static void r_sau_spi_do_transmission(sau_spi_instance_ctrl_t * p_ctrl, spi_cfg_t const * p_cfg); +static void r_sau_spi_do_transmission(sau_spi_instance_ctrl_t * p_ctrl); #elif (SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION) -static void r_sau_spi_do_reception(sau_spi_instance_ctrl_t * p_ctrl, spi_cfg_t const * p_cfg); +static void r_sau_spi_do_reception(sau_spi_instance_ctrl_t * p_ctrl); #else -static void r_sau_spi_do_transmission_reception(sau_spi_instance_ctrl_t * p_ctrl, spi_cfg_t const * p_cfg); +static void r_sau_spi_do_transmission_reception(sau_spi_instance_ctrl_t * p_ctrl); #endif + void sau_spi_txrxi_isr(void); /*********************************************************************************************************************** @@ -135,7 +207,6 @@ fsp_err_t R_SAU_SPI_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg #if SAU_SPI_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_cfg); #endif - sau_spi_extended_cfg_t * p_extend = (sau_spi_extended_cfg_t *) p_cfg->p_extend; #if SAU_SPI_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_ctrl); @@ -144,16 +215,25 @@ fsp_err_t R_SAU_SPI_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg FSP_ASSERT(NULL != p_cfg->p_callback); FSP_ASSERT(p_cfg->tei_irq >= 0); #endif -#if !SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE - p_ctrl->p_reg = ((R_SAU0_Type *) (R_SAU0_BASE + (SAU_REG_SIZE * p_extend->sau_unit))); +#if -1 == SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE + sau_spi_extended_cfg_t const * const p_extend = (sau_spi_extended_cfg_t *) p_cfg->p_extend; + p_ctrl->p_reg = ((R_SAU0_Type *) (R_SAU0_BASE + (SAU_REG_SIZE * SAU_SPI_PRV_UNIT))); #endif p_ctrl->p_cfg = p_cfg; - p_ctrl->p_callback = p_cfg->p_callback; - p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->transfer_in_progress = false; + +#if SAU_SPI_CFG_DTC_SUPPORT_ENABLE == 1 + + /* Open the SAU SPI transfer interface if available. */ + err = r_sau_spi_transfer_config(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif /* Enable Clock for the SAU Channel. */ - R_BSP_MODULE_START(FSP_IP_SAU, p_extend->sau_unit); + R_BSP_MODULE_START(FSP_IP_SAU, SAU_SPI_PRV_UNIT); /* Write user configuration to registers. */ r_sau_spi_hw_config(p_ctrl); @@ -184,7 +264,7 @@ fsp_err_t R_SAU_SPI_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg * @param p_api_ctrl Pointer to the control structure. * @param p_dest Pointer to the destination buffer. * @param[in] length The number of bytes to transfer. - * @param[in] bit_width Invalid for SAU_SPI (Set to SPI_BIT_WIDTH_8_BITS). + * @param[in] bit_width Data frame length (Set to SPI_BIT_WIDTH_7_BITS or SPI_BIT_WIDTH_8_BITS). * * @retval FSP_SUCCESS Read operation successfully completed. * @retval FSP_ERR_ASSERTION One of the following invalid parameters passed: @@ -205,18 +285,23 @@ fsp_err_t R_SAU_SPI_Read (spi_ctrl_t * const p_api_ctrl, uint32_t const length, spi_bit_width_t const bit_width) { -#if SAU_SPI_CFG_PARAM_CHECKING_ENABLE - FSP_ASSERT(NULL != p_api_ctrl); - - /* Check bit_width parameter, in simple SPI, 7 or 8 bits operation is allowed. */ - FSP_ERROR_RETURN((SPI_BIT_WIDTH_8_BITS == bit_width) || (SPI_BIT_WIDTH_7_BITS == bit_width), FSP_ERR_UNSUPPORTED); +#if SAU_SPI_TRANSFER_OPERATION_MODE != SAU_SPI_TRANSFER_MODE_TRANSMISSION + #if SAU_SPI_CFG_PARAM_CHECKING_ENABLE /* Check the destination, should not be NULL. */ FSP_ASSERT(NULL != p_dest); -#endif + #endif sau_spi_instance_ctrl_t * p_ctrl = (sau_spi_instance_ctrl_t *) p_api_ctrl; return r_sau_spi_write_read_common(p_ctrl, NULL, p_dest, length, bit_width); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(length); + FSP_PARAMETER_NOT_USED(bit_width); + + return FSP_ERR_UNSUPPORTED; +#endif } /*******************************************************************************************************************//** @@ -236,7 +321,7 @@ fsp_err_t R_SAU_SPI_Read (spi_ctrl_t * const p_api_ctrl, * @param p_api_ctrl Pointer to the control structure. * @param p_src Pointer to the source buffer. * @param[in] length The number of bytes to transfer. - * @param[in] bit_width Invalid for SAU_SPI (Set to SPI_BIT_WIDTH_8_BITS). + * @param[in] bit_width Data frame length (Set to SPI_BIT_WIDTH_7_BITS or SPI_BIT_WIDTH_8_BITS). * * @retval FSP_SUCCESS Write operation successfully completed. * @retval FSP_ERR_ASSERTION One of the following invalid parameters passed: @@ -257,14 +342,21 @@ fsp_err_t R_SAU_SPI_Write (spi_ctrl_t * const p_api_ctrl, uint32_t const length, spi_bit_width_t const bit_width) { -#if SAU_SPI_CFG_PARAM_CHECKING_ENABLE - FSP_ASSERT(NULL != p_api_ctrl); - FSP_ERROR_RETURN((SPI_BIT_WIDTH_8_BITS == bit_width) || (SPI_BIT_WIDTH_7_BITS == bit_width), FSP_ERR_UNSUPPORTED); +#if SAU_SPI_TRANSFER_OPERATION_MODE != SAU_SPI_TRANSFER_MODE_RECEPTION + #if SAU_SPI_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_src); -#endif + #endif sau_spi_instance_ctrl_t * p_ctrl = (sau_spi_instance_ctrl_t *) p_api_ctrl; return r_sau_spi_write_read_common(p_ctrl, p_src, NULL, length, bit_width); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(length); + FSP_PARAMETER_NOT_USED(bit_width); + + return FSP_ERR_UNSUPPORTED; +#endif } /*******************************************************************************************************************//** @@ -288,7 +380,7 @@ fsp_err_t R_SAU_SPI_Write (spi_ctrl_t * const p_api_ctrl, * @param p_src Pointer to the source buffer. * @param p_dest Pointer to the destination buffer. * @param[in] length The number of bytes to transfer. - * @param[in] bit_width Invalid for SAU_SPI (Set to SPI_BIT_WIDTH_8_BITS). + * @param[in] bit_width Data frame length (Set to SPI_BIT_WIDTH_7_BITS or SPI_BIT_WIDTH_8_BITS). * * @retval FSP_SUCCESS Write operation successfully completed. * @retval FSP_ERR_ASSERTION One of the following invalid parameters passed: @@ -311,15 +403,23 @@ fsp_err_t R_SAU_SPI_WriteRead (spi_ctrl_t * const p_api_ctrl, uint32_t const length, spi_bit_width_t const bit_width) { -#if SAU_SPI_CFG_PARAM_CHECKING_ENABLE - FSP_ASSERT(NULL != p_api_ctrl); - FSP_ERROR_RETURN((SPI_BIT_WIDTH_8_BITS == bit_width) || (SPI_BIT_WIDTH_7_BITS == bit_width), FSP_ERR_UNSUPPORTED); +#if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION + #if SAU_SPI_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_src); FSP_ASSERT(NULL != p_dest); -#endif + #endif sau_spi_instance_ctrl_t * p_ctrl = (sau_spi_instance_ctrl_t *) p_api_ctrl; return r_sau_spi_write_read_common(p_ctrl, p_src, p_dest, length, bit_width); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(length); + FSP_PARAMETER_NOT_USED(bit_width); + + return FSP_ERR_UNSUPPORTED; +#endif } /*******************************************************************************************************************//** @@ -337,7 +437,7 @@ fsp_err_t R_SAU_SPI_CallbackSet (spi_ctrl_t * const p_api_ctrl, { sau_spi_instance_ctrl_t * p_ctrl = (sau_spi_instance_ctrl_t *) p_api_ctrl; -#if (SAU_SPI_CFG_PARAM_CHECKING_ENABLE) +#if SAU_SPI_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(p_ctrl); FSP_ASSERT(p_callback); FSP_ERROR_RETURN(SAU_SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); @@ -369,17 +469,19 @@ fsp_err_t R_SAU_SPI_Close (spi_ctrl_t * const p_api_ctrl) FSP_ASSERT(NULL != p_ctrl); FSP_ERROR_RETURN(SAU_SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif - spi_cfg_t const * p_cfg = p_ctrl->p_cfg; + + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; /* Clear the RE and TE bits in SCR. */ - SAU_REG->SCR[p_cfg->channel] = 0; + SAU_REG->SCR[SAU_SPI_PRV_CHANNEL] = 0; #if SAU_SPI_CFG_CRITICAL_SECTION_ENABLE FSP_CRITICAL_SECTION_DEFINE; FSP_CRITICAL_SECTION_ENTER; #endif - SAU_REG->ST |= (uint16_t) (1 << p_cfg->channel); - SAU_REG->SOE &= (uint16_t) ~(1 << p_cfg->channel); + SAU_REG->ST |= (uint16_t) (1 << SAU_SPI_PRV_CHANNEL); + SAU_REG->SOE &= (uint16_t) ~(1 << SAU_SPI_PRV_CHANNEL); #if SAU_SPI_CFG_CRITICAL_SECTION_ENABLE FSP_CRITICAL_SECTION_EXIT; #endif @@ -387,6 +489,10 @@ fsp_err_t R_SAU_SPI_Close (spi_ctrl_t * const p_api_ctrl) p_ctrl->open = 0U; +#if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); +#endif + return FSP_SUCCESS; } @@ -416,20 +522,20 @@ fsp_err_t R_SAU_SPI_CalculateBitrate (uint32_t bitrate, FSP_ASSERT(bitrate); if ((0 == sau_unit) && (0 == channel)) { - FSP_ASSERT(bitrate <= (peripheral_clock) / SAU_SPI_PSR_MIN_DIV_2); + FSP_ASSERT(bitrate <= peripheral_clock / SAU_SPI_PSR_MIN_DIV_2); } else { - FSP_ASSERT(bitrate <= (peripheral_clock) / SAU_SPI_PSR_MIN_DIV_4); + FSP_ASSERT(bitrate <= peripheral_clock / SAU_SPI_PSR_MIN_DIV_4); } - FSP_ASSERT(bitrate >= (peripheral_clock) / SAU_SPI_SDR_STCLK_MAX_DIV / SAU_SPI_PSR_MAX_DIV); + FSP_ASSERT(bitrate >= peripheral_clock / SAU_SPI_SDR_STCLK_MAX_DIV / SAU_SPI_PSR_MAX_DIV); #else FSP_PARAMETER_NOT_USED(channel); #endif uint32_t best_delta_error = UINT32_MAX; -#if SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE +#if SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE != -1 const uint32_t sps = SAU_SPS_REG_INIT; FSP_PARAMETER_NOT_USED(sau_unit); #else @@ -479,109 +585,231 @@ static void r_sau_spi_hw_config (sau_spi_instance_ctrl_t * const p_ctrl) { spi_cfg_t const * p_cfg = p_ctrl->p_cfg; sau_spi_extended_cfg_t * p_extend = (sau_spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + R_SAU0_Type * p_reg = SAU_REG; + + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; /* Initialize registers to their reset values. */ uint16_t smr = SAU_SPI_SMR_INIT_VALUE; uint16_t scr = SAU_SPI_SCR_INIT_VALUE; -#if SAU_SPI_CFG_CRITICAL_SECTION_ENABLE - FSP_CRITICAL_SECTION_DEFINE; - FSP_CRITICAL_SECTION_ENTER; -#endif - uint16_t so = SAU_REG->SO; -#if SAU_SPI_CFG_CRITICAL_SECTION_ENABLE - FSP_CRITICAL_SECTION_EXIT; -#endif - p_ctrl->transfer_in_progress = false; - - /* Select the baud rate generator clock divider. */ - if (SPI_MODE_MASTER == p_cfg->operating_mode) - { - /* Configure the operation clock divisor based on BSP settings */ - SAU_REG->SPS = SAU_SPS_REG_INIT; - } - smr |= - (uint16_t) (p_extend->clk_div.operation_clock << R_SAU0_SMR_CKS_Pos) | - (uint16_t) ((uint16_t) (p_cfg->operating_mode << R_SAU0_SMR_CCS_Pos) | - (uint16_t) (p_extend->transfer_mode << R_SAU0_SMR_MD0_Pos)); + /* Write settings that are common to master and slave mode. */ + smr |= ((uint16_t) (p_cfg->operating_mode << R_SAU0_SMR_CCS_Pos) | + (uint16_t) (p_extend->transfer_mode << R_SAU0_SMR_MD0_Pos)); - SAU_REG->SMR[p_cfg->channel] = smr; -#if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION - scr |= (uint16_t) (SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION << R_SAU0_SCR_TRXE_Pos) | - (uint16_t) (p_extend->data_phase << R_SAU0_SCR_DCP1_Pos) | - (uint16_t) (p_extend->clock_phase << R_SAU0_SCR_DCP_Pos) | - (uint16_t) (p_cfg->bit_order << R_SAU0_SCR_DIR_Pos); -#endif -#if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION - scr |= (uint16_t) (SAU_SPI_TRANSFER_MODE_RECEPTION << R_SAU0_SCR_TRXE_Pos) | - (uint16_t) (p_extend->data_phase << R_SAU0_SCR_DCP1_Pos) | - (uint16_t) (p_extend->clock_phase << R_SAU0_SCR_DCP_Pos) | - (uint16_t) (p_cfg->bit_order << R_SAU0_SCR_DIR_Pos); -#endif -#if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION - scr |= (uint16_t) (SAU_SPI_TRANSFER_MODE_TRANSMISSION << R_SAU0_SCR_TRXE_Pos) | - (uint16_t) (p_extend->data_phase << R_SAU0_SCR_DCP1_Pos) | + scr |= (uint16_t) (p_extend->data_phase << R_SAU0_SCR_DCP1_Pos) | (uint16_t) (p_extend->clock_phase << R_SAU0_SCR_DCP_Pos) | (uint16_t) (p_cfg->bit_order << R_SAU0_SCR_DIR_Pos); + +#if SAU_SPI_CFG_CRITICAL_SECTION_ENABLE + + /* Enter critical section when modifying registers that are shared between channels (SPS, SS, SO, SOE). */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; #endif - SAU_REG->SCR[p_cfg->channel] = scr; + + uint16_t so = p_reg->SO; + uint16_t sdr = 0; if (SPI_MODE_MASTER == p_cfg->operating_mode) { - SAU_REG->SDR[p_cfg->channel] = (uint16_t) (p_extend->clk_div.stclk << R_SAU0_SDR_STCLK_Pos); + /* Write settings that are only used in master mode. */ + p_reg->SPS = SAU_SPS_REG_INIT; + + smr |= (uint16_t) (p_extend->clk_div.operation_clock << R_SAU0_SMR_CKS_Pos); + sdr = (uint16_t) (p_extend->clk_div.stclk << R_SAU0_SDR_STCLK_Pos); if (SAU_SPI_CLOCK_PHASE_REVERSE == p_extend->clock_phase) { - so &= (uint16_t) ~(1 << (R_SAU0_SO_CKO_Pos + p_cfg->channel)); + so &= (uint16_t) ~(1 << (R_SAU0_SO_CKO_Pos + SAU_SPI_PRV_CHANNEL)); } else { - so |= (uint16_t) (1 << (R_SAU0_SO_CKO_Pos + p_cfg->channel)); + so |= (uint16_t) (1 << (R_SAU0_SO_CKO_Pos + SAU_SPI_PRV_CHANNEL)); } } else { - SAU_REG->SDR[p_cfg->channel] = 0; + /* Write settings that are only used in slave mode. */ + if ((0 == SAU_SPI_PRV_UNIT) && (0 == SAU_SPI_PRV_CHANNEL)) + { + /* Enable IRQ0 pin as an external interrupt for SAU unit 0 channel 0. */ + R_PORGA->ISC_b.SSIE00 = 1U; + } } +#if SAU_SPI_TRANSFER_OPERATION_MODE != SAU_SPI_TRANSFER_MODE_RECEPTION + + /* Set initial serial output data to 0 if transmit is enabled. */ + so &= (uint16_t) ~(1 << SAU_SPI_PRV_CHANNEL); + + /* Only enable serial output if transmit is enabled. */ + p_reg->SOE |= (uint16_t) (1 << (SAU_SPI_PRV_CHANNEL)); +#endif + + p_reg->SMR[SAU_SPI_PRV_CHANNEL] = smr; + p_reg->SCR[SAU_SPI_PRV_CHANNEL] = scr; + p_reg->SDR[SAU_SPI_PRV_CHANNEL] = sdr; + p_reg->SO = so; + + SAU_REG->SS = (uint16_t) (1 << (SAU_SPI_PRV_CHANNEL)); + #if SAU_SPI_CFG_CRITICAL_SECTION_ENABLE - FSP_CRITICAL_SECTION_ENTER; + FSP_CRITICAL_SECTION_EXIT; #endif +} -#if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION +#if SAU_SPI_CFG_DTC_SUPPORT_ENABLE == 1 + +/*******************************************************************************************************************//** + * Configures SAU SPI related transfer drivers (if enabled). + * + * @param[in] p_ctrl Pointer to the control structure. + * + * @retval FSP_SUCCESS Operation successfully completed. + * @retval FSP_ERR_ASSERTION One of the following invalid parameters passed: + * - Pointer p_cfg is NULL + * - Interrupt is not enabled + * @retval FSP_ERR_INVALID_ARGUMENT DTC is used for data transmission but not used for data reception or + * vice versa. + **********************************************************************************************************************/ +static fsp_err_t r_sau_spi_transfer_config (sau_spi_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + spi_cfg_t const * const p_cfg = p_ctrl->p_cfg; + + /* Set default transfer info and open receive transfer module, if enabled. */ + #if SAU_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg->p_transfer_tx->p_api); + FSP_ASSERT(NULL != p_cfg->p_transfer_tx->p_ctrl); + FSP_ASSERT(NULL != p_cfg->p_transfer_tx->p_cfg); + #endif + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION + transfer_info_t * p_info_rx = &(p_cfg->p_transfer_tx->p_cfg->p_info[0]); + transfer_info_t * p_info_tx = &(p_cfg->p_transfer_tx->p_cfg->p_info[1]); + + /* Set the initial configuration for the rx transfer instance. */ + p_info_rx->transfer_settings_word = SAU_SPI_PRV_DTC_RX_FOR_READ_TRANSFER_SETTINGS; + p_info_rx->p_src = (void *) (&(SAU_REG->SDR[p_cfg->channel])); + + /* Set the initial configuration for the tx transfer instance. */ + p_info_tx->transfer_settings_word = SAU_SPI_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS; + p_info_tx->p_dest = (void *) (&(SAU_REG->SDR[p_cfg->channel])); + #endif + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION + transfer_info_t * p_info_tx = &(p_cfg->p_transfer_tx->p_cfg->p_info[1]); + + /* Set the initial configuration for the tx transfer instance. */ + p_info_tx->transfer_settings_word = SAU_SPI_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS; + p_info_tx->p_dest = (void *) (&(SAU_REG->SDR[p_cfg->channel])); + #endif + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION + transfer_info_t * p_info_rx = &(p_cfg->p_transfer_tx->p_cfg->p_info[0]); + transfer_info_t * p_info_tx = &(p_cfg->p_transfer_tx->p_cfg->p_info[1]); if (SPI_MODE_MASTER == p_cfg->operating_mode) { - SAU_REG->SO = so; + p_info_rx->transfer_settings_word = SAU_SPI_PRV_DTC_RX_FOR_READ_TRANSFER_SETTINGS; + p_info_rx->p_src = (void *) (&(SAU_REG->SDR[p_cfg->channel])); + + /* Set the initial configuration for the tx transfer instance. */ + p_info_tx->transfer_settings_word = SAU_SPI_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS; + p_info_tx->p_dest = (void *) (&(SAU_REG->SDR[p_cfg->channel])); + } + else + { + /* Set the initial configuration for the tx transfer instance. */ + p_info_tx->transfer_settings_word = SAU_SPI_PRV_DTC_TX_FOR_READ_TRANSFER_SETTINGS; + p_info_tx->p_src = (void *) (&(SAU_REG->SDR[p_cfg->channel])); } + #endif + err = p_cfg->p_transfer_tx->p_api->open(p_cfg->p_transfer_tx->p_ctrl, p_cfg->p_transfer_tx->p_cfg); -#else - so &= (uint16_t) ~(1 << (p_cfg->channel)); - SAU_REG->SO = so; - SAU_REG->SOE |= (uint16_t) (1 << (p_cfg->channel)); -#endif + return err; +} - if ((0 == p_extend->sau_unit) && (0 == p_cfg->channel)) +/******************************************************************************************************************//** + * Reconfigure the address mode for transfer interface + * + * @param[in] p_ctrl Pointer to the control structure. + * @param[in] p_cfg Pointer to a configuration structure. + * @param[in] length Number of data already transferred. + **********************************************************************************************************************/ +static void r_sau_spi_reconfigure_for_transfer (sau_spi_instance_ctrl_t * const p_ctrl, uint8_t const length) +{ + spi_cfg_t const * const p_cfg = p_ctrl->p_cfg; + + transfer_instance_t const * p_transfer = p_cfg->p_transfer_tx; + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION + transfer_info_t * p_info_tx = &(p_transfer->p_cfg->p_info[1]); + p_info_tx->length = (uint16_t) (p_ctrl->count - length); + p_info_tx->p_src = p_ctrl->p_src + length; + p_info_tx->transfer_settings_word = SAU_SPI_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS; + p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_info_tx); + #endif + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION + SAU_SPI_PRV_CHANNEL_DECLARATION; + + transfer_info_t * p_info_rx = &(p_transfer->p_cfg->p_info[0]); + transfer_info_t * p_info_tx = &(p_transfer->p_cfg->p_info[1]); + p_info_tx->length = (uint16_t) (p_ctrl->count - length); + + if (SPI_MODE_MASTER == p_cfg->operating_mode) { - if (SPI_MODE_SLAVE == p_cfg->operating_mode) - { - R_PORGA->ISC_b.SSIE00 = 1U; - } + p_info_rx->p_dest = p_ctrl->p_dest; + p_info_tx->p_src = (void *) &g_dummy_write_data_for_read_op; + p_info_tx->p_dest = (void *) &(SAU_REG->SDR[SAU_SPI_PRV_CHANNEL]); + p_info_tx->transfer_settings_word = SAU_SPI_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS; + p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_info_rx); + } + else + { + /* Configure the tx transfer instance. */ + p_info_tx->p_src = (void *) &(SAU_REG->SDR[SAU_SPI_PRV_CHANNEL]); + p_info_tx->transfer_settings_word = SAU_SPI_PRV_DTC_TX_FOR_READ_TRANSFER_SETTINGS; + p_info_tx->p_dest = p_ctrl->p_dest; + + /* Enable the transfer instance. */ + p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_info_tx); + } + #endif + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION + transfer_info_t * p_info_rx = &(p_transfer->p_cfg->p_info[0]); + transfer_info_t * p_info_tx = &(p_transfer->p_cfg->p_info[1]); + p_info_tx->length = (uint16_t) (p_ctrl->count - length); + if (NULL == p_ctrl->p_dest) + { + p_info_rx->p_dest = &dummy_rx; + p_info_rx->transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_info_tx->p_src = p_ctrl->p_src + length; + } + else if (NULL == p_ctrl->p_src) + { + p_info_rx->p_dest = p_ctrl->p_dest; + p_info_rx->transfer_settings_word = SAU_SPI_PRV_DTC_RX_FOR_READ_TRANSFER_SETTINGS; + p_info_tx->p_src = (void *) &g_dummy_write_data_for_read_op; } + else + { + p_info_rx->p_dest = p_ctrl->p_dest; + p_info_rx->transfer_settings_word = SAU_SPI_PRV_DTC_RX_FOR_READ_TRANSFER_SETTINGS; + p_info_tx->p_src = p_ctrl->p_src + length; + } + p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_info_rx); + #endif + p_ctrl->activation_on_tei = true; +} - SAU_REG->SS |= (uint16_t) (1 << (p_cfg->channel)); -#if SAU_SPI_CFG_CRITICAL_SECTION_ENABLE - FSP_CRITICAL_SECTION_EXIT; #endif -} /*******************************************************************************************************************//** - * Initiates writ or read process. Common routine used by SPI API write or read functions. + * Initiates write or read process. Common routine used by SPI API write or read functions. * * @param[in] p_ctrl Pointer to the control block. * @param[in] p_src Pointer to data buffer which need to be sent. * @param[out] p_dest Pointer to buffer where received data will be stored. * @param[in] length Number of data transactions to be performed. - * @param[in] bit_width Invalid for SAU_SPI (Set to SPI_BIT_WIDTH_8_BITS). + * @param[in] bit_width Data frame length (Set to SPI_BIT_WIDTH_7_BITS or SPI_BIT_WIDTH_8_BITS). * * @retval FSP_SUCCESS Operation successfully completed. * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. @@ -604,31 +832,48 @@ static fsp_err_t r_sau_spi_write_read_common (sau_spi_instance_ctrl_t * const p_ FSP_ASSERT(NULL != p_ctrl); FSP_ERROR_RETURN(SAU_SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); FSP_ASSERT(0 != length); + FSP_ERROR_RETURN((SPI_BIT_WIDTH_8_BITS == bit_width) || (SPI_BIT_WIDTH_7_BITS == bit_width), FSP_ERR_UNSUPPORTED); + + #if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + + /* DTC on RX could actually receive 65535+3 = 65538 bytes as 3 bytes are handled separately. + * Forcing to 65535 to keep TX and RX uniform with respect to max transaction length via DTC. + */ + FSP_ASSERT(length <= UINT16_MAX); + #endif #endif - spi_cfg_t const * p_cfg = p_ctrl->p_cfg; sau_spi_extended_cfg_t * p_extend = (sau_spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend; FSP_ERROR_RETURN(p_ctrl->transfer_in_progress == false, FSP_ERR_IN_USE); - if (SPI_BIT_WIDTH_8_BITS == bit_width) - { - SAU_REG->SCR[p_cfg->channel] |= R_SAU0_SCR_DLS_Msk; - } - else - { - SAU_REG->SCR[p_cfg->channel] &= (uint16_t) ~1; - } + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + + /* Writing to SCR is prohibited while the channel is enabled. If the bit width is changed, disable communication + * before writing to SCR. (See Section 21.3.4 in the RA0E1 user manual R01UH1040EJ0100). */ + SAU_REG->ST = (uint16_t) (1 << SAU_SPI_PRV_CHANNEL); + + /* Bit width is configured in SCR::DLS[1:0]: + * - 7bit: 0b10 + * - 8bit: 0b11 + */ + uint16_t tmp = SAU_REG->SCR[SAU_SPI_PRV_CHANNEL]; + SAU_REG->SCR[SAU_SPI_PRV_CHANNEL] = (uint16_t) (tmp & (uint16_t) ~1) | (SPI_BIT_WIDTH_8_BITS == bit_width); + + SAU_REG->SS = (uint16_t) (1 << SAU_SPI_PRV_CHANNEL); + tmp = SAU_REG->SMR[SAU_SPI_PRV_CHANNEL]; if (SAU_SPI_TRANSFER_MODE_CONTINUOUS == p_extend->transfer_mode) { - if (1 == length) - { - SAU_REG->SMR[p_cfg->channel] &= (uint16_t) ~R_SAU0_SMR_MD0_Msk; - } - else + tmp &= (uint16_t) ~R_SAU0_SMR_MD0_Msk; + + /* Continuous mode can be used only when length > 1. When DTC is enabled, the length needs to be greater than 2. */ + if (2 < length) { - SAU_REG->SMR[p_cfg->channel] |= (uint16_t) R_SAU0_SMR_MD0_Msk; + tmp |= (uint16_t) R_SAU0_SMR_MD0_Msk; } + + SAU_REG->SMR[SAU_SPI_PRV_CHANNEL] = tmp; } /* Setup the control block. */ @@ -637,6 +882,13 @@ static fsp_err_t r_sau_spi_write_read_common (sau_spi_instance_ctrl_t * const p_ p_ctrl->rx_count = 0U; p_ctrl->p_src = (uint8_t *) p_src; p_ctrl->p_dest = (uint8_t *) p_dest; +#if SAU_SPI_CFG_DTC_SUPPORT_ENABLE == 1 + p_ctrl->activation_on_tei = false; + if ((1 < length) && !(tmp & (SAU_SPI_TRANSFER_MODE_CONTINUOUS << R_SAU0_SMR_MD0_Pos))) + { + r_sau_spi_reconfigure_for_transfer(p_ctrl, 1); + } +#endif /* Enable transmit and receive interrupts. */ r_sau_spi_start_transfer(p_ctrl); @@ -652,13 +904,16 @@ static fsp_err_t r_sau_spi_write_read_common (sau_spi_instance_ctrl_t * const p_ static void r_sau_spi_start_transfer (sau_spi_instance_ctrl_t * const p_ctrl) { p_ctrl->transfer_in_progress = true; - #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION + + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + spi_cfg_t const * p_cfg = p_ctrl->p_cfg; if (SPI_MODE_MASTER == p_cfg->operating_mode) { /* start receive by dummy write */ - SAU_REG->SDR_b[p_cfg->channel].DAT = R_SAU_SDR_DUMMY_DATA; + SAU_REG->SDR[SAU_SPI_PRV_CHANNEL] = R_SAU_SDR_DUMMY_DATA; } #else @@ -678,13 +933,11 @@ static void r_sau_spi_start_transfer (sau_spi_instance_ctrl_t * const p_ctrl) **********************************************************************************************************************/ static void r_sau_spi_transmit (sau_spi_instance_ctrl_t * p_ctrl) { - spi_cfg_t const * p_cfg = p_ctrl->p_cfg; - sau_spi_extended_cfg_t * p_extend = (sau_spi_extended_cfg_t *) p_cfg->p_extend; - - uint16_t dat = (uint16_t) (p_extend->clk_div.stclk << R_SAU0_SDR_STCLK_Pos); + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; - dat |= p_ctrl->p_src ? p_ctrl->p_src[p_ctrl->tx_count] : R_SAU_SDR_DUMMY_DATA; - SAU_REG->SDR[p_cfg->channel] = dat; + uint16_t dat = p_ctrl->p_src ? p_ctrl->p_src[p_ctrl->tx_count] : R_SAU_SDR_DUMMY_DATA; + SAU_REG->SDR[SAU_SPI_PRV_CHANNEL] = dat; p_ctrl->tx_count++; } @@ -702,7 +955,7 @@ static void r_sau_spi_receive (sau_spi_instance_ctrl_t * p_ctrl) { spi_cfg_t const * p_cfg = p_ctrl->p_cfg; uint8_t dat = (uint8_t) (SAU_REG->SDR[p_cfg->channel] & R_SAU_SDR_DUMMY_DATA); - if (p_ctrl) + if (p_ctrl->p_dest) { p_ctrl->p_dest[p_ctrl->rx_count] = dat; } @@ -742,22 +995,24 @@ void sau_spi_txrxi_isr (void) IRQn_Type irq = R_FSP_CurrentIrqGet(); sau_spi_instance_ctrl_t * p_ctrl = (sau_spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); - spi_cfg_t const * p_cfg = p_ctrl->p_cfg; - uint16_t err_type = SAU_REG->SSR[p_cfg->channel] & R_SAU0_SSR_OVF_Msk; + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + + uint16_t err_type = SAU_REG->SSR[SAU_SPI_PRV_CHANNEL] & R_SAU0_SSR_OVF_Msk; if (err_type) { - SAU_REG->SIR[p_cfg->channel] = err_type; + SAU_REG->SIR[SAU_SPI_PRV_CHANNEL] = err_type; r_sau_spi_call_callback(p_ctrl, SPI_EVENT_ERR_READ_OVERFLOW); } else { #if (SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION) - r_sau_spi_do_reception(p_ctrl, p_cfg); + r_sau_spi_do_reception(p_ctrl); #elif (SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION) - r_sau_spi_do_transmission(p_ctrl, p_cfg); + r_sau_spi_do_transmission(p_ctrl); #else - r_sau_spi_do_transmission_reception(p_ctrl, p_cfg); + r_sau_spi_do_transmission_reception(p_ctrl); #endif } @@ -766,14 +1021,31 @@ void sau_spi_txrxi_isr (void) } #if (SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION) -void r_sau_spi_do_reception (sau_spi_instance_ctrl_t * p_ctrl, spi_cfg_t const * p_cfg) +static void r_sau_spi_do_reception (sau_spi_instance_ctrl_t * p_ctrl) { - uint16_t smr = SAU_REG->SMR[p_cfg->channel]; - if (smr & (SAU_SPI_TRANSFER_MODE_CONTINUOUS << R_SAU0_SMR_MD0_Pos)) + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + + uint16_t smr = SAU_REG->SMR[SAU_SPI_PRV_CHANNEL]; + uint8_t continous_transfer = smr & R_SAU0_SMR_MD0_Msk; + #if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + if (true == p_ctrl->activation_on_tei) + { + p_ctrl->activation_on_tei = false; + p_ctrl->rx_count = p_ctrl->count - 1 - continous_transfer; + p_ctrl->tx_count = p_ctrl->count; + + return; + } + #endif + if (continous_transfer) { if (0 == p_ctrl->tx_count) { - SAU_REG->SDR_b[p_cfg->channel].DAT = R_SAU_SDR_DUMMY_DATA; + #if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + r_sau_spi_reconfigure_for_transfer(p_ctrl, 2); + #endif + SAU_REG->SDR_b[SAU_SPI_PRV_CHANNEL].DAT = R_SAU_SDR_DUMMY_DATA; p_ctrl->tx_count++; } else @@ -781,12 +1053,12 @@ void r_sau_spi_do_reception (sau_spi_instance_ctrl_t * p_ctrl, spi_cfg_t const * r_sau_spi_receive(p_ctrl); if (p_ctrl->rx_count < (p_ctrl->count - 1U)) { - SAU_REG->SDR_b[p_cfg->channel].DAT = R_SAU_SDR_DUMMY_DATA; + SAU_REG->SDR[SAU_SPI_PRV_CHANNEL] = R_SAU_SDR_DUMMY_DATA; } else if (p_ctrl->rx_count == (p_ctrl->count - 1U)) { - smr &= (uint16_t) ~(SAU_SPI_TRANSFER_MODE_CONTINUOUS); - SAU_REG->SMR[p_cfg->channel] = smr; + smr &= (uint16_t) ~SAU_SPI_TRANSFER_MODE_CONTINUOUS; + SAU_REG->SMR[SAU_SPI_PRV_CHANNEL] = smr; } else { @@ -805,26 +1077,47 @@ void r_sau_spi_do_reception (sau_spi_instance_ctrl_t * p_ctrl, spi_cfg_t const * } else { - if (SPI_MODE_MASTER == p_cfg->operating_mode) + if (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) { - SAU_REG->SDR_b[p_cfg->channel].DAT = R_SAU_SDR_DUMMY_DATA; + SAU_REG->SDR[SAU_SPI_PRV_CHANNEL] = R_SAU_SDR_DUMMY_DATA; } } } } #elif (SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION) -void r_sau_spi_do_transmission (sau_spi_instance_ctrl_t * p_ctrl, spi_cfg_t const * p_cfg) +static void r_sau_spi_do_transmission (sau_spi_instance_ctrl_t * p_ctrl) { - uint16_t smr = SAU_REG->SMR[p_cfg->channel]; + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + + uint16_t smr = SAU_REG->SMR[SAU_SPI_PRV_CHANNEL]; + uint8_t continous_transfer = smr & R_SAU0_SMR_MD0_Msk; + #if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + if (true == p_ctrl->activation_on_tei) + { + p_ctrl->activation_on_tei = false; + p_ctrl->tx_count = p_ctrl->count; + + return; + } + + if (continous_transfer) + { + if (1U == p_ctrl->tx_count) + { + r_sau_spi_reconfigure_for_transfer(p_ctrl, 2); + } + } + #endif if (p_ctrl->tx_count < p_ctrl->count) { r_sau_spi_transmit(p_ctrl); } - else if (smr & (SAU_SPI_TRANSFER_MODE_CONTINUOUS << R_SAU0_SMR_MD0_Pos)) + else if (continous_transfer) { - smr &= (uint16_t) ~(SAU_SPI_TRANSFER_MODE_CONTINUOUS); - SAU_REG->SMR[p_cfg->channel] = smr; + smr &= (uint16_t) ~SAU_SPI_TRANSFER_MODE_CONTINUOUS; + SAU_REG->SMR[SAU_SPI_PRV_CHANNEL] = smr; } else { @@ -834,15 +1127,36 @@ void r_sau_spi_do_transmission (sau_spi_instance_ctrl_t * p_ctrl, spi_cfg_t cons } #else -void r_sau_spi_do_transmission_reception (sau_spi_instance_ctrl_t * p_ctrl, spi_cfg_t const * p_cfg) +static void r_sau_spi_do_transmission_reception (sau_spi_instance_ctrl_t * p_ctrl) { - uint16_t smr = SAU_REG->SMR[p_cfg->channel]; - if (smr & (SAU_SPI_TRANSFER_MODE_CONTINUOUS << R_SAU0_SMR_MD0_Pos)) + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + + uint16_t smr = SAU_REG->SMR[SAU_SPI_PRV_CHANNEL]; + uint8_t continous_transfer = smr & R_SAU0_SMR_MD0_Msk; + #if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + if (true == p_ctrl->activation_on_tei) + { + p_ctrl->activation_on_tei = false; + p_ctrl->rx_count = p_ctrl->count - 1 - continous_transfer; + p_ctrl->tx_count = p_ctrl->count; + + return; + } + #endif + if (continous_transfer) { if (1U < p_ctrl->tx_count) { r_sau_spi_receive(p_ctrl); } + + #if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + else + { + r_sau_spi_reconfigure_for_transfer(p_ctrl, 2); + } + #endif } else { @@ -853,11 +1167,11 @@ void r_sau_spi_do_transmission_reception (sau_spi_instance_ctrl_t * p_ctrl, spi_ { r_sau_spi_transmit(p_ctrl); } - else if (smr & (SAU_SPI_TRANSFER_MODE_CONTINUOUS << R_SAU0_SMR_MD0_Pos)) + else if (continous_transfer) { /* 2nd to last byte */ - smr &= (uint16_t) ~(SAU_SPI_TRANSFER_MODE_CONTINUOUS); - SAU_REG->SMR[p_cfg->channel] = smr; + smr &= (uint16_t) ~SAU_SPI_TRANSFER_MODE_CONTINUOUS; + SAU_REG->SMR[SAU_SPI_PRV_CHANNEL] = smr; } else { diff --git a/ra/fsp/src/r_sau_uart/r_sau_uart.c b/ra/fsp/src/r_sau_uart/r_sau_uart.c index a938175c9..2214cedbf 100644 --- a/ra/fsp/src/r_sau_uart/r_sau_uart.c +++ b/ra/fsp/src/r_sau_uart/r_sau_uart.c @@ -95,6 +95,7 @@ #define SAU_UART_SCR_DEFAULT_VALUE (0x0004U) #define SAU_UART_STCLK_MAX (127) #define SAU_UART_STCLK_MIN (2) +#define SAU_UART_PRS_DIVIDER_MAX (0xFU) #if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) @@ -344,8 +345,20 @@ static void r_sau_uart_config_set (sau_uart_instance_ctrl_t * const p_ctrl, uart #endif sau_uart_extended_cfg_t * p_extend_cfg = (sau_uart_extended_cfg_t *) p_cfg->p_extend; +#if (0 == SAU_UART_CFG_FIXED_BAUDRATE_ENABLE) + sau_uart_baudrate_setting_t * p_sau_baud_setting = p_extend_cfg->p_baudrate; + + /* Configure the operation clock divisor based on extended configuration settings */ + uint32_t sps_prs_offset = p_sau_baud_setting->operation_clock * R_SAU0_SPS_PRS1_Pos; + uint32_t sps_prs_mask = R_SAU0_SPS_PRS0_Msk << sps_prs_offset; + SAU_REG->SPS = + (uint16_t) ((SAU_REG->SPS & (~sps_prs_mask)) | + ((uint32_t) p_sau_baud_setting->prs << sps_prs_offset)); +#else + /* Configure the operation clock divisor based on BSP settings */ SAU_REG->SPS = SAU_SPS_REG_INIT; +#endif #if (SAU_UART_CFG_TX_ENABLE) @@ -594,6 +607,8 @@ fsp_err_t R_SAU_UART_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * cons * Implements @ref uart_api_t::baudSet * * @warning This terminates any in-progress transmission. + * @warning This function may change the operation clock frequency. Select a unique operation clock for each SAU + * instance if using this function. * * @retval FSP_SUCCESS Baud rate was successfully changed. * @retval FSP_ERR_ASSERTION Pointer p_ctrl is NULL @@ -635,17 +650,12 @@ fsp_err_t R_SAU_UART_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const SAU_REG->ST = reg_ss; FSP_HARDWARE_REGISTER_WAIT((SAU_REG->SE & reg_ss), 0U); - #if (SAU_UART_CFG_TX_ENABLE) - - /* Update TX operation clock setting. */ - SAU_REG->SMR_b[SAU_TX_INDEX].CKS = p_sau_baud_setting->operation_clock & (R_SAU0_SMR_CKS_Msk >> R_SAU0_SMR_CKS_Pos); - #endif - - #if (SAU_UART_CFG_RX_ENABLE) - - /* Update RX operation clock setting. */ - SAU_REG->SMR_b[SAU_RX_INDEX].CKS = p_sau_baud_setting->operation_clock & (R_SAU0_SMR_CKS_Msk >> R_SAU0_SMR_CKS_Pos); - #endif + /* Configure the operation clock divisor */ + uint32_t sps_prs_offset = p_sau_baud_setting->operation_clock * R_SAU0_SPS_PRS1_Pos; + uint32_t sps_prs_mask = R_SAU0_SPS_PRS0_Msk << sps_prs_offset; + SAU_REG->SPS = + (uint16_t) ((SAU_REG->SPS & (~sps_prs_mask)) | + ((uint32_t) p_sau_baud_setting->prs << sps_prs_offset)); /* Set SDR register value and re-enable. */ reg_ss = 0U; @@ -866,13 +876,6 @@ fsp_err_t R_SAU_UART_ReadStop (uart_ctrl_t * const p_api_ctrl, uint32_t * remain /*******************************************************************************************************************//** * Calculates baud rate register settings (SDR.STCLK) for the specified SAU unit. * - * @note This function calculates the baud settings with both operation clocks CK0 and CK1, then selects the operation - * clock and register setting combination that would produce the lowest error. Call @ref R_SAU_UART_BaudSet to apply - * the updated register settings. - * @note Configure the operation clock frequencies such that all required baud rates can be achieved using at least one - * of the 2 operation clocks. If all required baud rates cannot be achieved with one clock, set one operation clock to - * a lower frequency for slow baud rates, and the second clock to a faster frequency for faster baud rates. - * * @param[in] p_ctrl Pointer to the SAU UART control block. * @param[in] baudrate Baud rate [bps]. For example, 19200, 57600, 115200, etc. * @param[out] p_baud_setting Baud setting information stored here if successful @@ -904,41 +907,33 @@ fsp_err_t R_SAU_UART_BaudCalculate (sau_uart_instance_ctrl_t * const p_ctrl, FSP_PARAMETER_NOT_USED(p_ctrl); #endif - uint32_t best_delta_error = UINT32_MAX; - uint32_t peripheral_clock = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_ICLK); - const uint32_t sps = SAU_SPS_REG_INIT; + uint32_t peripheral_clock = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_ICLK); - /* Calculate settings twice, once for CK0 and once for CK1, selecting the result with the lowest error */ - for (uint8_t prs_shift = 0; prs_shift <= R_SAU0_SPS_PRS1_Pos; prs_shift += R_SAU0_SPS_PRS1_Pos) + /* Calculate the optimal value of STCLK for the given CKn clock. The divisor with the lowest error + * is always the smallest divisor that produces valid STCLK settings. Since we search the divisors + * low to high, the first divisor is the optimal divisor. */ + for (uint8_t prs = 0; prs <= SAU_UART_PRS_DIVIDER_MAX; prs++) { - uint8_t prs = (sps >> prs_shift) & R_SAU0_SPS_PRS0_Msk; - /* To get the stclk divider calculate the divisor to apply to ICLK. There's a built in div/2. */ const uint32_t divisor = baudrate << (prs + 1); /* Calculate stclk register value: STCLK = (f_mck / (2*bitrate)) - 1 */ const uint32_t stclk = (peripheral_clock + (divisor >> 1)) / divisor - 1; - /* Get the actual baudrate given the current settings. - * peripheral_clock / 2^prs / (2 * (stclk + 1)) */ - const uint32_t actual_baudrate = (peripheral_clock >> (prs + 1)) / (stclk + 1); - uint32_t delta_error = baudrate > - actual_baudrate ? baudrate - actual_baudrate : actual_baudrate - baudrate; - - /* Keep settings which are valid and provide the lowest error. */ - if ((SAU_UART_STCLK_MIN <= stclk) && (stclk <= SAU_UART_STCLK_MAX) && - (delta_error < best_delta_error)) + if ((SAU_UART_STCLK_MIN <= stclk) && (stclk <= SAU_UART_STCLK_MAX)) { - best_delta_error = delta_error; + /* Save the settings that provide the lowest error. */ + p_baud_setting->prs = prs; p_baud_setting->stclk = (uint8_t) stclk; - p_baud_setting->operation_clock = (sau_operation_clock_t) (prs_shift == R_SAU0_SPS_PRS1_Pos); + p_baud_setting->operation_clock = + ((sau_uart_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->p_baudrate->operation_clock; + + return FSP_SUCCESS; } } - /* Return an error if no valid STCLK setting was found with either operation clock */ - FSP_ERROR_RETURN(best_delta_error != UINT32_MAX, FSP_ERR_INVALID_ARGUMENT); - - return FSP_SUCCESS; + /* Return an error if no valid STCLK setting was found */ + return FSP_ERR_INVALID_ARGUMENT; #endif } diff --git a/ra/fsp/src/r_sce/aes2/adaptors/hw_sce_ra_private.h b/ra/fsp/src/r_sce/aes2/adaptors/hw_sce_ra_private.h index 986276288..79eb17f02 100644 --- a/ra/fsp/src/r_sce/aes2/adaptors/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/aes2/adaptors/hw_sce_ra_private.h @@ -154,7 +154,7 @@ uint32_t change_endian_long(uint32_t data); void hw_aes_set_key(uint8_t * key, uint32_t KeyLen); void hw_aes_set_iv(uint8_t * initialize_vetor); -void hw_aes_start(uint8_t * input, uint8_t * output, uint32_t block); +fsp_err_t hw_aes_start(uint8_t * input, uint8_t * output, uint32_t block); void hw_aes_ccm_mode_start(uint8_t * input, uint8_t * output, uint32_t block); fsp_err_t hw_gcm_calculation(uint8_t * input, uint8_t * output, diff --git a/ra/fsp/src/r_sce/aes2/adaptors/r_sce_AES_adapt.c b/ra/fsp/src/r_sce/aes2/adaptors/r_sce_AES_adapt.c index f44dfcdb5..9f52380a6 100644 --- a/ra/fsp/src/r_sce/aes2/adaptors/r_sce_AES_adapt.c +++ b/ra/fsp/src/r_sce/aes2/adaptors/r_sce_AES_adapt.c @@ -19,10 +19,13 @@ * Refer to Table 1.3 Numbers of Clock Cycles Required for Processing in the CCM Mode * Waiting time for 91 Clock Cycles Required for Processing in the CCM Mode with PCLKB 32MHz * Note: waiting for 91 clock cycles is still not enough for encryption of AES-CCM 256 bits key length. - * Must be to 120 clock cycles. + * Must be to 146 clock cycles. * */ -#define HW_SCE_AES_CCM_WAITING_CYCLES (120U) -#define HW_SCE_FREQUENCY_IN_HZ (1000000U) + +#define HW_SCE_AES_CCM_WAITING_CYCLES (146U) +#define HW_SCE_FREQUENCY_IN_HZ (1000000U) +#define HW_SCE_AES2_MAX_WAIT_USECONDS (0xFFFFFFFF) // Set the maximum value for uint32_t +#define HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS 10 // Set a 10 microsecond status check interval /*********************************************************************************************************************** * Typedef definitions @@ -65,8 +68,8 @@ extern void hw_aes_ccm_decrypt_init(uint32_t indata_cmd); * Private global variables and functions ***********************************************************************************************************************/ -static uint8_t InputData_DataA[SIZE_AES_GCM_IN_DATA_AAD_LEN_BYTES] = {0}; -static uint8_t InputData_IV_GCM[SIZE_AES_GCM_IN_DATA_IV_GCM_LEN_BYTES] = {0}; +static uint8_t __attribute__((aligned(32))) InputData_DataA[SIZE_AES_GCM_IN_DATA_AAD_LEN_BYTES] = {0}; +static uint8_t __attribute__((aligned(32))) InputData_IV_GCM[SIZE_AES_GCM_IN_DATA_IV_GCM_LEN_BYTES] = {0}; static uint8_t InputData_IV_GCM_LEN_BYTES = 0; uint32_t change_endian_long (uint32_t a) @@ -175,11 +178,12 @@ static void hw_aes_get_ciphertext (uint8_t * output) *(ptr + 7) = R_AES_B->AESODAT0.AESODATL; } -void hw_aes_start (uint8_t * input, uint8_t * output, uint32_t block) +fsp_err_t hw_aes_start (uint8_t * input, uint8_t * output, uint32_t block) { uint8_t * ptr; uint8_t * ptr_out; - uint32_t block_ctr = 0; + uint32_t block_ctr = 0; + uint32_t wait_count_useconds = HW_SCE_AES2_MAX_WAIT_USECONDS; ptr = input; ptr_out = output; @@ -189,9 +193,15 @@ void hw_aes_start (uint8_t * input, uint8_t * output, uint32_t block) hw_aes_set_plaintext(ptr); R_AES_B->AESDCNTL |= R_AES_AESDCNTL_CALCULATE_START; - while ((R_AES_B->AESSTSL & R_AES_AESSTSL_BIT_5) != 0) + while (((R_AES_B->AESSTSL & R_AES_AESSTSL_BIT_5) != 0) && (wait_count_useconds > 0U)) { - ; + R_BSP_SoftwareDelay(HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS, BSP_DELAY_UNITS_MICROSECONDS); + wait_count_useconds -= HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS; + } + + if (0 == wait_count_useconds) + { + return FSP_ERR_TIMEOUT; } if ((R_AES_B->AESSTSL & R_AES_AESSTSL_CALCULATE_COMPLETED) != 0) @@ -205,6 +215,8 @@ void hw_aes_start (uint8_t * input, uint8_t * output, uint32_t block) ptr_out += 16; block_ctr++; } while (block_ctr < block); + + return FSP_SUCCESS; } /*********************************************************************************************************************** @@ -220,18 +232,23 @@ void hw_aes_start (uint8_t * input, uint8_t * output, uint32_t block) void hw_aes_ccm_mode_start (uint8_t * input, uint8_t * output, uint32_t block) { uint32_t block_ctr; - uint32_t system_clock_freq_mhz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB) / HW_SCE_FREQUENCY_IN_HZ; + uint32_t pclkb_mhz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB) / HW_SCE_FREQUENCY_IN_HZ; + uint32_t iclk_mhz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_ICLK) / HW_SCE_FREQUENCY_IN_HZ; + uint8_t ratio = 0U; - /* Round up the frequency to a whole number */ - uint32_t delay_us = (HW_SCE_AES_CCM_WAITING_CYCLES + system_clock_freq_mhz - 1) / system_clock_freq_mhz; + while (iclk_mhz > pclkb_mhz) + { + iclk_mhz = iclk_mhz >> 1U; + ratio++; + } - for (block_ctr = 0; block_ctr < block; block_ctr++) + for (block_ctr = 0U; block_ctr < block; block_ctr++) { if (NULL != input) { hw_aes_set_plaintext(input); R_AES_B->AESDCNTL |= R_AES_AESDCNTL_CALCULATE_START; - R_BSP_SoftwareDelay(delay_us, BSP_DELAY_UNITS_MICROSECONDS); + bsp_prv_software_delay_loop(BSP_DELAY_LOOPS_CALCULATE(HW_SCE_AES_CCM_WAITING_CYCLES << ratio)); } if (NULL != output) @@ -329,9 +346,17 @@ void HW_SCE_Aes192EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_ fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub (void) { - while ((R_AES_B->AESSTSL & R_AES_AESSTSL_BIT_5) != 0) + uint32_t wait_count_useconds = HW_SCE_AES2_MAX_WAIT_USECONDS; + + while (((R_AES_B->AESSTSL & R_AES_AESSTSL_BIT_5) != 0) && (wait_count_useconds > 0U)) + { + R_BSP_SoftwareDelay(HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS, BSP_DELAY_UNITS_MICROSECONDS); + wait_count_useconds -= HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS; + } + + if (0 == wait_count_useconds) { - ; + return FSP_ERR_TIMEOUT; } if ((R_AES_B->AESSTSL & R_AES_AESSTSL_CALCULATE_COMPLETED) != 0) @@ -409,9 +434,17 @@ void HW_SCE_Aes128EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_ fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub (void) { - while ((R_AES_B->AESSTSL & R_AES_AESSTSL_BIT_5) != 0) + uint32_t wait_count_useconds = HW_SCE_AES2_MAX_WAIT_USECONDS; + + while (((R_AES_B->AESSTSL & R_AES_AESSTSL_BIT_5) != 0) && (wait_count_useconds > 0U)) + { + R_BSP_SoftwareDelay(HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS, BSP_DELAY_UNITS_MICROSECONDS); + wait_count_useconds -= HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS; + } + + if (0 == wait_count_useconds) { - ; + return FSP_ERR_TIMEOUT; } if ((R_AES_B->AESSTSL & R_AES_AESSTSL_CALCULATE_COMPLETED) != 0) @@ -489,9 +522,17 @@ void HW_SCE_Aes256EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_ fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub (void) { - while ((R_AES_B->AESSTSL & R_AES_AESSTSL_BIT_5) != 0) + uint32_t wait_count_useconds = HW_SCE_AES2_MAX_WAIT_USECONDS; + + while (((R_AES_B->AESSTSL & R_AES_AESSTSL_BIT_5) != 0) && (wait_count_useconds > 0U)) + { + R_BSP_SoftwareDelay(HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS, BSP_DELAY_UNITS_MICROSECONDS); + wait_count_useconds -= HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS; + } + + if (0 == wait_count_useconds) { - ; + return FSP_ERR_TIMEOUT; } if ((R_AES_B->AESSTSL & R_AES_AESSTSL_CALCULATE_COMPLETED) != 0) diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/adaptors/r_sce_adapt.c index 7f9e589ca..d28ae8be5 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/adaptors/r_sce_adapt.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/adaptors/r_sce_adapt.c @@ -405,6 +405,18 @@ fsp_err_t HW_SCE_Ecc521ScalarMultiplicationSubAdaptor(const uint32_t InData_Curv return (HW_SCE_Ecc521ScalarMultiplicationSub(InData_KeyIndex, InData_PubKey, InData_DomainParam, OutData_R)); } +fsp_err_t HW_SCE_EccEd25519ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_PubKey[], + const uint32_t InData_DomainParam[], + uint32_t OutData_R[]) +{ + FSP_PARAMETER_NOT_USED(InData_CurveType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + return (HW_SCE_Ed25519ScalarMultiplicationSub(InData_KeyIndex, InData_PubKey, InData_DomainParam, OutData_R)); +} + fsp_err_t HW_SCE_EcdsaSignatureGenerateSubAdaptor(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/hw_sce_ra_private.h index 43cc177d9..c0a2c0d27 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/hw_sce_ra_private.h @@ -333,6 +333,7 @@ fsp_err_t HW_SCE_EcdsaP384SignatureVerificationSubAdaptor(const uint32_t InData_ fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSub(const uint32_t InData_CurveType[], const uint32_t InData_KeyIndex[], const uint32_t InData_PubKey[], const uint32_t InData_DomainParam[], uint32_t OutData_R[]); fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_PubKey[], const uint32_t InData_DomainParam[], uint32_t OutData_R[]); fsp_err_t HW_SCE_Ecc521ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_PubKey[], const uint32_t InData_DomainParam[], uint32_t OutData_R[]); +fsp_err_t HW_SCE_EccEd25519ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_PubKey[], const uint32_t InData_DomainParam[], uint32_t OutData_R[]); fsp_err_t HW_SCE_EcdsaP512SignatureGenerateSub(const uint32_t InData_KeyIndex[], const uint32_t InData_MsgDgst[], const uint32_t InData_DomainParam[], uint32_t OutData_Signature[]); fsp_err_t HW_SCE_EcdsaP512SignatureVerificationSub(const uint32_t InData_KeyIndex[], const uint32_t InData_MsgDgst[], const uint32_t InData_Signature[], const uint32_t InData_DomainParam[]); fsp_err_t HW_SCE_Ecc512ScalarMultiplicationSub(const uint32_t InData_KeyIndex[], const uint32_t InData_PubKey[], const uint32_t InData_DomainParam[], uint32_t OutData_R[]); diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/public/inc/r_sce_if.h b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/public/inc/r_sce_if.h index c681a6f75..06de493bc 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/public/inc/r_sce_if.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/public/inc/r_sce_if.h @@ -692,6 +692,22 @@ typedef struct sce_ecc521_public_key_index } plain_value; } sce_ecc521_public_key_index_t; +/* ECC ED-25519 public key index data structure */ +typedef struct sce_ecc25519_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_q[HW_SCE_ECC_ED25519_PUBLIC_KEY_BYTE_SIZE]; + uint32_t key_management_info2[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; + struct + { + uint8_t key[HW_SCE_ECC_ED25519_PUBLIC_KEY_BYTE_SIZE]; + } plain_value; +} sce_ecc25519_public_key_index_t; + /* ECC P-192/224/256 private key index data structure */ typedef struct sce_ecc_private_key_index { diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/public/inc/r_sce_if.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/public/inc/r_sce_if.h index 8f4a22151..178a18d65 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/public/inc/r_sce_if.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/public/inc/r_sce_if.h @@ -593,29 +593,29 @@ typedef struct sce_rsa4096_private_key_index /* RSA 1024bit key index pair structure */ typedef struct sce_rsa1024_key_pair_index { - sce_rsa1024_private_key_index_t private; - sce_rsa1024_public_key_index_t public; + sce_rsa1024_private_key_index_t priv_key; + sce_rsa1024_public_key_index_t pub_key; } sce_rsa1024_key_pair_index_t; /* RSA 2048bit key index pair structure */ typedef struct sce_rsa2048_key_pair_index { - sce_rsa2048_private_key_index_t private; - sce_rsa2048_public_key_index_t public; + sce_rsa2048_private_key_index_t priv_key; + sce_rsa2048_public_key_index_t pub_key; } sce_rsa2048_key_pair_index_t; /* RSA 3072bit key index pair structure */ typedef struct sce_rsa3072_key_pair_index { - sce_rsa3072_private_key_index_t private; - sce_rsa3072_public_key_index_t public; + sce_rsa3072_private_key_index_t priv_key; + sce_rsa3072_public_key_index_t pub_key; } sce_rsa3072_key_pair_index_t; /* RSA 4096bit key index pair structure */ typedef struct sce_rsa4096_key_pair_index { - sce_rsa4096_private_key_index_t private; - sce_rsa4096_public_key_index_t public; + sce_rsa4096_private_key_index_t priv_key; + sce_rsa4096_public_key_index_t pub_key; } sce_rsa4096_key_pair_index_t; /* ECC P-192/224/256 public key index data structure */ @@ -640,8 +640,8 @@ typedef struct sce_ecc_private_key_index /* ECC key index pair structure */ typedef struct sce_ecc_key_pair_index { - sce_ecc_private_key_index_t private; - sce_ecc_public_key_index_t public; + sce_ecc_private_key_index_t priv_key; + sce_ecc_public_key_index_t pub_key; } sce_ecc_key_pair_index_t; /* ECDH key index data structure */ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c index 23af46e3d..efd859891 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c @@ -540,6 +540,22 @@ fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSubAdaptor(const uint32_t InData_Curv return (HW_SCE_Ecc384ScalarMultiplicationSub(InData_CurveType, InData_KeyIndex, InData_PubKey, OutData_R)); } +fsp_err_t HW_SCE_EccEd25519ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_PubKey[], + const uint32_t InData_DomainParam[], + uint32_t OutData_R[]) +{ + FSP_PARAMETER_NOT_USED(InData_CurveType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_PubKey); + FSP_PARAMETER_NOT_USED(InData_DomainParam); + FSP_PARAMETER_NOT_USED(OutData_R); + return FSP_ERR_UNSUPPORTED; +} + fsp_err_t HW_SCE_EcdsaSignatureGenerateSubAdaptor(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h index c8d38a818..1129cfd46 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h @@ -353,6 +353,7 @@ fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_PubKey, uint32_t *OutData_R); fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_PubKey[], const uint32_t InData_DomainParam[], uint32_t OutData_R[]); +fsp_err_t HW_SCE_EccEd25519ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_PubKey[], const uint32_t InData_DomainParam[], uint32_t OutData_R[]); fsp_err_t HW_SCE_TdesEcbEncryptInitPrivate(sce_tdes_key_index_t *key_index); fsp_err_t HW_SCE_TdesEcbEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c index a33f621f5..e27a92138 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c @@ -460,6 +460,22 @@ fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSubAdaptor(const uint32_t InData_Curv return (HW_SCE_Ecc384ScalarMultiplicationSub(InData_CurveType, InData_KeyIndex, InData_PubKey, OutData_R)); } +fsp_err_t HW_SCE_EccEd25519ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_PubKey[], + const uint32_t InData_DomainParam[], + uint32_t OutData_R[]) +{ + FSP_PARAMETER_NOT_USED(InData_CurveType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_PubKey); + FSP_PARAMETER_NOT_USED(InData_DomainParam); + FSP_PARAMETER_NOT_USED(OutData_R); + return FSP_ERR_UNSUPPORTED; +} + fsp_err_t HW_SCE_EcdsaSignatureGenerateSubAdaptor(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h index 2ab2261c9..c26af607c 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h @@ -362,6 +362,7 @@ fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_PubKey, uint32_t *OutData_R); fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_PubKey[], const uint32_t InData_DomainParam[], uint32_t OutData_R[]); +fsp_err_t HW_SCE_EccEd25519ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_PubKey[], const uint32_t InData_DomainParam[], uint32_t OutData_R[]); fsp_err_t HW_SCE_TdesEcbEncryptInitPrivate(sce_tdes_key_index_t *key_index); fsp_err_t HW_SCE_TdesEcbEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); fsp_err_t HW_SCE_TdesEcbEncryptFinalPrivate(void); diff --git a/ra/fsp/src/r_sce/hw_sce_aes_private.h b/ra/fsp/src/r_sce/hw_sce_aes_private.h index d07e35d68..33a606902 100644 --- a/ra/fsp/src/r_sce/hw_sce_aes_private.h +++ b/ra/fsp/src/r_sce/hw_sce_aes_private.h @@ -23,8 +23,8 @@ #define SIZE_AES_256BIT_KEYLEN_BYTES ((SIZE_AES_256BIT_KEYLEN_BITS) / 8) #define SIZE_AES_256BIT_KEYLEN_WORDS ((SIZE_AES_256BIT_KEYLEN_BITS) / 32) -#define SIZE_AES_BLOCK_BITS (128) -#define SIZE_AES_BLOCK_BYTES (128 / 8) +#define SIZE_AES_BLOCK_BITS (128U) +#define SIZE_AES_BLOCK_BYTES ((SIZE_AES_BLOCK_BITS) / 8) #define SIZE_AES_BLOCK_WORDS ((SIZE_AES_BLOCK_BITS) / 32) #define SCE_AES_IN_DATA_CMD_ECB_ENCRYPTION (0x00000000U) diff --git a/ra/fsp/src/r_sce/hw_sce_ecc_private.h b/ra/fsp/src/r_sce/hw_sce_ecc_private.h index 3d96e2d23..820072505 100644 --- a/ra/fsp/src/r_sce/hw_sce_ecc_private.h +++ b/ra/fsp/src/r_sce/hw_sce_ecc_private.h @@ -46,6 +46,10 @@ #define ECC_521_PRIVATE_KEY_LENGTH_BITS (521U) #define ECC_521_PRIVATE_KEY_LENGTH_WORDS (20U) +/* ECC ED-25519 */ +#define ECC_25519_PRIVATE_KEY_LENGTH_BITS (256U) +#define ECC_25519_PRIVATE_KEY_LENGTH_WORDS (8U) + /* SCE based wrapped keys are at most 20/32 bytes larger than corresponding plain private keys */ #define HW_SCE_ECC_WRAPPED_KEY_ADJUST(x) ((x) + ((HW_SCE_PRIVATE_KEY_WRAPPING_WORD_SIZE) * 4)) @@ -168,6 +172,7 @@ fsp_err_t HW_SCE_ECC_384WrappedScalarMultiplication(const uint32_t * InData_Curv const uint32_t * InData_P, const uint32_t * Domain_Param, uint32_t * OutData_R); + #if BSP_FEATURE_CRYPTO_HAS_RSIP7 fsp_err_t HW_SCE_ECC_521GenerateSign(const uint32_t * InData_CurveType, const uint32_t * InData_G, @@ -189,15 +194,37 @@ fsp_err_t HW_SCE_ECC_521HrkGenerateSign(const uint32_t * InData_DomainParam, const uint32_t * InData_MsgDgst, uint32_t * OutData_R, uint32_t * OutData_S); - + fsp_err_t HW_SCE_ECC_521WrappedScalarMultiplication(const uint32_t * InData_CurveType, const uint32_t * InData_Cmd, const uint32_t * InData_KeyIndex, const uint32_t * InData_P, const uint32_t * Domain_Param, uint32_t * OutData_R); + +fsp_err_t HW_SCE_ECC_255GenerateSign(const uint32_t * InData_CurveType, + const uint32_t * InData_G, + const uint32_t * InData_PrivKey, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S); + +fsp_err_t HW_SCE_ECC_255HrkGenerateSign(const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S); + #endif +fsp_err_t HW_SCE_ECC_ED25519WrappedScalarMultiplication(const uint32_t * InData_CurveType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_P, + const uint32_t * Domain_Param, + uint32_t * OutData_R); + /* ECC - 224 HW Procedure definitions */ fsp_err_t HW_SCE_ECC_224GenerateSign(const uint32_t * InData_DomainParam, const uint32_t * InData_G, diff --git a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api/r_sce_api.h b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api/r_sce_api.h index 9e1a43e69..af5d64906 100644 --- a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api/r_sce_api.h +++ b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api/r_sce_api.h @@ -190,19 +190,6 @@ FSP_HEADER * Typedef definitions **********************************************************************************************************************/ -/** Data lifecycle */ -typedef enum -{ - SCE_CM = 1, - SCE_SSD, - SCE_NSECSD, - SCE_DPL, - SCE_LCK_DBG, - SCE_LCK_BOOT, - SCE_RMA_REQ, - SCE_RMA_ACK, -} lifecycle_t; - /** Byte data structure */ typedef struct sce_byte_data { @@ -479,7 +466,7 @@ typedef void sce_ctrl_t; /** User configuration structure, used in open function */ typedef struct st_sce_cfg { - lifecycle_t lifecycle; ///< Data lifecycle + /* No structure members */ } sce_cfg_t; /** Functions implemented at the HAL layer will follow this API. */ diff --git a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/r_sce_private.h b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/r_sce_private.h index 27ada9b5c..ef8ca8b6f 100644 --- a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/r_sce_private.h +++ b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/r_sce_private.h @@ -52,11 +52,10 @@ extern const uint32_t sce_oem_key_size[SCE_OEM_CMD_NUM]; fsp_err_t R_SCE_SelfCheck1Private(void); fsp_err_t R_SCE_SelfCheck2Private(void); fsp_err_t R_SCE_SelfCheck3Private(void); -fsp_err_t R_SCE_LoadHukPrivate(lifecycle_t lifecycle); +fsp_err_t R_SCE_LoadHukPrivate(void); fsp_err_t R_SCE_FwIntegrityCheckPrivate(void); -fsp_err_t R_SCE_UpdateOemKeyIndexPrivate(lifecycle_t lifecycle, - sce_oem_cmd_t key_type, +fsp_err_t R_SCE_UpdateOemKeyIndexPrivate(sce_oem_cmd_t key_type, uint8_t * iv, uint8_t * encrypted_oem_key, uint32_t * key_index); diff --git a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce.c b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce.c index e0ed8491c..e2367dfe4 100644 --- a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce.c +++ b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce.c @@ -25,7 +25,6 @@ /*********************************************************************************************************************** * Private global variables **********************************************************************************************************************/ -static lifecycle_t gs_lifecycle; /*********************************************************************************************************************** * Global variables @@ -272,7 +271,7 @@ fsp_err_t R_SCE_Open (sce_ctrl_t * const p_ctrl, sce_cfg_t const * const p_cfg) sce_instance_ctrl_t * p_instance_ctrl = (sce_instance_ctrl_t *) p_ctrl; p_instance_ctrl->open = 1; - gs_lifecycle = p_cfg->lifecycle; + FSP_PARAMETER_NOT_USED(p_cfg); R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); @@ -290,7 +289,7 @@ fsp_err_t R_SCE_Open (sce_ctrl_t * const p_ctrl, sce_cfg_t const * const p_cfg) if (FSP_SUCCESS == error_code) { - error_code = R_SCE_LoadHukPrivate(p_cfg->lifecycle); + error_code = R_SCE_LoadHukPrivate(); } if (FSP_SUCCESS == error_code) @@ -484,13 +483,11 @@ fsp_err_t R_SCE_AES128_EncryptedKeyWrap (uint8_t * initial_vector, sce_aes_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_AES128; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -529,13 +526,11 @@ fsp_err_t R_SCE_AES256_EncryptedKeyWrap (uint8_t * initial_vector, sce_aes_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_AES256; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -694,13 +689,11 @@ fsp_err_t R_SCE_SHA256HMAC_EncryptedKeyWrap (uint8_t * initia sce_hmac_sha_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_HMAC_SHA256; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -815,13 +808,11 @@ fsp_err_t R_SCE_RSA1024_EncryptedPublicKeyWrap (uint8_t sce_rsa1024_public_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_RSA1024_PUBLIC; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -860,13 +851,11 @@ fsp_err_t R_SCE_RSA1024_EncryptedPrivateKeyWrap (uint8_t sce_rsa1024_private_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_RSA1024_PRIVATE; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -905,13 +894,11 @@ fsp_err_t R_SCE_RSA2048_EncryptedPublicKeyWrap (uint8_t sce_rsa2048_public_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_RSA2048_PUBLIC; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -950,13 +937,11 @@ fsp_err_t R_SCE_RSA2048_EncryptedPrivateKeyWrap (uint8_t sce_rsa2048_private_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_RSA2048_PRIVATE; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -995,13 +980,11 @@ fsp_err_t R_SCE_RSA3072_EncryptedPublicKeyWrap (uint8_t sce_rsa3072_public_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_RSA3072_PUBLIC; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -1040,13 +1023,11 @@ fsp_err_t R_SCE_RSA4096_EncryptedPublicKeyWrap (uint8_t sce_rsa4096_public_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_RSA4096_PUBLIC; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -1259,13 +1240,11 @@ fsp_err_t R_SCE_ECC_secp192r1_EncryptedPublicKeyWrap (uint8_t sce_ecc_public_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P192_PUBLIC; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -1304,13 +1283,11 @@ fsp_err_t R_SCE_ECC_secp224r1_EncryptedPublicKeyWrap (uint8_t sce_ecc_public_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P224_PUBLIC; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -1349,13 +1326,11 @@ fsp_err_t R_SCE_ECC_secp256r1_EncryptedPublicKeyWrap (uint8_t sce_ecc_public_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P256_PUBLIC; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -1394,13 +1369,11 @@ fsp_err_t R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap (uint8_t sce_ecc_public_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P384_PUBLIC; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -1439,13 +1412,11 @@ fsp_err_t R_SCE_ECC_secp192r1_EncryptedPrivateKeyWrap (uint8_t sce_ecc_private_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P192_PRIVATE; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -1484,13 +1455,11 @@ fsp_err_t R_SCE_ECC_secp224r1_EncryptedPrivateKeyWrap (uint8_t sce_ecc_private_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P224_PRIVATE; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -1529,13 +1498,11 @@ fsp_err_t R_SCE_ECC_secp256r1_EncryptedPrivateKeyWrap (uint8_t sce_ecc_private_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P256_PRIVATE; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -1574,13 +1541,11 @@ fsp_err_t R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap (uint8_t sce_ecc_private_wrapped_key_t * wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; - lifecycle_t lifecycle = gs_lifecycle; sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P384_PRIVATE; memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); - error_code = R_SCE_UpdateOemKeyIndexPrivate(lifecycle, - key_type, + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, initial_vector, encrypted_key, (uint32_t *) &wrapped_key->value); @@ -1680,10 +1645,10 @@ fsp_err_t R_SCE_TLS_ECC_secp256r1_EphemeralWrappedKeyPairGenerate(sce_tls_p256_e * @retval FSP_ERR_CRYPTO_SCE_FAIL self-test1 fail * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict **********************************************************************************************************************/ -fsp_err_t R_SCE_LoadHukPrivate (lifecycle_t lifecycle) +fsp_err_t R_SCE_LoadHukPrivate (void) { uint32_t LC[1]; - LC[0] = lifecycle; + LC[0] = R_PSCU->DLMMON; return R_SCE_LoadHukSub(LC); } @@ -1742,8 +1707,7 @@ fsp_err_t R_SCE_FwIntegrityCheckPrivate (void) * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT * @retval FSP_ERR_CRYPTO_SCE_FAIL **********************************************************************************************************************/ -fsp_err_t R_SCE_UpdateOemKeyIndexPrivate (lifecycle_t lifecycle, - sce_oem_cmd_t key_type, +fsp_err_t R_SCE_UpdateOemKeyIndexPrivate (sce_oem_cmd_t key_type, uint8_t * iv, uint8_t * encrypted_oem_key, uint32_t * key_index) @@ -1752,7 +1716,7 @@ fsp_err_t R_SCE_UpdateOemKeyIndexPrivate (lifecycle_t lifecycle, uint32_t CMD[1] = {0}; uint32_t LC[1] = {0}; CMD[0] = key_type; - LC[0] = lifecycle; + LC[0] = R_PSCU->DLMMON; INST_DATA_SIZE = sce_oem_key_size[key_type]; diff --git a/ra/fsp/src/r_sci_b_lin/r_sci_b_lin.c b/ra/fsp/src/r_sci_b_lin/r_sci_b_lin.c index 09a6bd288..e9e2cb7e6 100644 --- a/ra/fsp/src/r_sci_b_lin/r_sci_b_lin.c +++ b/ra/fsp/src/r_sci_b_lin/r_sci_b_lin.c @@ -379,7 +379,7 @@ fsp_err_t R_SCI_B_LIN_StartFrameWrite (lin_ctrl_t * const p_api_ctrl, uint8_t co /*******************************************************************************************************************//** * Begins non-blocking transmission of a LIN information frame. * - * On successful information frame reception, the callback is called with event + * On successful information frame transmission, the callback is called with event * @ref lin_event_t::LIN_EVENT_TX_INFORMATION_FRAME_COMPLETE. * * Implements @ref lin_api_t::informationFrameWrite. @@ -1988,7 +1988,10 @@ void sci_b_lin_tei_isr (void) #endif /* Call user callback */ - r_sci_b_lin_call_callback(p_ctrl, p_ctrl->event); + if (p_ctrl->event) + { + r_sci_b_lin_call_callback(p_ctrl, p_ctrl->event); + } /* Clear pending IRQ to make sure it doesn't fire again after exiting */ R_BSP_IrqStatusClear(irq); @@ -2024,6 +2027,7 @@ void sci_b_lin_eri_isr (void) p_ctrl->rx_bytes_received = 0; p_ctrl->tx_src_bytes = 0; p_ctrl->p_information = NULL; + p_ctrl->event = LIN_EVENT_NONE; /* Clear pending IRQ to make sure it doesn't fire again after exiting */ R_BSP_IrqStatusClear(irq); diff --git a/ra/fsp/src/r_sci_uart/r_sci_uart.c b/ra/fsp/src/r_sci_uart/r_sci_uart.c index 5a8265e40..59b46efb4 100644 --- a/ra/fsp/src/r_sci_uart/r_sci_uart.c +++ b/ra/fsp/src/r_sci_uart/r_sci_uart.c @@ -734,7 +734,8 @@ fsp_err_t R_SCI_UART_CallbackSet (uart_ctrl_t * const p_api_ctrl, * @retval FSP_SUCCESS Baud rate was successfully changed. * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL or the UART is not configured to use the * internal clock. - * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED A restricted channel is selected. **********************************************************************************************************************/ fsp_err_t R_SCI_UART_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting) { @@ -743,7 +744,8 @@ fsp_err_t R_SCI_UART_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) FSP_ASSERT(p_ctrl); FSP_ERROR_RETURN(SCI_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); - + /* Verify that the selected channel is not among the restricted channels when ABCSE is 1. Refer "Limitations" section of r_sci_uart module in FSP User Manual */ + FSP_ERROR_RETURN(!((BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS & (1 << p_ctrl->p_cfg->channel)) && (((baud_setting_t*)p_baud_setting)->semr_baudrate_bits_b.abcse)),FSP_ERR_UNSUPPORTED); /* Verify that the On-Chip baud rate generator is currently selected. */ FSP_ASSERT((p_ctrl->p_reg->SCR_b.CKE & 0x2) == 0U); #endif @@ -950,6 +952,7 @@ fsp_err_t R_SCI_UART_ReadStop (uart_ctrl_t * const p_api_ctrl, uint32_t * remain /*******************************************************************************************************************//** * Calculates baud rate register settings. Evaluates and determines the best possible settings set to the baud rate * related registers. + * @note For limitations of this API, refer to the 'Limitations' section of r_sci_uart module in FSP User Manual. * * @param[in] baudrate Baud rate [bps]. For example, 19200, 57600, 115200, etc. * @param[in] bitrate_modulation Enable bitrate modulation diff --git a/ra/fsp/src/r_tau_pwm/r_tau_pwm.c b/ra/fsp/src/r_tau_pwm/r_tau_pwm.c index b4072086f..9b3245c4d 100644 --- a/ra/fsp/src/r_tau_pwm/r_tau_pwm.c +++ b/ra/fsp/src/r_tau_pwm/r_tau_pwm.c @@ -25,6 +25,13 @@ #define TAU_PWM_PRV_PERIOD_MAX (0x10001U) #define TAU_PWM_PRV_PERIOD_MIN (0x00002U) +/* Shifted mask for TPS0.PRS2 and .PRS3 bitfields */ +#define TAU_PRV_PRS2_PRS3_MASK (0x3U) + +/* Divisor settings for CK02 and CK03 */ +#define TAU_PRV_TPS0_PRS3_SETTING ((BSP_CFG_TAU_CK03 >> 1) & TAU_PRV_PRS2_PRS3_MASK) +#define TAU_PRV_TPS0_PRS2_SETTING ((BSP_CFG_TAU_CK02 >> 1) & TAU_PRV_PRS2_PRS3_MASK) + /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ @@ -70,7 +77,7 @@ const timer_api_t g_timer_on_tau_pwm = .start = R_TAU_PWM_Start, .reset = R_TAU_PWM_Reset, .enable = R_TAU_PWM_Enable, - .disable = R_TAU_PWM_Disable, + .disable = R_TAU_PWM_Stop, .periodSet = R_TAU_PWM_PeriodSet, .compareMatchSet = R_TAU_PWM_CompareMatchSet, .dutyCycleSet = R_TAU_PWM_DutyCycleSet, @@ -125,7 +132,9 @@ fsp_err_t R_TAU_PWM_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const r_tau_pwm_hardware_initialize(p_instance_ctrl, p_cfg); +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE p_instance_ctrl->open = TAU_PWM_OPEN; +#endif return err; } @@ -139,20 +148,14 @@ fsp_err_t R_TAU_PWM_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const * @retval FSP_SUCCESS Timer successfully stopped. * @retval FSP_ERR_ASSERTION p_ctrl was NULL. * @retval FSP_ERR_NOT_OPEN The instance is not opened. - * @retval FSP_ERR_INVALID_MODE The mode is invalid, only called in TIMER_MODE_PWM mode. - * @retval FSP_ERR_UNSUPPORTED Unsupported when pwm mode support is disabled **********************************************************************************************************************/ fsp_err_t R_TAU_PWM_Stop (timer_ctrl_t * const p_ctrl) { -#if TAU_PWM_CFG_PWM_MODE_ENABLE tau_pwm_instance_ctrl_t * p_instance_ctrl = (tau_pwm_instance_ctrl_t *) p_ctrl; - #if TAU_PWM_CFG_PARAM_CHECKING_ENABLE +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_instance_ctrl); FSP_ERROR_RETURN(TAU_PWM_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); - - /* Only called in pwm mode */ - FSP_ERROR_RETURN(TIMER_MODE_PWM == p_instance_ctrl->p_cfg->mode, FSP_ERR_INVALID_MODE); - #endif +#endif /* Stop timer */ R_TAU->TT0 = p_instance_ctrl->channels_mask; @@ -161,10 +164,6 @@ fsp_err_t R_TAU_PWM_Stop (timer_ctrl_t * const p_ctrl) R_TAU->TOE0 &= (uint16_t) ~(p_instance_ctrl->slave_channels_mask); return FSP_SUCCESS; -#else - FSP_PARAMETER_NOT_USED(p_ctrl); - FSP_RETURN(FSP_ERR_UNSUPPORTED); -#endif } /*******************************************************************************************************************//** @@ -172,7 +171,7 @@ fsp_err_t R_TAU_PWM_Stop (timer_ctrl_t * const p_ctrl) * Implements @ref timer_api_t::start. * * @note In one-shot mode, this function is supported only after the timer has been placed into the start trigger - * detection wait state by calling @ref R_TAU_PWM_Enable. + * detection wait state by calling @ref timer_api_t::enable * * Example: * @snippet r_tau_pwm_example.c R_TAU_PWM_Start @@ -188,11 +187,12 @@ fsp_err_t R_TAU_PWM_Start (timer_ctrl_t * const p_ctrl) #if TAU_PWM_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_instance_ctrl); FSP_ERROR_RETURN(TAU_PWM_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #if TAU_PWM_CFG_ONE_SHOT_MODE_ENABLE if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) { /* Get the channel status */ - bool channel_in_use = (R_TAU->TE0_b.TE >> p_instance_ctrl->p_cfg->channel) & 1U; + bool channel_in_use = R_TAU->TE0 & (1U << p_instance_ctrl->p_cfg->channel); FSP_ERROR_RETURN(channel_in_use, FSP_ERR_NOT_ENABLED); } #endif @@ -245,7 +245,7 @@ fsp_err_t R_TAU_PWM_Reset (timer_ctrl_t * const p_ctrl) #endif /* Get the channel status */ - bool channel_in_use = (R_TAU->TE0_b.TE >> p_instance_ctrl->p_cfg->channel) & 1U; + bool channel_in_use = R_TAU->TE0 & (1U << p_instance_ctrl->p_cfg->channel); if (channel_in_use) { /* Stop timer */ @@ -297,43 +297,6 @@ fsp_err_t R_TAU_PWM_Enable (timer_ctrl_t * const p_ctrl) #endif } -/*******************************************************************************************************************//** - * Stops timer and disables external event inputs and software trigger. Implements @ref timer_api_t::disable. - * - * Example: - * @snippet r_tau_pwm_example.c R_TAU_PWM_Disable - * - * @retval FSP_SUCCESS External events successfully disabled. - * @retval FSP_ERR_ASSERTION p_ctrl was NULL. - * @retval FSP_ERR_NOT_OPEN The instance is not opened. - * @retval FSP_ERR_INVALID_MODE The mode is invalid, only called in TIMER_MODE_ONE_SHOT mode. - * @retval FSP_ERR_UNSUPPORTED Unsupported when one shot mode support is disabled - **********************************************************************************************************************/ -fsp_err_t R_TAU_PWM_Disable (timer_ctrl_t * const p_ctrl) -{ -#if TAU_PWM_CFG_ONE_SHOT_MODE_ENABLE - tau_pwm_instance_ctrl_t * p_instance_ctrl = (tau_pwm_instance_ctrl_t *) p_ctrl; - #if TAU_PWM_CFG_PARAM_CHECKING_ENABLE - FSP_ASSERT(NULL != p_instance_ctrl); - FSP_ERROR_RETURN(TAU_PWM_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); - - /* Only called in one-shot mode */ - FSP_ERROR_RETURN(TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode, FSP_ERR_INVALID_MODE); - #endif - - /* Stop timer */ - R_TAU->TT0 = p_instance_ctrl->channels_mask; - - /* Disable the output */ - R_TAU->TOE0 &= (uint16_t) ~(p_instance_ctrl->slave_channels_mask); - - return FSP_SUCCESS; -#else - FSP_PARAMETER_NOT_USED(p_ctrl); - FSP_RETURN(FSP_ERR_UNSUPPORTED); -#endif -} - /*******************************************************************************************************************//** * Sets period value provided. If the timer is running, the period will be updated after the next counter underflow. * If the timer is stopped, this function resets the counter and updates the period. @@ -432,7 +395,7 @@ fsp_err_t R_TAU_PWM_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const du #endif /* Sets the TDR register for slave channels */ - R_TAU->TDR0[(tau_pwm_io_pin_t) pin].TDR0n = (uint16_t) duty_cycle_counts; + R_TAU->TDR0[pin].TDR0n = (uint16_t) duty_cycle_counts; return FSP_SUCCESS; } @@ -472,21 +435,9 @@ fsp_err_t R_TAU_PWM_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p #endif /* Get and store clock frequency */ - switch (p_extend->operation_clock) - { - case TAU_PWM_OPERATION_CLOCK_CK01: - { - specific_divider = BSP_CFG_TAU_CK01; - break; - } - - case TAU_PWM_OPERATION_CLOCK_CK00: - default: - { - specific_divider = BSP_CFG_TAU_CK00; - break; - } - } + /* figure out which clock and associated divider is driving this channel */ + uint32_t bsp_ck0n_div = BSP_CFG_TAU_CK01 << 8 | BSP_CFG_TAU_CK00; + specific_divider = (uint8_t) (bsp_ck0n_div >> (p_extend->operation_clock << 2)); p_info->clock_frequency = SystemCoreClock >> specific_divider; @@ -516,11 +467,13 @@ fsp_err_t R_TAU_PWM_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * con FSP_ERROR_RETURN(TAU_PWM_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); #endif + uint8_t channel = p_instance_ctrl->p_cfg->channel; + /* Get counter state. */ - p_status->state = (timer_state_t) ((R_TAU->TE0_b.TE >> p_instance_ctrl->p_cfg->channel) & 1U); + p_status->state = (timer_state_t) ((R_TAU->TE0 >> channel) & 1U); /* Get counter value */ - p_status->counter = R_TAU->TCR0[p_instance_ctrl->p_cfg->channel]; + p_status->counter = R_TAU->TCR0[channel]; return FSP_SUCCESS; } @@ -577,19 +530,41 @@ fsp_err_t R_TAU_PWM_Close (timer_ctrl_t * const p_ctrl) R_TAU->TOE0 &= (uint16_t) ~(p_instance_ctrl->slave_channels_mask); /* Disable interrupts. */ - tau_pwm_extended_cfg_t * p_extend = (tau_pwm_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + const tau_pwm_extended_cfg_t * p_extend = (tau_pwm_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; r_tau_pwm_disable_irq(p_instance_ctrl->p_cfg->cycle_end_irq); +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE + + /* Clear open flag. */ + p_instance_ctrl->open = 0U; +#endif + +#if (1 == TAU_PWM_CFG_MULTI_SLAVE_ENABLE) + + /* Save the active slave mask; shift right because channel 0 cant be a slave */ + uint8_t slave_channels_mask = (p_instance_ctrl->slave_channels_mask >> 1); - for (uint8_t channel = 0; channel < TAU_PWM_PRV_MAX_NUM_CHANNELS; channel++) + uint8_t index = 0; + do { - if (NULL != p_extend->p_slave_channel_cfgs[channel]) + if (slave_channels_mask & 0x01) { - r_tau_pwm_disable_irq(p_extend->p_slave_channel_cfgs[channel]->cycle_end_irq); + r_tau_pwm_disable_irq(p_extend->p_slave_channel_cfgs[index]->cycle_end_irq); + index++; } - } - /* Clear open flag. */ - p_instance_ctrl->open = 0U; + slave_channels_mask >>= 1; + } while (slave_channels_mask > 0); + + p_instance_ctrl->slave_channels_mask = 0; +#else + + /* Single slave mode always uses index 0 */ + if ((0 != p_instance_ctrl->slave_channels_mask) && (NULL != p_extend->p_slave_channel_cfgs[0])) + { + r_tau_pwm_disable_irq(p_extend->p_slave_channel_cfgs[0]->cycle_end_irq); + p_instance_ctrl->slave_channels_mask = 0; + } +#endif return FSP_SUCCESS; } @@ -650,35 +625,47 @@ static fsp_err_t r_tau_pwm_parameter_checking (tau_pwm_instance_ctrl_t * const p FSP_ASSERT(TIMER_SOURCE_DIV_1 == p_cfg->source_div); } - for (uint8_t channel = 0; channel < TAU_PWM_PRV_MAX_NUM_CHANNELS; channel++) + #if (0 == TAU_PWM_CFG_MULTI_SLAVE_ENABLE) + const uint8_t index = 0; + #else + for (uint8_t index = 0; index < TAU_PWM_MAX_NUM_SLAVE_CHANNELS; index++) + #endif { - if (NULL != p_extend->p_slave_channel_cfgs[channel]) + if (NULL != p_extend->p_slave_channel_cfgs[index]) { + uint8_t slaveChannel = p_extend->p_slave_channel_cfgs[index]->channel; slave_channels_configured++; /* Slave channel must be valid in range 1 to 7 and greater than master channel number */ - FSP_ERROR_RETURN(((1 << p_extend->p_slave_channel_cfgs[channel]->channel) & - BSP_FEATURE_TAU_VALID_CHANNEL_MASK) && - (p_extend->p_slave_channel_cfgs[channel]->channel > p_cfg->channel), + + FSP_ERROR_RETURN((slaveChannel > TAU_PWM_SLAVE_CHANNEL_UNUSED) && + (slaveChannel <= TAU_PWM_MAX_CHANNEL_NUM) && /*This is TAU_PWM_MAX_CHANNEL_NUM + * because even with a single slave it could be any slave + * from 1-7 */ + (p_extend->p_slave_channel_cfgs[index]->channel > p_cfg->channel), FSP_ERR_INVALID_CHANNEL); /* Pulse width/duty cycle counts of slave channels must be in valid range */ if (TIMER_SOURCE_DIV_1 == p_cfg->source_div) { - FSP_ASSERT(1 <= p_extend->p_slave_channel_cfgs[channel]->duty_cycle_counts); + FSP_ASSERT(1 <= p_extend->p_slave_channel_cfgs[index]->duty_cycle_counts); } } } uint32_t master_counter_max = TAU_PWM_PRV_PERIOD_MAX; uint32_t master_counter_min = TAU_PWM_PRV_PERIOD_MIN; - master_counter_min = (TIMER_SOURCE_DIV_1 == p_cfg->source_div) ? master_counter_min + 1 : master_counter_min; - #if TAU_PWM_CFG_PWM_MODE_ENABLE - if (TIMER_MODE_PWM == p_cfg->mode) + + if (TIMER_SOURCE_DIV_1 == p_cfg->source_div) { - master_counter_max = master_counter_max - 1U; - master_counter_min = master_counter_min - 1U; + master_counter_min++; } + + #if TAU_PWM_CFG_PWM_MODE_ENABLE + + /* decrement counters if mode is PWM */ + master_counter_min = master_counter_min - (TIMER_MODE_PWM == p_cfg->mode); + master_counter_max = master_counter_max - (TIMER_MODE_PWM == p_cfg->mode); #endif /* Pulse period/delay time of master channel must be in valid range */ @@ -711,24 +698,10 @@ static fsp_err_t r_tau_pwm_parameter_checking (tau_pwm_instance_ctrl_t * const p static void r_tau_pwm_hardware_initialize (tau_pwm_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg) { - /* Save pointer to extended configuration structure. */ - tau_pwm_extended_cfg_t * p_extend = (tau_pwm_extended_cfg_t *) p_cfg->p_extend; - - /* Setting the operation clock divider */ - uint16_t tps0 = R_TAU->TPS0; - - if (TAU_PWM_OPERATION_CLOCK_CK00 == p_extend->operation_clock) - { - tps0 &= (uint16_t) ~R_TAU_TPS0_PRS0_Msk; - tps0 |= (uint16_t) (p_cfg->source_div << R_TAU_TPS0_PRS0_Pos); - } - else - { - tps0 &= (uint16_t) ~R_TAU_TPS0_PRS1_Msk; - tps0 |= (uint16_t) (p_cfg->source_div << R_TAU_TPS0_PRS1_Pos); - } - - R_TAU->TPS0 = tps0; + /* Set TAU divisors based on BSP settings */ + R_TAU->TPS0 = (uint16_t) ((TAU_PRV_TPS0_PRS3_SETTING << R_TAU_TPS0_PRS3_Pos) | + (TAU_PRV_TPS0_PRS2_SETTING << R_TAU_TPS0_PRS2_Pos) | + (BSP_CFG_TAU_CK01 << R_TAU_TPS0_PRS1_Pos) | BSP_CFG_TAU_CK00); /* Setting for master channel */ r_tau_pwm_master_channel_initialize(p_instance_ctrl, p_cfg); @@ -768,13 +741,15 @@ static void r_tau_pwm_master_channel_initialize (tau_pwm_instance_ctrl_t * p_ins } /* Clear the noise filter */ - R_PORGA->TNFEN &= (uint8_t) ~(p_instance_ctrl->master_channel_mask); + uint8_t tnfen = R_PORGA->TNFEN & (uint8_t) ~(p_instance_ctrl->master_channel_mask); if ((TAU_PWM_SOURCE_PIN_INPUT == p_extend->trigger_source)) { /* Enables the noise filter for input pin */ - R_PORGA->TNFEN |= p_instance_ctrl->master_channel_mask; + tnfen |= p_instance_ctrl->master_channel_mask; } + R_PORGA->TNFEN = tnfen; + /* Sets the operation mode to one count */ tmr0 = TAU_PWM_PRV_TMR0_MD_ONE_COUNT << R_TAU_TMR0_MD_Pos; @@ -811,10 +786,7 @@ static void r_tau_pwm_master_channel_initialize (tau_pwm_instance_ctrl_t * p_ins /* Sets the TDR register to specify the counter data of master channel */ uint32_t tdr0 = p_cfg->period_counts - 2U; #if TAU_PWM_CFG_PWM_MODE_ENABLE - if (TIMER_MODE_PWM == p_cfg->mode) - { - tdr0 = tdr0 + 1U; - } + tdr0 += (TIMER_MODE_PWM == p_cfg->mode); #endif R_TAU->TDR0[p_cfg->channel].TDR0n = (uint16_t) tdr0; @@ -847,16 +819,18 @@ static void r_tau_pwm_slave_channels_initialize (tau_pwm_instance_ctrl_t * p_ins /* Calculate TMR0 register for slave channels */ uint16_t tmr0; - for (uint8_t channel = 0; channel < TAU_PWM_PRV_MAX_NUM_CHANNELS; channel++) +#if (0 == TAU_PWM_CFG_MULTI_SLAVE_ENABLE) + const uint8_t index = 0; +#else + for (uint8_t index = 0; index < TAU_PWM_MAX_NUM_SLAVE_CHANNELS; index++) +#endif { - if (NULL != p_extend->p_slave_channel_cfgs[channel]) + if (NULL != p_extend->p_slave_channel_cfgs[index]) { - uint8_t slave_channel = p_extend->p_slave_channel_cfgs[channel]->channel; + const tau_pwm_channel_cfg_t * slave_channel_cfg = p_extend->p_slave_channel_cfgs[index]; + uint8_t slave_channel = slave_channel_cfg->channel; uint8_t slave_channel_mask = (uint8_t) (1U << slave_channel); - /* Power on TAU to start module. */ - R_BSP_MODULE_START(FSP_IP_TAU, slave_channel); - /* Sets the operation mode */ tmr0 = TAU_PWM_PRV_TMR0_MD_ONE_COUNT << R_TAU_TMR0_MD_Pos; #if TAU_PWM_CFG_PWM_MODE_ENABLE @@ -878,26 +852,25 @@ static void r_tau_pwm_slave_channels_initialize (tau_pwm_instance_ctrl_t * p_ins /* Sets the TDR register to specify the counter data of slave channel */ R_TAU->TDR0[slave_channel].TDR0n = - p_extend->p_slave_channel_cfgs[channel]->duty_cycle_counts; + slave_channel_cfg->duty_cycle_counts; /* Sets output setting for slave channel */ R_TAU->TOM0 |= (uint16_t) (slave_channel_mask); uint16_t tol0 = R_TAU->TOL0; tol0 &= (uint16_t) ~(slave_channel_mask); - tol0 |= (uint16_t) (p_extend->p_slave_channel_cfgs[channel]->output_polarity << slave_channel); + tol0 |= (uint16_t) (slave_channel_cfg->output_polarity << slave_channel); R_TAU->TOL0 = tol0; uint16_t to0 = R_TAU->TO0; to0 &= (uint16_t) ~(slave_channel_mask); - to0 |= (uint16_t) (p_extend->p_slave_channel_cfgs[channel]->output_level << slave_channel); + to0 |= (uint16_t) (slave_channel_cfg->output_level << slave_channel); R_TAU->TO0 = to0; p_instance_ctrl->slave_channels_mask |= slave_channel_mask; /* Enables interrupt */ - r_tau_pwm_enable_irq(p_extend->p_slave_channel_cfgs[channel]->cycle_end_irq, - p_extend->p_slave_channel_cfgs[channel]->cycle_end_ipl, p_instance_ctrl); + r_tau_pwm_enable_irq(slave_channel_cfg->cycle_end_irq, slave_channel_cfg->cycle_end_ipl, p_instance_ctrl); } } diff --git a/ra/fsp/src/r_uarta/r_uarta.c b/ra/fsp/src/r_uarta/r_uarta.c index c8370ccbb..2b3ba91c0 100644 --- a/ra/fsp/src/r_uarta/r_uarta.c +++ b/ra/fsp/src/r_uarta/r_uarta.c @@ -23,17 +23,13 @@ /* "UART" in ASCII. Used to determine if the control block is open. */ #define UARTA_OPEN (0x55415254) -/* UARTA ASISA register receiver error bit masks */ -#define UARTA_ASISA_RCVR_ERR_MASK (R_UARTA_ASISA0_PEA_Msk | R_UARTA_ASISA0_FEA_Msk | R_UARTA_ASISA0_OVEA_Msk) - /* UARTA parity bit mapping */ #define UARTA_PARITY_OFF_MAPPING (0U) #define UARTA_PARITY_ZERO_MAPPING (1U) #define UARTA_PARITY_ODD_MAPPING (2U) #define UARTA_PARITY_EVEN_MAPPING (3U) -/* No limit to the number of bytes to read or write if DTC is not used. */ -#define UARTA_MAX_READ_WRITE_NO_DTC (0xFFFFFFFFU) +#define UARTA_MAX_TRANSFER_BYTES (0x10000) /* Number of clock select and divider */ #define UARTA_UATCK_UATSEL_COUNT (4U) @@ -45,9 +41,6 @@ #define UARTA_BRGCA_MAX (255) #define UARTA_BRGCA_MIN (2) -/* Maximum DTC transfer value is 65536 */ -#define UARTA_DTC_MAX_TRANSFER (0x10000U) - /* Delay cycles */ #define UARTA_DELAY_2_CYCLE_UATCK (2U) #define UARTA_DELAY_1_CYCLE_UATCK (1U) @@ -69,7 +62,9 @@ (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_DEST_ADDR_BITS) | \ (TRANSFER_REPEAT_AREA_SOURCE << TRANSFER_SETTINGS_REPEAT_AREA_BITS)) -#define UARTA_CONVERT_TO_MICRO_SECOND (1000000U) +/* Wait time needs to be rounded up to enable TX/RX. */ +#define UARTA_CONVERT_TO_MICRO_SECOND (999999U) + #define UARTA_MAX_BAUD_RATE_ERROR_10PPM (4740U) /* Scaling factor for baud rate error values, 10ppm or .001% */ @@ -105,20 +100,15 @@ static fsp_err_t r_uarta_read_write_param_check(uarta_instance_ctrl_t const * co #if UARTA_CFG_DTC_SUPPORT_ENABLE static fsp_err_t r_uarta_transfer_configure(uarta_instance_ctrl_t * const p_ctrl); +static fsp_err_t r_uarta_transfer_configure_helper(transfer_instance_t const * p_transfer, uart_dir_t direction); #endif -static fsp_err_t r_uarta_baud_validate(uint32_t baudrate, - uint32_t f_uta, - uint32_t baud_divider, - uint32_t max_error_10ppm, - uint32_t * p_error_10ppm); - -static void r_uarta_baud_set(R_UARTA_Type * p_uarta_reg, uarta_baud_setting_t const * const p_baud_setting); +static void r_uarta_baud_set(uarta_baud_setting_t const * const p_baud_setting); static void r_uarta_call_callback(uarta_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event); -static void r_uarta_wait_time(uarta_instance_ctrl_t * const p_ctrl, uint32_t delay_cyles); +static uint16_t r_uarta_calculate_wait_time(uarta_baud_setting_t const * const p_baud_setting); #if (UARTA_CFG_RX_ENABLE) @@ -140,10 +130,10 @@ void uarta_txi_isr(void); /** Look-up table for parity values */ static const uint8_t uarta_parity_lut[] = { - [UART_PARITY_OFF] = UARTA_PARITY_OFF_MAPPING, - [UART_PARITY_ZERO] = UARTA_PARITY_ZERO_MAPPING, - [UART_PARITY_EVEN] = UARTA_PARITY_EVEN_MAPPING, - [UART_PARITY_ODD] = UARTA_PARITY_ODD_MAPPING + [UART_PARITY_OFF] = UARTA_PARITY_OFF_MAPPING << R_UARTA_ASIMA01_PS_Pos, + [UART_PARITY_ZERO] = UARTA_PARITY_ZERO_MAPPING << R_UARTA_ASIMA01_PS_Pos, + [UART_PARITY_EVEN] = UARTA_PARITY_EVEN_MAPPING << R_UARTA_ASIMA01_PS_Pos, + [UART_PARITY_ODD] = UARTA_PARITY_ODD_MAPPING << R_UARTA_ASIMA01_PS_Pos }; /** Look-up table for converting UARTA clock source, used to get the clock value from R_BSP_SourceClockHzGet */ @@ -155,6 +145,25 @@ static fsp_priv_source_clock_t uarta_f_uta0_sel_lut[] = [UARTA_CLOCK_SOURCE_MOCO] = FSP_PRIV_CLOCK_MOCO }; +#if (UARTA_CFG_RX_ENABLE) + +/** Look-up table for event types */ +static const uint8_t uarta_event_lut[] = +{ + [0] = 0, + [1] = UART_EVENT_ERR_OVERFLOW, + [2] = UART_EVENT_ERR_FRAMING, + [3] = UART_EVENT_ERR_OVERFLOW | UART_EVENT_ERR_FRAMING, + [4] = UART_EVENT_ERR_PARITY, + [5] = UART_EVENT_ERR_PARITY | UART_EVENT_ERR_OVERFLOW, + [6] = UART_EVENT_ERR_PARITY | UART_EVENT_ERR_FRAMING, + [7] = UART_EVENT_ERR_OVERFLOW | UART_EVENT_ERR_FRAMING | UART_EVENT_ERR_PARITY +}; + + #define UARTA_ASISA_RCVR_ERR_MASK (R_UARTA_ASISA0_OVEA_Msk | R_UARTA_ASISA0_FEA_Msk | R_UARTA_ASISA0_PEA_Msk) + +#endif + /* UART on UARTA HAL API mapping for UART interface */ const uart_api_t g_uart_on_uarta = { @@ -213,11 +222,11 @@ fsp_err_t R_UARTA_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const FSP_ASSERT(p_cfg->rxi_irq >= 0); FSP_ASSERT(p_cfg->txi_irq >= 0); + #if (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE == 0) + /* UARTA0_ERRI interrupt request should be greater than 0 when Receive Error Interrupt Mode is disabled */ - if (UARTA_RXI_MODE_ERROR_TRIGGER_ERI == (uarta_extended_cfg_t *) p_cfg->p_extend) - { - FSP_ASSERT(p_cfg->eri_irq >= 0); - } + FSP_ASSERT(p_cfg->eri_irq >= 0); + #endif #endif p_ctrl->p_cfg = p_cfg; @@ -239,59 +248,54 @@ fsp_err_t R_UARTA_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const uarta_extended_cfg_t * p_extend = (uarta_extended_cfg_t *) p_ctrl->p_cfg->p_extend; /* Set the baud rate settings for the internal baud rate generator. */ - r_uarta_baud_set(R_UARTA, p_extend->p_baud_setting); - - uint8_t asima1 = 0; + r_uarta_baud_set(p_extend->p_baud_setting); /* Setting parity, length, stop, direction, and level bit */ - asima1 = (uint8_t) ((uarta_parity_lut[p_cfg->parity] << R_UARTA_ASIMA01_PS_Pos) | - ((uint8_t) (p_cfg->data_bits << R_UARTA_ASIMA01_CL_Pos)) | - ((uint8_t) (p_cfg->stop_bits << R_UARTA_ASIMA01_SL_Pos)) | - ((uint8_t) (p_extend->transfer_dir << R_UARTA_ASIMA01_DIR_Pos)) | - ((uint8_t) (p_extend->transfer_level << R_UARTA_ASIMA01_ALV_Pos))); - - uint8_t asima0 = 0; + R_UARTA->ASIMA01 = (uint8_t) ((uarta_parity_lut[p_cfg->parity]) | + ((uint8_t) (p_cfg->data_bits << R_UARTA_ASIMA01_CL_Pos)) | + ((uint8_t) (p_cfg->stop_bits << R_UARTA_ASIMA01_SL_Pos)) | + ((uint8_t) (p_extend->transfer_dir << R_UARTA_ASIMA01_DIR_Pos)) | + ((uint8_t) (p_extend->transfer_level << R_UARTA_ASIMA01_ALV_Pos))); /* Setting interrupt for continuous transmission and receive interrupt mode select */ - asima0 |= (uint8_t) ((R_UARTA_ASIMA00_ISSMA_Msk) | - ((uint8_t) (p_extend->rxi_mode << R_UARTA_ASIMA00_ISRMA_Pos))); + uint8_t asima0 = (uint8_t) ((R_UARTA_ASIMA00_ISSMA_Msk) | + ((uint8_t) (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE << R_UARTA_ASIMA00_ISRMA_Pos))); - /* Configure for register ASIMA1 and ASIMA0 */ - R_UARTA->ASIMA01 = asima1; + /* Configure for register ASIMA0 */ R_UARTA->ASIMA00 = asima0; - p_ctrl->p_tx_src = NULL; - p_ctrl->tx_src_bytes = 0U; - p_ctrl->p_rx_dest = NULL; - p_ctrl->rx_dest_bytes = 0U; - /* Enables the UARTA operation clock */ asima0 |= R_UARTA_ASIMA00_EN_Msk; R_UARTA->ASIMA00 = asima0; #if (UARTA_CFG_RX_ENABLE) + p_ctrl->rx_dest_bytes = 0; /* If reception is enabled at build time, enable reception. */ - asima0 |= R_UARTA_ASIMA00_RXEA_Msk; - R_UARTA->ASIMA00 = asima0; - - /* ERI is optional. */ - if (0 <= p_cfg->eri_irq) - { - R_BSP_IrqCfgEnable(p_cfg->eri_irq, p_cfg->eri_ipl, p_ctrl); - } - R_BSP_IrqCfgEnable(p_cfg->rxi_irq, p_cfg->rxi_ipl, p_ctrl); + asima0 |= R_UARTA_ASIMA00_RXEA_Msk; #endif #if (UARTA_CFG_TX_ENABLE) + p_ctrl->tx_src_bytes = 0; /* If transmission is enabled at build time, enable transmission. */ - asima0 |= R_UARTA_ASIMA00_TXEA_Msk; + asima0 |= R_UARTA_ASIMA00_TXEA_Msk; +#endif + R_UARTA->ASIMA00 = asima0; +#if (UARTA_CFG_RX_ENABLE) + #if (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE == 0) + R_BSP_IrqCfgEnable(p_cfg->eri_irq, p_cfg->eri_ipl, p_ctrl); + #endif + R_BSP_IrqCfgEnable(p_cfg->rxi_irq, p_cfg->rxi_ipl, p_ctrl); +#endif + +#if (UARTA_CFG_TX_ENABLE) + /* Wait for the period of at least one cycle of the UARTA operation clock according to "Note" section 22.2.3 * "ASIMA00 : Operation Mode Setting Register 00" in the RA0E1 manual r01uh1040ej0060-ra0e1.pdf .*/ - r_uarta_wait_time(p_ctrl, UARTA_DELAY_1_CYCLE_UATCK); + R_BSP_SoftwareDelay(p_extend->p_baud_setting->delay_time, BSP_DELAY_UNITS_MICROSECONDS); R_BSP_IrqCfgEnable(p_cfg->txi_irq, p_cfg->txi_ipl, p_ctrl); #endif @@ -312,11 +316,14 @@ fsp_err_t R_UARTA_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const fsp_err_t R_UARTA_Close (uart_ctrl_t * const p_api_ctrl) { uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) p_api_ctrl; + #if (UARTA_CFG_PARAM_CHECKING_ENABLE) FSP_ASSERT(p_ctrl); FSP_ERROR_RETURN(UARTA_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif + uart_cfg_t const * p_cfg = p_ctrl->p_cfg; + /* Mark UARTA not open so it can be used again. */ p_ctrl->open = 0; @@ -332,33 +339,32 @@ fsp_err_t R_UARTA_Close (uart_ctrl_t * const p_api_ctrl) R_UARTA->ASIMA00 = (uint8_t) (current_value & ~R_UARTA_ASIMA00_EN_Msk); #if (UARTA_CFG_RX_ENABLE) + #if (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE == 0) + R_BSP_IrqDisable(p_cfg->eri_irq); + #endif /* If reception is enabled at build time, disable reception irqs. */ - R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); - - /* ERI is optional. */ - if (0 <= p_ctrl->p_cfg->eri_irq) - { - R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq); - } + R_BSP_IrqDisable(p_cfg->rxi_irq); #endif #if (UARTA_CFG_TX_ENABLE) /* If transmission is enabled at build time, disable transmission irqs. */ - R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + R_BSP_IrqDisable(p_cfg->txi_irq); #endif #if UARTA_CFG_DTC_SUPPORT_ENABLE #if (UARTA_CFG_RX_ENABLE) - if (NULL != p_ctrl->p_cfg->p_transfer_rx) + transfer_instance_t const * p_transfer_rx = p_cfg->p_transfer_rx; + if (NULL != p_transfer_rx) { - p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + p_transfer_rx->p_api->close(p_transfer_rx->p_ctrl); } #endif #if (UARTA_CFG_TX_ENABLE) - if (NULL != p_ctrl->p_cfg->p_transfer_tx) + transfer_instance_t const * p_transfer_tx = p_cfg->p_transfer_tx; + if (NULL != p_transfer_tx) { - p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + p_transfer_tx->p_api->close(p_transfer_tx->p_ctrl); } #endif #endif @@ -394,36 +400,19 @@ fsp_err_t R_UARTA_Read (uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, #endif #if UARTA_CFG_DTC_SUPPORT_ENABLE + transfer_instance_t const * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; /* Configure transfer instance to receive the requested number of bytes if transfer is used for reception. */ - if (NULL != p_ctrl->p_cfg->p_transfer_rx) + if (NULL != p_transfer_rx) { - uint32_t size = bytes; - #if (UARTA_CFG_PARAM_CHECKING_ENABLE) - - /* Check that the number of transfers is within the 65536 limit. */ - FSP_ASSERT(size <= UARTA_DTC_MAX_TRANSFER); - #endif - err = - p_ctrl->p_cfg->p_transfer_rx->p_api->reset(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, NULL, (void *) p_dest, - (uint16_t) size); + err = p_transfer_rx->p_api->reset(p_transfer_rx->p_ctrl, NULL, (void *) p_dest, (uint16_t) bytes); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); - p_ctrl->p_rx_dest = NULL; - p_ctrl->rx_dest_bytes = bytes; - } - else - { - /* Data can be received when DTC support is enabled but the transfer instances are null.*/ - p_ctrl->p_rx_dest = p_dest; - p_ctrl->rx_dest_bytes = bytes; } - - #else + #endif /* Save the destination address and size for use in rxi_isr. */ p_ctrl->p_rx_dest = p_dest; p_ctrl->rx_dest_bytes = bytes; - #endif return err; #else @@ -475,18 +464,19 @@ fsp_err_t R_UARTA_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * const p /* If a transfer instance is used for transmission, reset the transfer instance to transmit the requested * data. */ - if ((NULL != p_ctrl->p_cfg->p_transfer_tx) && (num_transfers)) + transfer_instance_t const * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + if ((NULL != p_transfer_tx) && (num_transfers)) { #if (UARTA_CFG_PARAM_CHECKING_ENABLE) /* Check that the number of transfers is within the 16-bit limit. */ - FSP_ASSERT(num_transfers <= UARTA_DTC_MAX_TRANSFER); + FSP_ASSERT(num_transfers <= UARTA_MAX_TRANSFER_BYTES); #endif - err = p_ctrl->p_cfg->p_transfer_tx->p_api->reset(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, - (void const *) p_ctrl->p_tx_src, - NULL, - (uint16_t) num_transfers); + err = p_transfer_tx->p_api->reset(p_transfer_tx->p_ctrl, + (void const *) p_ctrl->p_tx_src, + NULL, + (uint16_t) num_transfers); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); } #endif @@ -569,15 +559,14 @@ fsp_err_t R_UARTA_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const p_ /* Modify the BRGCAn bits while the TXEAn and RXEAn bits are 0 (in the transmission/reception stopped state).*/ R_UARTA->ASIMA00 = (preserved_asima00 & (uint8_t) (~(R_UARTA_ASIMA00_RXEA_Msk | R_UARTA_ASIMA00_TXEA_Msk))); - p_ctrl->p_tx_src = NULL; - /* Apply new baud rate register settings. */ - r_uarta_baud_set(R_UARTA, p_baud_setting); + r_uarta_baud_set(p_baud_setting); /* To enable transmission or reception again, set the TXEAn or RXEAn bit to 1 at least two cycles of the UARTAn * operation clock after clearing the TXEAn or RXEAn bit to 0 according to "Note" section 22.2.3 * "ASIMA00 : Operation Mode Setting Register 00" in the RA0E1 manual r01uh1040ej0060-ra0e1.pdf.*/ - r_uarta_wait_time(p_ctrl, UARTA_DELAY_2_CYCLE_UATCK); + uint16_t delay_time = r_uarta_calculate_wait_time(p_baud_setting); + R_BSP_SoftwareDelay((uint32_t) delay_time << 1U, BSP_DELAY_UNITS_MICROSECONDS); /* Restore all settings. */ R_UARTA->ASIMA00 = preserved_asima00; @@ -588,7 +577,7 @@ fsp_err_t R_UARTA_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const p_ { /* Wait for the period of at least one cycle of the UARTA operation clock according to "Note" section 22.2.3 * "ASIMA00 : Operation Mode Setting Register 00" in the RA0E1 manual r01uh1040ej0060-ra0e1.pdf .*/ - r_uarta_wait_time(p_ctrl, UARTA_DELAY_1_CYCLE_UATCK); + R_BSP_SoftwareDelay((uint32_t) delay_time, BSP_DELAY_UNITS_MICROSECONDS); } #endif @@ -605,45 +594,17 @@ fsp_err_t R_UARTA_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const p_ **********************************************************************************************************************/ fsp_err_t R_UARTA_InfoGet (uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info) { -#if UARTA_CFG_PARAM_CHECKING_ENABLE || UARTA_CFG_DTC_SUPPORT_ENABLE +#if UARTA_CFG_PARAM_CHECKING_ENABLE uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) p_api_ctrl; -#else - FSP_PARAMETER_NOT_USED(p_api_ctrl); -#endif - -#if (UARTA_CFG_PARAM_CHECKING_ENABLE) FSP_ASSERT(p_ctrl); FSP_ASSERT(p_info); FSP_ERROR_RETURN(UARTA_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); #endif - uint32_t read_bytes_max = UARTA_MAX_READ_WRITE_NO_DTC; - uint32_t write_bytes_max = UARTA_MAX_READ_WRITE_NO_DTC; - -#if (UARTA_CFG_RX_ENABLE) - - /* Store number of bytes that can be read at a time. */ - #if UARTA_CFG_DTC_SUPPORT_ENABLE - if (NULL != p_ctrl->p_cfg->p_transfer_rx) - { - read_bytes_max = UARTA_DTC_MAX_TRANSFER; - } - #endif -#endif - -#if (UARTA_CFG_TX_ENABLE) - - /* Store number of bytes that can be written at a time. */ - #if UARTA_CFG_DTC_SUPPORT_ENABLE - if (NULL != p_ctrl->p_cfg->p_transfer_tx) - { - write_bytes_max = UARTA_DTC_MAX_TRANSFER; - } - #endif -#endif - - p_info->read_bytes_max = read_bytes_max; - p_info->write_bytes_max = write_bytes_max; + p_info->read_bytes_max = UARTA_MAX_TRANSFER_BYTES; + p_info->write_bytes_max = UARTA_MAX_TRANSFER_BYTES; return FSP_SUCCESS; } @@ -664,8 +625,10 @@ fsp_err_t R_UARTA_InfoGet (uart_ctrl_t * const p_api_ctrl, uart_info_t * const p **********************************************************************************************************************/ fsp_err_t R_UARTA_Abort (uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort) { +#if (UARTA_CFG_PARAM_CHECKING_ENABLE) || (UARTA_CFG_TX_ENABLE) || (UARTA_CFG_RX_ENABLE) uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) p_api_ctrl; - fsp_err_t err = FSP_ERR_UNSUPPORTED; +#endif + fsp_err_t err = FSP_ERR_UNSUPPORTED; #if (UARTA_CFG_PARAM_CHECKING_ENABLE) FSP_ASSERT(p_ctrl); @@ -680,13 +643,14 @@ fsp_err_t R_UARTA_Abort (uart_ctrl_t * const p_api_ctrl, uart_dir_t communicatio R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); #if UARTA_CFG_DTC_SUPPORT_ENABLE - if (NULL != p_ctrl->p_cfg->p_transfer_tx) + transfer_instance_t const * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + if (NULL != p_transfer_tx) { - err = p_ctrl->p_cfg->p_transfer_tx->p_api->disable(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + err = p_transfer_tx->p_api->disable(p_transfer_tx->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); } - FSP_ERROR_RETURN(FSP_SUCCESS == err, err); #endif - p_ctrl->tx_src_bytes = 0U; + p_ctrl->tx_src_bytes = 0; } #endif @@ -695,15 +659,14 @@ fsp_err_t R_UARTA_Abort (uart_ctrl_t * const p_api_ctrl, uart_dir_t communicatio { err = FSP_SUCCESS; - p_ctrl->rx_dest_bytes = 0U; - #if UARTA_CFG_DTC_SUPPORT_ENABLE - if (NULL != p_ctrl->p_cfg->p_transfer_rx) + transfer_instance_t const * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; + if (NULL != p_transfer_rx) { - err = p_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + err = p_transfer_rx->p_api->disable(p_transfer_rx->p_ctrl); } - FSP_ERROR_RETURN(FSP_SUCCESS == err, err); #endif + p_ctrl->rx_dest_bytes = 0U; } #endif @@ -738,13 +701,14 @@ fsp_err_t R_UARTA_ReadStop (uart_ctrl_t * const p_api_ctrl, uint32_t * p_remaini p_ctrl->rx_dest_bytes = 0; #if UARTA_CFG_DTC_SUPPORT_ENABLE - if (NULL != p_ctrl->p_cfg->p_transfer_rx) + transfer_instance_t const * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; + if (NULL != p_transfer_rx) { - fsp_err_t err = p_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + fsp_err_t err = p_transfer_rx->p_api->disable(p_transfer_rx->p_ctrl); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); transfer_properties_t transfer_info; - err = p_ctrl->p_cfg->p_transfer_rx->p_api->infoGet(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, &transfer_info); + err = p_transfer_rx->p_api->infoGet(p_transfer_rx->p_ctrl, &transfer_info); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); remaining_bytes = transfer_info.transfer_length_remaining; } @@ -790,35 +754,13 @@ fsp_err_t R_UARTA_BaudCalculate (uint32_t baudrate, FSP_ERROR_RETURN(UARTA_MAX_BAUD_RATE >= baudrate, FSP_ERR_INVALID_ARGUMENT); FSP_ERROR_RETURN((0U != baudrate), FSP_ERR_INVALID_ARGUMENT); #endif - uint32_t min_error_10ppm = UINT32_MAX; - uint32_t clock_source_value = R_BSP_SourceClockHzGet(uarta_f_uta0_sel_lut[clock_source]); + fsp_err_t ret = FSP_ERR_INVALID_RATE; - if (UARTA_CLOCK_SOURCE_SOSC_LOCO == clock_source) - { - /* Find the appropriate divider for the requested baud rate. - * k = round(f_UTA0 / (2 * Desired baud rate)) - * Integer round to the nearest divider. - */ - const uint32_t k = (clock_source_value + baudrate) / (2U * baudrate); - - uint32_t error_10ppm = 0; - - /* Validate the baud rate and get the error. If invalid, skip to the next divider. */ - fsp_err_t err = r_uarta_baud_validate(baudrate, - clock_source_value, - k, - baud_rate_percent_error_x1000, - &error_10ppm); - FSP_ERROR_RETURN(FSP_SUCCESS == err, err); - - /* Save the settings. */ - p_baud_setting->brgca = (uint8_t) k; - p_baud_setting->uta0ck_clock_b.utasel = 0U; - p_baud_setting->uta0ck_clock_b.uta0ck = UARTA_UTA0CK_SOSC_LOCO_SETTING; + /* UARTA_MAX_BAUD_RATE * UARTA_MAX_BAUD_RATE_ERROR_10PPM < UINT32_MAX */ + uint32_t delta_max = baudrate * baud_rate_percent_error_x1000 / UARTA_BAUD_ERROR_SCALING_10PPM; - return FSP_SUCCESS; - } + uint32_t clock_source_value = R_BSP_SourceClockHzGet(uarta_f_uta0_sel_lut[clock_source]); /* Go ahead and set the clock source here. It stays constant through the baud rate search. */ p_baud_setting->uta0ck_clock_b.utasel = (uint8_t) (clock_source & UARTA_UTA0SEL_MASK); @@ -826,40 +768,36 @@ fsp_err_t R_UARTA_BaudCalculate (uint32_t baudrate, for (uarta_clock_div_t f_uta0_div = UARTA_CLOCK_DIV_1; f_uta0_div < UARTA_CLOCK_DIV_COUNT; f_uta0_div++) { /* Calculate UARTA operation clock (f_UTA0)*/ - const uint32_t f_uta0_value = clock_source_value >> f_uta0_div; + uint32_t f_uta0_value = clock_source_value >> f_uta0_div; /* Find the appropriate divider for the requested baud rate. - * k = round(f_UTA0 / (2 * Desired baud rate)) + * divider = round(f_UTA0 / (2 * Desired baud rate)) * Integer round to the nearest divider. */ - const uint32_t k = (f_uta0_value + baudrate) / (2U * baudrate); - - uint32_t error_10ppm = 0; - - /* Validate the baud rate and get the error. If invalid, skip to the next divider. */ - if (FSP_SUCCESS != - r_uarta_baud_validate(baudrate, f_uta0_value, k, baud_rate_percent_error_x1000, &error_10ppm)) + uint32_t divider = ((f_uta0_value + baudrate) >> 1) / baudrate; + if ((divider >= UARTA_BRGCA_MIN) && (divider <= UARTA_BRGCA_MAX)) { - continue; + /* Calculate actual baudrate using the divider. */ + uint32_t actual_baudrate = (f_uta0_value >> 1) / divider; + uint32_t delta = baudrate >= + actual_baudrate ? (baudrate - actual_baudrate) : (actual_baudrate - baudrate); + if (delta < delta_max) + { + delta_max = delta; + p_baud_setting->brgca = (uint8_t) divider; + p_baud_setting->uta0ck_clock_b.uta0ck = (uint8_t) (f_uta0_div & R_UARTA_UTA0CK_CK_Msk); + ret = FSP_SUCCESS; + } } - if (error_10ppm < min_error_10ppm) + if (UARTA_CLOCK_SOURCE_SOSC_LOCO == clock_source) { - /* Save the current error and update the settings. */ - min_error_10ppm = error_10ppm; - - p_baud_setting->brgca = (uint8_t) k; - p_baud_setting->uta0ck_clock_b.uta0ck = (uint8_t) (f_uta0_div & R_UARTA_UTA0CK_CK_Msk); + p_baud_setting->uta0ck_clock_b.uta0ck = UARTA_UTA0CK_SOSC_LOCO_SETTING; + break; } } - /* If no divider could be found, min_error_10ppm would still be UINT32_MAX. */ - if (min_error_10ppm == UINT32_MAX) - { - return FSP_ERR_INVALID_RATE; - } - - return FSP_SUCCESS; + return ret; } /*******************************************************************************************************************//** @@ -890,6 +828,7 @@ static fsp_err_t r_uarta_read_write_param_check (uarta_instance_ctrl_t const * c FSP_ASSERT(p_ctrl); FSP_ASSERT(addr); FSP_ASSERT(0U != bytes); + FSP_ASSERT(UARTA_MAX_TRANSFER_BYTES >= bytes); FSP_ERROR_RETURN(UARTA_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); return FSP_SUCCESS; @@ -909,66 +848,69 @@ static fsp_err_t r_uarta_read_write_param_check (uarta_instance_ctrl_t const * c **********************************************************************************************************************/ static fsp_err_t r_uarta_transfer_configure (uarta_instance_ctrl_t * const p_ctrl) { - fsp_err_t err = FSP_SUCCESS; - transfer_info_t * p_info = NULL; + fsp_err_t err = FSP_SUCCESS; + #if (UARTA_CFG_RX_ENABLE) transfer_instance_t const * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; /* If a transfer instance is used for reception, apply UART specific settings and open the transfer instance. */ - if (NULL != p_transfer_rx) - { - /* Configure the transfer instance, if enabled. */ - #if (UARTA_CFG_PARAM_CHECKING_ENABLE) - FSP_ASSERT(NULL != p_transfer_rx->p_api); - FSP_ASSERT(NULL != p_transfer_rx->p_ctrl); - FSP_ASSERT(NULL != p_transfer_rx->p_cfg); - FSP_ASSERT(NULL != p_transfer_rx->p_cfg->p_info); - FSP_ASSERT(NULL != p_transfer_rx->p_cfg->p_extend); - #endif - - p_info = p_transfer_rx->p_cfg->p_info; - - p_info->transfer_settings_word = UARTA_DTC_RX_TRANSFER_SETTINGS; - - /* Casting for compatibility with 5, 7 or 8 bit mode. */ - p_info->p_src = (void *) &(R_UARTA->RXBA0); - - err = p_transfer_rx->p_api->open(p_transfer_rx->p_ctrl, p_transfer_rx->p_cfg); - FSP_ERROR_RETURN(FSP_SUCCESS == err, err); - } + err = r_uarta_transfer_configure_helper(p_transfer_rx, UART_DIR_RX); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); #endif + #if (UARTA_CFG_TX_ENABLE) transfer_instance_t const * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; /* If a transfer instance is used for transmission, apply UART specific settings and open the transfer instance. */ - if (NULL != p_transfer_tx) + err = r_uarta_transfer_configure_helper(p_transfer_tx, UART_DIR_TX); + #if (UARTA_CFG_RX_ENABLE) + if ((err != FSP_SUCCESS) && (NULL != p_transfer_rx)) { - /* Configure the transfer instance, if enabled. */ - #if (UARTA_CFG_PARAM_CHECKING_ENABLE) - FSP_ASSERT(NULL != p_transfer_tx->p_api); - FSP_ASSERT(NULL != p_transfer_tx->p_ctrl); - FSP_ASSERT(NULL != p_transfer_tx->p_cfg); - FSP_ASSERT(NULL != p_transfer_tx->p_cfg->p_info); - FSP_ASSERT(NULL != p_transfer_tx->p_cfg->p_extend); + p_transfer_rx->p_api->close(p_transfer_rx->p_ctrl); + } #endif + #endif - p_info = p_transfer_tx->p_cfg->p_info; + return err; +} - p_info->transfer_settings_word = UARTA_DTC_TX_TRANSFER_SETTINGS; +/*******************************************************************************************************************//** + * This function initializes transfer descriptor + * + * @param[in] p_transfer Pointer to transfer instance. + * @param[in] direction UART_DIR_TX or UART_DIR_RX. + **********************************************************************************************************************/ +static fsp_err_t r_uarta_transfer_configure_helper (transfer_instance_t const * p_transfer, uart_dir_t direction) +{ + fsp_err_t err = FSP_SUCCESS; - p_info->p_dest = (void *) &(R_UARTA->TXBA0); + if (NULL != p_transfer) + { + /* Configure the transfer instance, if enabled. */ + #if (UARTA_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_transfer->p_api); + FSP_ASSERT(NULL != p_transfer->p_ctrl); + FSP_ASSERT(NULL != p_transfer->p_cfg); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_info); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_extend); + #endif - err = p_transfer_tx->p_api->open(p_transfer_tx->p_ctrl, p_transfer_tx->p_cfg); + transfer_info_t * p_info = p_transfer->p_cfg->p_info; - #if (UARTA_CFG_RX_ENABLE) - if ((err != FSP_SUCCESS) && (NULL != p_transfer_rx)) + /* Casting for compatibility with 5, 7 or 8 bit mode. */ + if (UART_DIR_RX == direction) { - p_transfer_rx->p_api->close(p_transfer_rx->p_ctrl); + p_info->transfer_settings_word = UARTA_DTC_RX_TRANSFER_SETTINGS; + p_info->p_src = (void *) &(R_UARTA->RXBA0); } - #endif - FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + else + { + p_info->transfer_settings_word = UARTA_DTC_TX_TRANSFER_SETTINGS; + p_info->p_dest = (void *) &(R_UARTA->TXBA0); + } + + err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); } - #endif return err; } @@ -978,82 +920,28 @@ static fsp_err_t r_uarta_transfer_configure (uarta_instance_ctrl_t * const p_ctr /*******************************************************************************************************************//** * Changes baud rate based on predetermined register settings. * - * @param[in] p_uarta_reg Base pointer for UARTA registers - * @param[in] p_baud_setting Pointer to other divisor related settings + * @param[in] p_baud_setting Pointer to baud rate settings * * @note The transmitter and receiver (TXEA and RXEA bits in ASIMA00) must be disabled prior to calling this function. **********************************************************************************************************************/ -static void r_uarta_baud_set (R_UARTA_Type * p_uarta_reg, uarta_baud_setting_t const * const p_baud_setting) +static void r_uarta_baud_set (uarta_baud_setting_t const * const p_baud_setting) { /* Set BRGCA register value. */ - p_uarta_reg->BRGCA0 = p_baud_setting->brgca; + R_UARTA->BRGCA0 = p_baud_setting->brgca; /* Set UTA0CK register value. */ - p_uarta_reg->UTA0CK = p_baud_setting->uta0ck_clock; -} - -/*******************************************************************************************************************//** - * Validates the baud rate divisor for the given f_UTA0 frequency. - * - * @param[in] baudrate The desired baud rate. - * @param[in] f_uta The operating frequency of the f_UTA0 clock into the baud rate generator. - * @param[in] baud_divider Baud generator divider configured into BRGCA0. - * @param[in] max_error_10ppm Maximum permissible error in 10ppm units (0.001%). - * @param[out] p_error_10ppm Calculated baud rate error in 10ppm units given f_uta and baud_divider. - * - * @retval FSP_SUCCESS The values of f_uta and baud_divider provide an acceptable baud rate. - * @retval FSP_ERR_INVALID_ARGUMENT The value of baud_divider is out of range. - * @retval FSP_ERR_INVALID_RATE The baud rate error is outside the allowed range. - **********************************************************************************************************************/ -static fsp_err_t r_uarta_baud_validate (uint32_t baudrate, - uint32_t f_uta, - uint32_t baud_divider, - uint32_t max_error_10ppm, - uint32_t * p_error_10ppm) -{ - /* If the divider calculated is out of range return an error. */ - if ((baud_divider < UARTA_BRGCA_MIN) || (baud_divider > UARTA_BRGCA_MAX)) - { - return FSP_ERR_INVALID_ARGUMENT; - } - - /* Calculate actual baudrate using the divider (k). - * The formula to calculate actual baudrate is as: - * Actual baud rate = f_UTA0 / (2 * k) - */ - const uint32_t actual_baudrate = f_uta / (2U * baud_divider); - - /* Calculate the error between the actual and desired baud rate in 10ppm. */ - int32_t error_10ppm = (UARTA_BAUD_ERROR_SCALING_10PPM * ((int32_t) actual_baudrate - (int32_t) baudrate)) / - ((int32_t) baudrate); - - if (error_10ppm < 0) - { - error_10ppm = -error_10ppm; - } - - /* If the error is outside the provided bound return. */ - if (((uint32_t) error_10ppm) > max_error_10ppm) - { - return FSP_ERR_INVALID_RATE; - } - - /* Pass the calculated error back to the caller. */ - *p_error_10ppm = (uint32_t) error_10ppm; - - return FSP_SUCCESS; + R_UARTA->UTA0CK = p_baud_setting->uta0ck_clock; } /*******************************************************************************************************************//** - * This function implements waiting for the period of at least one cycle of the UARTAn operation clock (f_UTA0) + * This function calculates the wait time to enable TX * - * @param[in] p_ctrl Pointer to instance control block. - * @param[in] delay_cyles Delay cycles value of the operating clock (f_UTA0). + * @param[in] p_baud_setting Pointer to baud rate settings. **********************************************************************************************************************/ -static void r_uarta_wait_time (uarta_instance_ctrl_t * const p_ctrl, uint32_t delay_cyles) +static uint16_t r_uarta_calculate_wait_time (uarta_baud_setting_t const * const p_baud_setting) { - uint8_t uta0ck = ((uarta_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->p_baud_setting->uta0ck_clock_b.uta0ck; - uint8_t utasel = ((uarta_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->p_baud_setting->uta0ck_clock_b.utasel; + uint8_t uta0ck = p_baud_setting->uta0ck_clock_b.uta0ck; + uint8_t utasel = p_baud_setting->uta0ck_clock_b.utasel; /* Get UARTA clock divider shift. * Anything outside UARTA_CLOCK_DIV_MASK is not a valid divider and is probably LOCO/SOSC selection instead. @@ -1061,11 +949,10 @@ static void r_uarta_wait_time (uarta_instance_ctrl_t * const p_ctrl, uint32_t de uint32_t divider_shift = (uint32_t) (uta0ck & UARTA_CLOCK_DIV_MASK); /* Calculate frequency UARTA0 operation clock */ - uint32_t f_uta0 = (R_BSP_SourceClockHzGet(uarta_f_uta0_sel_lut[utasel]) >> divider_shift); - uint32_t delay_us_cycle = (uint32_t) (UARTA_CONVERT_TO_MICRO_SECOND / f_uta0); + uint32_t f_uta0 = (R_BSP_SourceClockHzGet(uarta_f_uta0_sel_lut[utasel]) >> divider_shift); - /* Waiting for the period */ - R_BSP_SoftwareDelay(delay_us_cycle * delay_cyles, BSP_DELAY_UNITS_MICROSECONDS); + /* Round up especially for the use case f_uta0 > UARTA_CONVERT_TO_MICRO_SECOND */ + return (uint16_t) ((UARTA_CONVERT_TO_MICRO_SECOND + f_uta0) / f_uta0); } /*******************************************************************************************************************//** @@ -1077,15 +964,18 @@ static void r_uarta_wait_time (uarta_instance_ctrl_t * const p_ctrl, uint32_t de **********************************************************************************************************************/ static void r_uarta_call_callback (uarta_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event) { - uart_callback_args_t args; + if (NULL != p_ctrl->p_callback) + { + uart_callback_args_t args; - args.channel = p_ctrl->p_cfg->channel; - args.data = data; - args.event = event; - args.p_context = p_ctrl->p_context; + args.channel = p_ctrl->p_cfg->channel; + args.data = data; + args.event = event; + args.p_context = p_ctrl->p_context; - /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ - p_ctrl->p_callback(&args); + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(&args); + } } #if (UARTA_CFG_TX_ENABLE) @@ -1109,7 +999,9 @@ void uarta_txi_isr (void) if (0U < p_ctrl->tx_src_bytes) { + #if UARTA_CFG_DTC_SUPPORT_ENABLE if (NULL == p_ctrl->p_cfg->p_transfer_tx) + #endif { /* Write 1byte (uint8_t) data to (uint8_t) data register */ R_UARTA->TXBA0 = *(p_ctrl->p_tx_src); @@ -1118,10 +1010,13 @@ void uarta_txi_isr (void) p_ctrl->tx_src_bytes -= 1U; p_ctrl->p_tx_src += 1U; } + + #if UARTA_CFG_DTC_SUPPORT_ENABLE else { p_ctrl->tx_src_bytes = 0; } + #endif } else if (0U != (R_UARTA->ASIMA00 & R_UARTA_ASIMA00_ISSMA_Msk)) { @@ -1129,13 +1024,7 @@ void uarta_txi_isr (void) } else if (0 == p_ctrl->tx_src_bytes) { - p_ctrl->p_tx_src = NULL; - - /* If a callback was provided, call it with the argument */ - if (NULL != p_ctrl->p_callback) - { - r_uarta_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE); - } + r_uarta_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE); } else { @@ -1167,44 +1056,33 @@ void uarta_rxi_isr (void) IRQn_Type irq = R_FSP_CurrentIrqGet(); /* Recover ISR context saved in open. */ - uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) R_FSP_IsrContextGet(irq); - uarta_extended_cfg_t * p_extend = (uarta_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) R_FSP_IsrContextGet(irq); #if UARTA_CFG_DTC_SUPPORT_ENABLE if ((p_ctrl->p_cfg->p_transfer_rx == NULL) || (0 == p_ctrl->rx_dest_bytes)) #endif { - uint8_t data; - uint8_t err_type = 0; - uart_event_t event; - data = R_UARTA->RXBA0; + uint8_t data = R_UARTA->RXBA0; + #if (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE != 0) - if (UARTA_RXI_MODE_ERROR_TRIGGER_RXI == p_extend->rxi_mode) - { - /* Determine cause of error. */ - err_type = R_UARTA->ASISA0; - event = (uart_event_t) ((((err_type & R_UARTA_ASISA0_OVEA_Msk) != 0) << UARTA_ERR_OVERFLOW_SHIFT_VALUE) | - (((err_type & R_UARTA_ASISA0_FEA_Msk) != 0) << UARTA_ERR_FRAMING_SHIFT_VALUE) | - (((err_type & R_UARTA_ASISA0_PEA_Msk) != 0) << UARTA_ERR_PARITY_SHIFT_VALUE)); - } + /* Determine cause of error. */ + uint8_t err_type = R_UARTA->ASISA0; - if (0 != err_type) + /* Clear error condition. */ + R_UARTA->ASCTA0 = UARTA_ASISA_RCVR_ERR_MASK; + + err_type &= (uint8_t) UARTA_ASISA_RCVR_ERR_MASK; + err_type = uarta_event_lut[err_type]; + if (err_type) { - /* Clear error condition. */ - R_UARTA->ASCTA0 &= (uint8_t) (~UARTA_ASISA_RCVR_ERR_MASK); - r_uarta_call_callback(p_ctrl, (uint32_t) data, event); + r_uarta_call_callback(p_ctrl, data, (uart_event_t) err_type); } else + #endif { if (0 == p_ctrl->rx_dest_bytes) { - /* If a callback was provided, call it with the argument */ - if (NULL != p_ctrl->p_callback) - { - event = UART_EVENT_RX_CHAR; - - /* Call user callback with the data. */ - r_uarta_call_callback(p_ctrl, (uint32_t) data, event); - } + /* Call user callback with the data. */ + r_uarta_call_callback(p_ctrl, (uint32_t) data, UART_EVENT_RX_CHAR); } else { @@ -1214,12 +1092,7 @@ void uarta_rxi_isr (void) if (0 == p_ctrl->rx_dest_bytes) { - /* If a callback was provided, call it with the argument */ - if (NULL != p_ctrl->p_callback) - { - event = UART_EVENT_RX_COMPLETE; - r_uarta_call_callback(p_ctrl, 0U, event); - } + r_uarta_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); } } } @@ -1229,13 +1102,7 @@ void uarta_rxi_isr (void) else { p_ctrl->rx_dest_bytes = 0; - - /* If a callback was provided, call it with the argument */ - if (NULL != p_ctrl->p_callback) - { - /* Call callback */ - r_uarta_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); - } + r_uarta_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); } #endif @@ -1243,16 +1110,14 @@ void uarta_rxi_isr (void) FSP_CONTEXT_RESTORE; } -#endif - -#if (UARTA_CFG_RX_ENABLE) - /*******************************************************************************************************************//** * ERI interrupt processing for UARTA mode. When an ERI interrupt fires, the user callback function is called if it is * registered in R_UARTA_Open() with the event code that triggered the interrupt. **********************************************************************************************************************/ void uarta_eri_isr (void) { + #if (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE == 0) + /* Save context if RTOS is used */ FSP_CONTEXT_SAVE; @@ -1261,30 +1126,20 @@ void uarta_eri_isr (void) /* Recover ISR context saved in open. */ uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) R_FSP_IsrContextGet(irq); - uint8_t data = 0U; - uart_event_t event; - - /* Read data. */ - data = R_UARTA->RXBA0; + uint8_t data = R_UARTA->RXBA0; - /* Determine cause of error. */ uint8_t err_type = R_UARTA->ASISA0; - event = (uart_event_t) ((((err_type & R_UARTA_ASISA0_OVEA_Msk) != 0) << UARTA_ERR_OVERFLOW_SHIFT_VALUE) | - (((err_type & R_UARTA_ASISA0_FEA_Msk) != 0) << UARTA_ERR_FRAMING_SHIFT_VALUE) | - (((err_type & R_UARTA_ASISA0_PEA_Msk) != 0) << UARTA_ERR_PARITY_SHIFT_VALUE)); /* Clear error condition. */ - R_UARTA->ASCTA0 &= (uint8_t) (~UARTA_ASISA_RCVR_ERR_MASK); + R_UARTA->ASCTA0 = UARTA_ASISA_RCVR_ERR_MASK; - /* If a callback was provided, call it with the argument */ - if (NULL != p_ctrl->p_callback) - { - /* Call callback. */ - r_uarta_call_callback(p_ctrl, (uint32_t) data, event); - } + err_type &= (uint8_t) UARTA_ASISA_RCVR_ERR_MASK; + err_type = uarta_event_lut[err_type]; + r_uarta_call_callback(p_ctrl, data, (uart_event_t) err_type); /* Restore context if RTOS is used */ FSP_CONTEXT_RESTORE; + #endif } #endif diff --git a/ra/fsp/src/r_usb_basic/r_usb_basic.c b/ra/fsp/src/r_usb_basic/r_usb_basic.c index 39a7fc05e..f8fa1062b 100644 --- a/ra/fsp/src/r_usb_basic/r_usb_basic.c +++ b/ra/fsp/src/r_usb_basic/r_usb_basic.c @@ -283,6 +283,7 @@ const usb_api_t g_usb_on_usb = .setupGet = R_USB_SetupGet, .otgCallbackSet = R_USB_OtgCallbackSet, .otgSRP = R_USB_OtgSRP, + .typecInfoGet = R_USB_TypeCInfoGet, }; /*********************************************************************************************************************** @@ -409,6 +410,9 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c #if USB_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(p_api_ctrl) FSP_ASSERT(p_cfg) + + /* Check if the module number is valid */ + FSP_ERROR_RETURN(!((USB_IP0 != p_cfg->module_number) && (USB_IP1 != p_cfg->module_number)), FSP_ERR_USB_PARAMETER) #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ #if defined(USB_CFG_OTG_USE) @@ -436,16 +440,14 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c #if USB_CFG_PARAM_CHECKING_ENABLE /* Argument Checking */ - FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) - FSP_ERROR_RETURN(!(((USB_SPEED_HS != p_cfg->usb_speed) && (USB_SPEED_FS != p_cfg->usb_speed)) && (USB_SPEED_LS != p_cfg->usb_speed) && (USB_MODE_HOST != p_cfg->usb_mode)), FSP_ERR_USB_PARAMETER) - #if defined(BSP_MCU_GROUP_RA2A1) + #if (USB_NUM_USBIP == 1) FSP_ERROR_RETURN(USB_IP1 != p_ctrl->module_number, FSP_ERR_USB_PARAMETER) - #endif /* defined(BSP_MCU_GROUP_RA2A1) */ + #endif /* USB_NUM_USBIP == 1 */ switch ((usb_class_internal_t) p_ctrl->type) { @@ -486,10 +488,10 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c case USB_CLASS_INTERNAL_HPRN: case USB_CLASS_INTERNAL_HUVC: { - #if defined(BSP_MCU_GROUP_RA2A1) + #if defined(USB_NOT_SUPPORT_HOST) - return FSP_ERR_ASSERTION; - #else /* defined(BSP_MCU_GROUP_RA2A1) */ + return FSP_ERR_USB_PARAMETER; + #else /* defined(USB_NOT_SUPPORT_HOST) */ FSP_ERROR_RETURN(USB_MODE_HOST == p_cfg->usb_mode, FSP_ERR_USB_PARAMETER) #if defined(USB_HIGH_SPEED_MODULE) FSP_ERROR_RETURN(!((USB_SPEED_HS == p_cfg->usb_speed) && (USB_IP1 != p_ctrl->module_number)), @@ -497,7 +499,7 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c #else /* defined (USB_HIGH_SPEED_MODULE) */ FSP_ERROR_RETURN(USB_SPEED_HS != p_cfg->usb_speed, FSP_ERR_USB_PARAMETER) #endif /* defined (USB_HIGH_SPEED_MODULE) */ - #endif /* defined(BSP_MCU_GROUP_RA2A1) */ + #endif /* defined(USB_NOT_SUPPORT_HOST) */ break; } @@ -632,6 +634,10 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c g_p_usb_otg_cfg = (usb_cfg_t *) p_cfg; #endif /* defined (USB_CFG_OTG_USE) */ +#if (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) + hw_usb_typec_module_init(); +#endif /* USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE */ + if (USB_MODE_HOST == p_cfg->usb_mode) { #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) @@ -859,10 +865,16 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c { #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) g_usb_open_class[p_ctrl->module_number] |= (uint16_t) (1 << p_ctrl->type); /* Set USB Open device class */ + /* Check if both HCDC class and HMSC class are enabled */ + #if (defined(USB_CFG_HCDC_USE) && defined(USB_CFG_HMSC_USE)) + /* Set USB Open device class for HCDC Class and HCDCC Class */ + g_usb_open_class[p_ctrl->module_number] |= ((1 << USB_CLASS_INTERNAL_HCDC) | (1 << USB_CLASS_INTERNAL_HCDCC)); + #else if (USB_CLASS_INTERNAL_HCDC == (usb_class_internal_t) p_ctrl->type) { g_usb_open_class[p_ctrl->module_number] |= (1 << USB_CLASS_INTERNAL_HCDCC); /* Set USB Open device class */ } + #endif /* defined(USB_CFG_HCDC_USE) && defined(USB_CFG_HMSC_USE) */ #if defined(USB_CFG_OTG_USE) g_is_A_device[p_ctrl->module_number] = USB_YES; @@ -1426,6 +1438,10 @@ fsp_err_t R_USB_Close (usb_ctrl_t * const p_api_ctrl) g_usb_pmsc_usbip = USB_VALUE_FFH; #endif /* defined(USB_CFG_PMSC_USE) */ + #if (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) + hw_usb_typec_module_uninit(); + #endif /* USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE */ + return ret_code; #endif /* defined(USB_CFG_OTG_USE) */ } @@ -3798,6 +3814,59 @@ fsp_err_t R_USB_OtgSRP (usb_ctrl_t * const p_api_ctrl) #endif /* (BSP_CFG_RTOS == 1) */ } +/**************************************************************************//** + * @brief USB Type-C connect Information get. + * + * @retval FSP_SUCCESS Successful completion. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + ******************************************************************************/ +fsp_err_t R_USB_TypeCInfoGet (usb_ctrl_t * const p_api_ctrl, usb_typec_info_t * p_info) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + +#if (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) + + /* Set Connection State Mode */ + if (USB_TYPEC_MEC_MODE == (R_USBCC->MEC & USB_TYPEC_MEC_MODE)) + { + p_info->operation_mode = USB_TYPEC_MODE_USB20_ONLY_SINK; /* USB 2.0 Only Sink Mode */ + } + else + { + p_info->operation_mode = USB_TYPEC_MODE_SINK; /* Sink Only Mode */ + } + + /* Set Connection of Plug Orientation */ + if (USB_TYPEC_TCS_PLUG == (g_usb_typec_reg_tcs & USB_TYPEC_TCS_PLUG)) + { + p_info->plug = USB_TYPEC_PLUG_CC2_CONNECTED; /* CC2 connected */ + } + else + { + p_info->plug = USB_TYPEC_PLUG_CC1_CONNECTED; /* CC1 connected */ + } + + /* Set Status of VBUS */ + if (USB_TYPEC_TCS_VBUSS == (g_usb_typec_reg_tcs & USB_TYPEC_TCS_VBUSS)) + { + p_info->vbus_status = USB_TYPEC_VBUS_STATUS_ON; /* VBUS On State */ + } + else + { + p_info->vbus_status = USB_TYPEC_VBUS_STATUS_OFF; /* VBUS Off State */ + } + + /* Set Status of Connection State Machine */ + p_info->connection_status = (g_usb_typec_reg_tcs & USB_TYPEC_TCS_CNS_MASK) >> 4; + + return FSP_SUCCESS; +#else /* USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE */ + FSP_PARAMETER_NOT_USED(p_info); + + return FSP_ERR_USB_FAILED; +#endif /* USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE */ +} + /*******************************************************************************************************************//** * @} (end addtogroup USB) **********************************************************************************************************************/ diff --git a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h index 464256b68..dd14b42d8 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h +++ b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h @@ -31,111 +31,96 @@ extern "C" { /********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ - #if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA8M1) || defined(BSP_MCU_GROUP_RA8D1) + #if (BSP_FEATURE_USB_HAS_USBFS == 1) && (BSP_FEATURE_USB_HAS_USBHS == 1) #define USB_HIGH_SPEED_MODULE - #define USB_IP0_MODULE USB_FS_MODULE - #define USB_IP1_MODULE USB_HS_MODULE + #define USB_IP0_MODULE USB_FS_MODULE + #define USB_IP1_MODULE USB_HS_MODULE - #define USB_NUM_USBIP (2U) + #define USB_NUM_USBIP (2U) - #endif /* defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) */ - - #if defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA6E2) || defined(BSP_MCU_GROUP_RA6T3) || \ - defined(BSP_MCU_GROUP_RA4E2) || defined(BSP_MCU_GROUP_RA6E1) || defined(BSP_MCU_GROUP_RA4E1) \ - || defined(BSP_MCU_GROUP_RA4M1) || defined(BSP_MCU_GROUP_RA4M2) || defined(BSP_MCU_GROUP_RA4M3) \ - || defined(BSP_MCU_GROUP_RA4W1) || defined(BSP_MCU_GROUP_RA6M1) || defined(BSP_MCU_GROUP_RA6M2) \ - || defined(BSP_MCU_GROUP_RA6M4) || defined(BSP_MCU_GROUP_RA8T1) + #endif - #define USB_IP0_MODULE USB_FS_MODULE - #define USB_IP1_MODULE USB_NOT_SUPPORT + #if (BSP_FEATURE_USB_HAS_USBFS == 1) && (BSP_FEATURE_USB_HAS_USBHS == 0) + #define USB_IP0_MODULE USB_FS_MODULE + #define USB_IP1_MODULE USB_NOT_SUPPORT - #define USB_NUM_USBIP (1U) - #endif /* defined(BSP_MCU_GROUP_RA2A1 || defined(BSP_MCU_GROUP_RA6E2) || defined(BSP_MCU_GROUP_RA6T3) || defined(BSP_MCU_GROUP_RA4E2) */ + #define USB_NUM_USBIP (1U) + #endif - #if defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA6E2) || defined(BSP_MCU_GROUP_RA6T3) || \ - defined(BSP_MCU_GROUP_RA4E2) + #if defined(__CM23_REV) - #define USB_SUPPORT_MINI_MODULE - #define USB_NOT_SUPPORT_HOST - #define USB_NOT_SUPPORT_DMAC + #define USB_UNALIGNED_MEMORY_ACCESS_NG_MCU /* Coretex M23 etc */ - #endif /* defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA6E2) || defined(BSP_MCU_GROUP_RA6T3) || defined(BSP_MCU_GROUP_RA4E2) */ + #endif - #if defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA4W1) + #if (BSP_FEATURE_USB_HAS_PIPE04567 == 1) - #define USB_SUPPORT_PERI_LS /* USB Peripheral Low-speed Support Module */ + #define USB_SUPPORT_MINI_MODULE - #endif /* defined(BSP_MCU_GROUP_RA2A1) */ + #endif - #if defined(BSP_MCU_GROUP_RA2A1) + #if (BSP_FEATURE_USB_HAS_NOT_HOST == 1) - #define USB_UNALIGNED_MEMORY_ACCESS_NG_MCU /* Coretex M23 etc */ + #define USB_NOT_SUPPORT_HOST - #endif /* defined(BSP_MCU_GROUP_RA2A1) */ + #endif - #if defined(BSP_MCU_GROUP_RA2A1) + #if (BSP_FEATURE_USB_HAS_USBLS_PERI == 1) - #define USB_SUPPORT_HOCO_MODULE /* UCKSELC bit */ + #define USB_SUPPORT_PERI_LS /* USB Peripheral Low-speed Support Module */ - #endif /* defined(BSP_MCU_GROUP_RA2A1) */ + #endif - #if defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA4M1) + #if (BSP_FEATURE_USB_REG_UCKSEL_UCKSELC == 1) - #define USB_LDO_REGULATOR_MODULE /* VDCEN bit */ + #define USB_SUPPORT_HOCO_MODULE /* UCKSELC bit */ - #endif /* (BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA4M1) */ + #endif - #if defined(BSP_MCU_GROUP_RA4M1) || defined(BSP_MCU_GROUP_RA4W1) || defined(BSP_MCU_GROUP_RA2A1) + #if (BSP_FEATURE_USB_REG_USBMC_VDCEN == 1) - #define USB_SUPPORT_VDDUSBE /* VDDUSBE bit */ + #define USB_LDO_REGULATOR_MODULE /* VDCEN bit */ - #endif /* defined(BSP_MCU_GROUP_RA4M1) || defined(BSP_MCU_GROUP_RA4W1) || defined(BSP_MCU_GROUP_RA2A1) */ + #endif - #if defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M2) || defined(BSP_MCU_GROUP_RA6M1) + #if (BSP_FEATURE_USB_REG_USBMC_VDDUSBE == 1) - #define USB_SUPPORT_PHYSLEW /* PHYSLEW bit */ + #define USB_SUPPORT_VDDUSBE /* VDDUSBE bit */ - #endif /* defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M2) || defined(BSP_MCU_GROUP_RA6M1) */ + #endif - #if defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M2) || defined(BSP_MCU_GROUP_RA6M1) + #if (BSP_FEATURE_USB_REG_PHYSLEW == 1) - #define USB_PHYSLEW_VALUE (0xEU) + #define USB_SUPPORT_PHYSLEW /* PHYSLEW bit */ + #define USB_PHYSLEW_VALUE BSP_FEATURE_USB_REG_PHYSLEW_VALUE - #endif /* defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M2) || defined(BSP_MCU_GROUP_RA6M1) */ + #endif - #if defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8) + #if (BSP_FEATURE_USB_HAS_USBHS_BC == 1) - #define USB_CNEN_SYSCFG_USB_IP1 /* CNEN bit */ - #define USB_SUPPORT_BC_HS /* Battery Charging in High-speed module */ + #define BSP_FEATURE_USBHS_REG_SYSCFG_CNEN /* CNEN bit */ + #define USB_SUPPORT_BC_HS /* Battery Charging in High-speed module */ - #endif /* defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8) */ + #endif - #if defined(BSP_MCU_GROUP_RA2A1) + #if (BSP_FEATURE_USB_HAS_USBFS_BC == 1) - #define USB_CNEN_SYSCFG_USB_IP0 /* CNEN bit */ #define USB_SUPPORT_BC_FS /* Battery Charging in Full-speed module*/ - #endif /* defined(USB_SUPPORT_MINI_MODULE) */ /* defined(BSP_MCU_GROUP_RA2A1 */ + #endif - #if defined(BSP_MCU_GROUP_RA6E2) || defined(BSP_MCU_GROUP_RA6T3) || defined(BSP_MCU_GROUP_RA4E2) \ - || defined(BSP_MCU_GROUP_RA4M1) || defined(BSP_MCU_GROUP_RA4M2) || defined(BSP_MCU_GROUP_RA4M3) \ - || defined(BSP_MCU_GROUP_RA4W1) || defined(BSP_MCU_GROUP_RA6M5) \ - || defined(BSP_MCU_GROUP_RA6M4) || defined(BSP_MCU_GROUP_RA6E1) || defined(BSP_MCU_GROUP_RA4E1) + #if (BSP_FEATURE_USB_REG_PHYSECTRL_CNEN == 1) #define USB_CNEN_PHYSECTRL_USB_IP0 /* CNEN bit */ - #if defined(BSP_MCU_GROUP_RA6M5) - #define USB_SUPPORT_BC_HS /* Battery Charging in High-speed module */ - #define USB_SUPPORT_BC_FS /* Battery Charging in Full-speed module */ - #endif /* defined(BSP_MCU_GROUP_RA6M5) */ + #endif + + #if (BSP_FEATURE_USB_HAS_TYPEC == 1) - #if defined(BSP_MCU_GROUP_RA4M1) || defined(BSP_MCU_GROUP_RA4M2) || defined(BSP_MCU_GROUP_RA4M3) \ - || defined(BSP_MCU_GROUP_RA4W1) || defined(BSP_MCU_GROUP_RA6M4) || defined(BSP_MCU_GROUP_RA6E1) || \ - defined(BSP_MCU_GROUP_RA4E1) - #define USB_SUPPORT_BC_FS - #endif /* defined(BSP_MCU_GROUP_RA4M1) || defined(BSP_MCU_GROUP_RA4M2) || defined(BSP_MCU_GROUP_RA4M3) */ - #endif /* defined(BSP_MCU_GROUP_RA6E2) || defined(BSP_MCU_GROUP_RA6T3) || defined(BSP_MCU_GROUP_RA4E2) */ + #define USB_SUPPORT_TYPEC /* USB Type-C Support Module */ + + #endif /* Version Number of API. */ #define USB_VERSION_MAJOR (1) @@ -314,11 +299,7 @@ extern "C" { #define USB_M1 (R_USB_HS0) #else /* R_USB_HS0 */ #ifndef R_USB_HS0_BASE - #if defined(BSP_MCU_GROUP_RA4M3) || defined(BSP_MCU_GROUP_RA6M4) - #define R_USB_HS0_BASE (0x40111000) - #else /* defined(BSP_MCU_GROUP_RA4M3) || defined(BSP_MCU_GROUP_RA6M4) */ - #define R_USB_HS0_BASE (0x40060000) - #endif /* defined(BSP_MCU_GROUP_RA4M3) || defined(BSP_MCU_GROUP_RA6M4) */ + #define R_USB_HS0_BASE (0x40060000) #endif /* R_USB_HS0_BASE */ #define USB_M1 (((R_USB_FS0_Type *) R_USB_HS0_BASE)) diff --git a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_extern.h b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_extern.h index 65c3b00e5..3d0ee6f40 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_extern.h +++ b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_extern.h @@ -188,6 +188,9 @@ extern volatile uint8_t g_usb_otg_hnp_counter; extern TX_TIMER g_usb_otg_hnp_timer; #endif /* defined(USB_CFG_OTG_USE) */ +/* USB Type-C */ +extern uint32_t g_usb_typec_reg_tcs; + /***************************************************************************** * Public Functions ******************************************************************************/ diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdrequest.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdrequest.c index 1ef0ccc06..28ae9d032 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdrequest.c +++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdrequest.c @@ -1679,6 +1679,7 @@ static void usb_peri_class_request_usbx (usb_setup_t * p_req) FSP_SETUP_VALUE) = p_req->request_value; *(uint16_t *) (transfer_request->ux_slave_transfer_request_setup + FSP_SETUP_LENGTH) = p_req->request_length; + transfer_request->ux_slave_transfer_request_actual_length = p_req->request_length - g_usb_pstd_data_cnt[USB_PIPE0]; #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE) *(transfer_request->ux_slave_transfer_request_setup + FSP_SETUP_REQUEST_TYPE) = (uint8_t) (p_req->request_type & VALUE_FFH); @@ -1915,8 +1916,12 @@ void usb_peri_class_request_wnss (usb_setup_t * req, usb_utr_t * p_utr) /* Is a request receive target Interface? */ if (USB_INTERFACE == (req->request_type & USB_BMREQUESTTYPERECIP)) { + #if (BSP_CFG_RTOS == 1) if ((USB_MASS_STORAGE_RESET == (req->request_type & USB_BREQUEST)) || (USB_PCDC_SET_CONTROL_LINE_STATE == (req->request_type & USB_BREQUEST))) + #else + if (USB_MASS_STORAGE_RESET == (req->request_type & USB_BREQUEST)) + #endif /* (BSP_CFG_RTOS == 1) */ { #if (BSP_CFG_RTOS == 1) usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); @@ -1942,7 +1947,12 @@ void usb_peri_class_request_wnss (usb_setup_t * req, usb_utr_t * p_utr) usb_pstd_set_stall_pipe0(p_utr); /* Req Error */ } + #if (BSP_CFG_RTOS == 1) + if ((USB_MASS_STORAGE_RESET != (req->request_type & USB_BREQUEST)) && + (USB_PCDC_SET_CONTROL_LINE_STATE != (req->request_type & USB_BREQUEST))) + #else if (USB_MASS_STORAGE_RESET != (req->request_type & USB_BREQUEST)) + #endif /* (BSP_CFG_RTOS == 1) */ { usb_pstd_ctrl_end((uint16_t) USB_CTRL_END, p_utr); /* End control transfer. */ } diff --git a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h index b57db8721..8e8db0638 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h +++ b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h @@ -478,6 +478,66 @@ extern "C" { #define NRDYSTS_MASK (0x03FFU) /* NRDYSTS Reserved bit mask */ #define BEMPSTS_MASK (0x03FFU) /* BEMPSTS Reserved bit mask */ +/**************************************************************************************************/ + +/* USB TypeC module bit define */ + +/* TCC (Type C Control) Register */ + #define USB_TYPEC_TCC_ENB (0x00000001U) /* b0 : Connection State Machine Enable */ + #define USB_TYPEC_TCC_RESET (0x80000000U) /* b31: Type C Software Reset */ + +/* MEC (Mode Setting and State Control) Register */ + #define USB_TYPEC_MEC_MODE (0x00000001U) /* b0 : Connection State Machine Enable */ + #define USB_TYPEC_MEC_PMODE_MASK (0x00000006U) /* b2-b1 : Source Current Detection Mode */ + #define USB_TYPEC_MEC_PMODE_DEFAULT (0x00000000U) /* Detect Default USB Source */ + #define USB_TYPEC_MEC_PMODE_DEFAULT_15A (0x00000002U) /* Detect Default USB Source and 1.5A Source */ + #define USB_TYPEC_MEC_PMODE_DEFAULT_15A_30A (0x00000004U) /* Detect Default USB Source, 15A and 3.0A Source */ + #define USB_TYPEC_MEC_GD (0x00010000U) /* b16 : Direct Connection State to Disable State */ + #define USB_TYPEC_MEC_GUS (0x00020000U) /* b17 : Direct Connection State to Unattached_SNK */ + +/* CCC (CC-PHY Control) Register */ + #define USB_TYPEC_CCC_RD (0x00000001U) /* b0 : RD Control */ + #define USB_TYPEC_CCC_ZOPEN (0x00000002U) /* b1 : zOpen Control */ + #define USB_TYPEC_CCC_CCSEL (0x00000100U) /* b8 : Selection of CC */ + #define USB_TYPEC_CCC_VRAEN (0x00010000U) /* b16 : vRa Detection Circuit Enable */ + #define USB_TYPEC_CCC_VRD15EN (0x00020000U) /* b17 : vRd-1.5 Detection Circuit Enable */ + #define USB_TYPEC_CCC_VRD30EN (0x00040000U) /* b18 : vRd-3.0 Detection Circuit Enable */ + #define USB_TYPEC_CCC_PDOWN (0x80000000U) /* b31 : CC-PHY Power Down Control */ + +/* IES (Interrupt Enable Control and Status) Register */ + #define USB_TYPEC_IES_ISCN (0x00000001U) /* b0 : Interrupt Status of Connection */ + #define USB_TYPEC_IES_ISCC (0x00000010U) /* b4 : Interrupt Status of CC */ + #define USB_TYPEC_IES_ISVBUS (0x00000020U) /* b5 : Interrupt Status of VBUS */ + #define USB_TYPEC_IES_ISVRA (0x00008000U) /* b15 : Interrupt Status of VRA */ + #define USB_TYPEC_IES_CIEN (0x00010000U) /* b16 : CC Interrupt Enable */ + #define USB_TYPEC_IES_CCIEN (0x00100000U) /* b20 : CC Interrupt Enable */ + #define USB_TYPEC_IES_VBUSIEN (0x00200000U) /* b21 : VBUS Interrupt Enable */ + #define USB_TYPEC_IES_VRAIEN (0x80000000U) /* b31 : VRA Interrupt Enable */ + +/* TCS (Type-CC Connection State and Status) Register */ + #define USB_TYPEC_TCS_SRCD (0x00000001U) /* b0 : Interrupt Status of Connection */ + #define USB_TYPEC_TCS_VRD15D (0x00000002U) /* b1 : Interrupt Status of CC (Power1.5 Source is Detected) */ + #define USB_TYPEC_TCS_VRD30D (0x00000004U) /* b2 : Interrupt Status of CC (Power3.0 Source is Detected) */ + #define USB_TYPEC_TCS_PLUG (0x00000008U) /* b3 : Connection of Plug Orientation */ + #define USB_TYPEC_TCS_CNS_MASK (0x000000F0U) /* b7-b4: CC Interrupt Enable */ + #define USB_TYPEC_TCS_CNS_DEFAULT (0x00000000U) /* Disabled */ + #define USB_TYPEC_TCS_CNS_UNATTACHED (0x00000010U) /* Unattached.SNK */ + #define USB_TYPEC_TCS_CNS_ATTACHED_WAIT (0x00000020U) /* AttachedWait.SNK */ + #define USB_TYPEC_TCS_CNS_ATTACHED_DEFAULT (0x00000040U) /* Attache.SNK (PowerDefault.SNK) */ + #define USB_TYPEC_TCS_CNS_ATTACHED_15 (0x00000050U) /* Attache.SNK (Power1.5.SNK) */ + #define USB_TYPEC_TCS_CNS_ATTACHED_30 (0x00000060U) /* Attache.SNK (Power3.0.SNK) */ + #define USB_TYPEC_TCS_CC1S_MASK (0x00000300U) /* b9-b8: Status of CC1 */ + #define USB_TYPEC_TCS_CC1S_OPEN (0x00000000U) /* SNK.Open */ + #define USB_TYPEC_TCS_CC1S_DEFAULT (0x00000100U) /* SNK.Default */ + #define USB_TYPEC_TCS_CC1S_15 (0x00000200U) /* SNK.Power1.5 */ + #define USB_TYPEC_TCS_CC1S_30 (0x00000300U) /* SNK.Power3.0 */ + #define USB_TYPEC_TCS_CC2S_MASK (0x00000C00U) /* b11-b10: Status of CC2 */ + #define USB_TYPEC_TCS_CC2S_OPEN (0x00000000U) /* b11-b10: Status of CC2 */ + #define USB_TYPEC_TCS_CC2S_DEFAULT (0x00000400U) /* SNK.Default */ + #define USB_TYPEC_TCS_CC2S_15 (0x00000800U) /* SNK.Power1.5 */ + #define USB_TYPEC_TCS_CC2S_30 (0x00000C00U) /* SNK.Power3.0 */ + #define USB_TYPEC_TCS_VBUSS (0x00001000U) /* Status of VBUS */ + #ifdef __cplusplus } #endif diff --git a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h index 7c3410c01..767bd4209 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h +++ b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h @@ -49,9 +49,9 @@ extern "C" { #define USB1_D0FIFO32 (USB_M1->D0FIFO) #define USB1_D1FIFO32 (USB_M1->D1FIFO) - #if (defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA4M1)) + #if defined(USB_LDO_REGULATOR_MODULE) #define USB_LDO_REGULATOR_MODULE - #endif /* (defined(USB_LDO_REGULATOR_MODULE) && (USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE)) */ + #endif /* USB_LDO_REGULATOR_MODULE */ /****************/ /* INITIARIZE */ @@ -375,19 +375,21 @@ void hw_usb_write_pipetrn(usb_utr_t * ptr, uint16_t pipeno, uint16_t data); /************/ /* BCCTRL */ /************/ -void hw_usb_set_bcctrl(usb_utr_t * ptr, uint16_t data); -void hw_usb_clear_bcctrl(usb_utr_t * ptr, uint16_t data); -uint16_t hw_usb_read_bcctrl(usb_utr_t * ptr); -void hw_usb_set_vdmsrce(usb_utr_t * ptr); -void hw_usb_clear_vdmsrce(usb_utr_t * ptr); -void hw_usb_set_idpsinke(usb_utr_t * ptr); -void hw_usb_set_suspendm(uint8_t usb_ip); -void hw_usb_clear_suspm(uint8_t usb_ip); -void hw_usb_clear_idpsinke(usb_utr_t * ptr); -void hw_usb_set_vdcen(void); -void hw_usb_clear_vdcen(void); -void hw_usb_set_uckselc(void); -void hw_usb_clear_uckselc(void); +void hw_usb_set_bcctrl(usb_utr_t * ptr, uint16_t data); +void hw_usb_clear_bcctrl(usb_utr_t * ptr, uint16_t data); +uint16_t hw_usb_read_bcctrl(usb_utr_t * ptr); +void hw_usb_set_vdmsrce(usb_utr_t * ptr); +void hw_usb_clear_vdmsrce(usb_utr_t * ptr); +void hw_usb_set_idpsinke(usb_utr_t * ptr); +void hw_usb_set_suspendm(uint8_t usb_ip); +void hw_usb_clear_suspm(uint8_t usb_ip); +void hw_usb_clear_idpsinke(usb_utr_t * ptr); +void hw_usb_set_vdcen(void); +void hw_usb_clear_vdcen(void); +void hw_usb_set_uckselc(void); +void hw_usb_clear_uckselc(void); +fsp_err_t hw_usb_typec_module_init(void); +void hw_usb_typec_module_uninit(void); #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) void hw_usb_hset_dcpmode(usb_utr_t * ptr); diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c index c6f027df7..556263e54 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c +++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c @@ -3804,7 +3804,7 @@ void hw_usb_clear_idpsinke (usb_utr_t * ptr) { #if defined(USB_HIGH_SPEED_MODULE) ptr->ipp1->BCCTRL = (uint16_t) (ptr->ipp1->BCCTRL & (~USB_IDPSINKE)); - #endif /* defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M5) */ + #endif /* vdefined (USB_HIGH_SPEED_MODULE) */ } } @@ -3927,6 +3927,73 @@ void hw_usb_clear_uckselc (void) #endif /* defined(USB_SUPPORT_HOCO_MODULE) */ +#if (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) + +/****************************************************************************** + * Function Name : hw_usb_typec_module_init + * Description : Initialization of USB TypeC module + * Arguments : none + * @retval FSP_SUCCESS Success. + * @retval FSP_ERR_USB_BUSY USB is in use. + ******************************************************************************/ +fsp_err_t hw_usb_typec_module_init (void) +{ + #if defined(USB_SUPPORT_TYPEC) && (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) + FSP_ERROR_RETURN(0 != R_MSTP->MSTPCRB_b.MSTPB14, FSP_ERR_USB_BUSY) + + /* Enable module start for TypeC module */ + R_BSP_MODULE_START(FSP_IP_USBCC, 0); + + /* Type-C Reset Processing */ + R_USBCC->TCC |= USB_TYPEC_TCC_RESET; + while (0 != (R_USBCC->TCC & USB_TYPEC_TCC_RESET)) + { + ; + } + + /* CC1 and CC2 pin setting */ + + /* CCC-PHY not Power Down */ + R_USBCC->CCC = (R_USBCC->CCC & (~USB_TYPEC_CCC_PDOWN)); + + /* Change to Unattached_SNK */ + R_USBCC->MEC |= USB_TYPEC_MEC_GUS; + #endif /* defined(USB_SUPPORT_TYPEC) && (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) */ + + return FSP_SUCCESS; +} + +/****************************************************************************** + * End of function hw_usb_typec_module_init + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_typec_module_uninit + * Description : Uninitialization of USB TypeC module + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_typec_module_uninit (void) +{ + #if defined(USB_SUPPORT_TYPEC) && (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) + + /* Change to Unattached_SNK */ + R_USBCC->MEC |= USB_TYPEC_MEC_GD; + + /* CCC-PHY Power Down */ + R_USBCC->CCC |= USB_TYPEC_CCC_PDOWN; + + /* Disable module start for TypeC module */ + R_BSP_MODULE_STOP(FSP_IP_USBCC, 0); + #endif /* defined(USB_SUPPORT_TYPEC) && (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) */ +} + +/****************************************************************************** + * End of function hw_usb_typec_module_uninit + ******************************************************************************/ + +#endif /* USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE */ + /****************************************************************************** * End of file ******************************************************************************/ diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c index be5b8be0d..540bd4fe5 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c +++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c @@ -834,7 +834,7 @@ void hw_usb_hmodule_init (uint8_t usb_ip) else { #if defined(USB_HIGH_SPEED_MODULE) - USB_M1->PHYSET = (USB_DIRPD | USB_PLLRESET | USB_CLKSEL); + USB_M1->PHYSET = (USB_DIRPD | USB_CLKSEL); #if USB_CFG_CLKSEL == USB_CFG_48MHZ USB_M1->PHYSET &= (uint16_t) ~USB_CLKSEL; diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c index df7d52d2f..29b39220e 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c +++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c @@ -111,6 +111,11 @@ void usbhs_interrupt_handler(void); void usbhs_d0fifo_handler(void); void usbhs_d1fifo_handler(void); +#if (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) +void usb_typec_interrupt_handler(void); + +#endif /* USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE */ + #if defined(USB_CFG_OTG_USE) static usb_utr_t g_usb_irq_otg_msg; static usb_utr_t g_usb_otg_detach_msg; @@ -128,6 +133,10 @@ static uint16_t g_usb_hstd_m1_reg_intenb1; #endif /* defined(USB_HIGH_SPEED_MODULE) */ #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ +#if (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) +uint32_t g_usb_typec_reg_tcs; +#endif /* USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE */ + /****************************************************************************** * Renesas Abstracted RSK functions ******************************************************************************/ @@ -329,7 +338,7 @@ void usb_cpu_usbint_init (uint8_t ip_type, usb_cfg_t const * const cfg) { if (USB_IP0 == ip_type) { -#if (!defined(BSP_MCU_GROUP_RA4M1)) && (!defined(BSP_MCU_GROUP_RA2A1)) +#if (!defined(USB_LDO_REGULATOR_MODULE)) /* Deep standby USB monitor register * b0 SRPC0 USB0 single end control @@ -350,7 +359,7 @@ void usb_cpu_usbint_init (uint8_t ip_type, usb_cfg_t const * const cfg) * b31-b24 Reserved 0 */ USB_M0->DPUSR0R_FS_b.FIXPHY0 = 0U; /* USB0 Transceiver Output fixed */ -#endif /* (!defined(BSP_MCU_GROUP_RA4M1)) && (!defined(BSP_MCU_GROUP_RA2A1)) */ +#endif /* !defined(USB_LDO_REGULATOR_MODULE) */ /* Interrupt enable register * b0 IEN0 Interrupt enable bit @@ -425,6 +434,13 @@ void usb_cpu_usbint_init (uint8_t ip_type, usb_cfg_t const * const cfg) #endif /*((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST)*/ #endif /* defined (USB_HIGH_SPEED_MODULE) */ } + +#if (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) + if (cfg->irq_typec >= 0) + { + R_BSP_IrqCfgEnable(cfg->irq_typec, cfg->ipl_typec, (void *) cfg); /* USBCC CCI enable */ + } +#endif /* USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE */ } /****************************************************************************** @@ -916,6 +932,29 @@ static void usbfs_usbi_isr (void) * End of function usbfs_usbi_isr ******************************************************************************/ +#if (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) + +/******************************************************************************* + * Function Name: usb_typec_isr + * Description : Interrupt service routine of USB TypeC + * Arguments : none + * Return Value : none + *******************************************************************************/ +static void usb_typec_isr (void) +{ + if (USB_TYPEC_IES_ISCN == (R_USBCC->IES & USB_TYPEC_IES_ISCN)) + { + R_USBCC->IES = (R_USBCC->IES | USB_TYPEC_IES_ISCN); + g_usb_typec_reg_tcs = R_USBCC->TCS; + USB_M0->INTENB0 |= USB_VBSE; + } +} + +/****************************************************************************** + * End of function usb_typec_isr + ******************************************************************************/ +#endif /* USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE */ + #if defined(USB_HIGH_SPEED_MODULE) /******************************************************************************* @@ -1175,6 +1214,23 @@ void usbhs_d1fifo_handler (void) FSP_CONTEXT_RESTORE } +#if (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) +void usb_typec_interrupt_handler (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + usb_typec_isr(); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif /* USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE */ + /****************************************************************************** * End Of File ******************************************************************************/ diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_abs.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_abs.c index 4a7568791..0d1ed0024 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_abs.c +++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_abs.c @@ -490,10 +490,10 @@ uint8_t * usb_pstd_write_fifo (uint16_t count, uint16_t pipemode, uint8_t * writ uint16_t hs_flag = 0; #endif /* defined (USB_HIGH_SPEED_MODULE) */ - #if defined(BSP_MCU_GROUP_RA2A1) + #if defined(USB_UNALIGNED_MEMORY_ACCESS_NG_MCU) /* The value of "write_p" is odd */ - if (USB_ODD == (write_p && USB_ODD)) + if (USB_ODD == ((uint32_t) write_p & USB_ODD)) { /* 8bit access */ /* write_p == odd */ @@ -510,7 +510,7 @@ uint8_t * usb_pstd_write_fifo (uint16_t count, uint16_t pipemode, uint8_t * writ return write_p; } - #endif /* defined(BSP_MCU_GROUP_RA2A1) */ + #endif /* defined(USB_UNALIGNED_MEMORY_ACCESS_NG_MCU) */ if ((USB_CFG_IP0 == p_utr->ip) || (0 == hs_flag)) { @@ -616,10 +616,10 @@ uint8_t * usb_pstd_read_fifo (uint16_t count, uint16_t pipemode, uint8_t * read_ uint16_t hs_flag = 0; #endif /* defined (USB_HIGH_SPEED_MODULE) */ - #if defined(BSP_MCU_GROUP_RA2A1) + #if defined(USB_UNALIGNED_MEMORY_ACCESS_NG_MCU) /* The value of "read_p" is odd */ - if (USB_ODD == (read_p && USB_ODD)) + if (USB_ODD == ((uint32_t) read_p & USB_ODD)) { /* 8bit access */ /* read_p == odd */ @@ -636,7 +636,7 @@ uint8_t * usb_pstd_read_fifo (uint16_t count, uint16_t pipemode, uint8_t * read_ return read_p; } - #endif /* defined(BSP_MCU_GROUP_RA2A1) */ + #endif /* defined(USB_UNALIGNED_MEMORY_ACCESS_NG_MCU) */ if ((USB_CFG_IP0 == p_utr->ip) || (0 == hs_flag)) { diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c index e1b92233a..a8a60a7c7 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c +++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c @@ -241,12 +241,16 @@ void hw_usb_pmodule_init (uint8_t usb_ip) USB_M0->D1FIFOSEL |= USB_BIGEND; #endif /* USB_CFG_ENDIAN == USB_CFG_BIG */ + #if defined(USB_SUPPORT_TYPEC) && (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) + USB_M0->INTENB0 = (USB_BEMPE | USB_BRDYE | USB_DVSE | USB_CTRE); + #else /* defined(USB_SUPPORT_TYPEC) && (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) */ USB_M0->INTENB0 = (USB_BEMPE | USB_BRDYE | USB_VBSE | USB_DVSE | USB_CTRE); + #endif /* defined(USB_SUPPORT_TYPEC) && (USB_CFG_TYPEC_FEATURE == USB_CFG_ENABLE) */ } else { #if defined(USB_HIGH_SPEED_MODULE) - USB_M1->PHYSET = (USB_DIRPD | USB_PLLRESET | USB_CLKSEL); + USB_M1->PHYSET = (USB_DIRPD | USB_CLKSEL); #if USB_CFG_CLKSEL == USB_CFG_48MHZ USB_M1->PHYSET &= (uint16_t) ~USB_CLKSEL; diff --git a/ra/fsp/src/r_usb_hcdc/src/r_usb_hcdc_driver.c b/ra/fsp/src/r_usb_hcdc/src/r_usb_hcdc_driver.c index e1b9862de..ba9a86d49 100644 --- a/ra/fsp/src/r_usb_hcdc/src/r_usb_hcdc_driver.c +++ b/ra/fsp/src/r_usb_hcdc/src/r_usb_hcdc_driver.c @@ -886,6 +886,8 @@ uint16_t usb_hcdc_get_string_info (usb_utr_t * mess, uint16_t addr, uint16_t str /* Condition compilation by the difference of useful function */ #if defined(USB_DEBUG_ON) + uint8_t p_data[USB_VALUE_32 + 2]; + uint16_t j; for (j = (uint16_t) 0; j < g_usb_hstd_class_data[mess->ip][0]; j++) { p_data[j] = g_usb_hstd_class_data[mess->ip][j * (uint16_t) 2 + (uint16_t) 2]; diff --git a/ra/fsp/src/rm_at_transport_da16xxx_uart/rm_at_transport_da16xxx_uart.c b/ra/fsp/src/rm_at_transport_da16xxx_uart/rm_at_transport_da16xxx_uart.c index 96c24f4b6..61f204737 100644 --- a/ra/fsp/src/rm_at_transport_da16xxx_uart/rm_at_transport_da16xxx_uart.c +++ b/ra/fsp/src/rm_at_transport_da16xxx_uart/rm_at_transport_da16xxx_uart.c @@ -27,6 +27,13 @@ typedef sci_b_baud_setting_t rm_at_transport_da16xxx_baud_setting_t; #define RM_AT_TRANSPORT_DA16XXX_SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS SCI_B_UART_FLOW_CONTROL_HARDWARE_CTSRTS static fsp_err_t (* p_sci_uart_baud_calculate)(uint32_t, bool, uint32_t, struct st_sci_b_baud_setting_t * const) = &R_SCI_B_UART_BaudCalculate; +#elif (R_SAU0_BASE) + #include "r_sau_uart.h" +typedef sau_uart_instance_ctrl_t rm_at_transport_da16xxx_uart_instance_ctrl_t; +typedef sau_uart_extended_cfg_t at_transport_da16xxx_uart_extended_cfg_t; +typedef sau_uart_baudrate_setting_t rm_at_transport_da16xxx_baud_setting_t; +static fsp_err_t (* p_sau_uart_baud_calculate)(sau_uart_instance_ctrl_t * const, uint32_t, + sau_uart_baudrate_setting_t * const) = &R_SAU_UART_BaudCalculate; #else #include "r_sci_uart.h" typedef sci_uart_instance_ctrl_t rm_at_transport_da16xxx_uart_instance_ctrl_t; @@ -131,6 +138,9 @@ static rm_at_transport_da16xxx_baud_setting_t g_baud_setting = .baudrate_bits_b.bgdm = 0, .baudrate_bits_b.brr = 0, .baudrate_bits_b.mddr = 0, +#elif (R_SAU0_BASE) + .prs = 0, + .stclk = 0, #else .semr_baudrate_bits_b.brme = 0, .semr_baudrate_bits_b.abcse = 0, @@ -456,24 +466,47 @@ fsp_err_t rm_at_transport_da16xxx_uartOpen (at_transport_da16xxx_ctrl_t * const rm_at_transport_da16xxx_reset(p_instance_ctrl); p_instance_ctrl->open = AT_TRANSPORT_DA16XXX_UART_OPEN; + + uart0_cfg.p_extend = (void *) &uart0_cfg_extended; + uart0_cfg.p_callback = rm_at_transport_da16xxx_uart_callback; + uart0_cfg.p_context = p_instance_ctrl; + + /* Open UART */ + p_uart = p_instance_ctrl->uart_instance_objects[AT_TRANSPORT_DA16XXX_UART_INITIAL_PORT]; + err = p_uart->p_api->open(p_uart->p_ctrl, &uart0_cfg); + for (index = 0; index < UART_BAUD_MAX_CNT; index++) { curr_uart_baud = uart_baud_rates[index]; - - (*p_sci_uart_baud_calculate)(curr_uart_baud, AT_TRANSPORT_DA16XXX_DEFAULT_MODULATION, - AT_TRANSPORT_DA16XXX_DEFAULT_ERROR, &g_baud_setting); +#ifndef R_SAU0_BASE + (* p_sci_uart_baud_calculate)(curr_uart_baud, AT_TRANSPORT_DA16XXX_DEFAULT_MODULATION, + AT_TRANSPORT_DA16XXX_DEFAULT_ERROR, &g_baud_setting); uart0_cfg_extended.p_baud_setting = &g_baud_setting; uart0_cfg_extended.flow_control = RM_AT_TRANSPORT_DA16XXX_SCI_UART_FLOW_CONTROL_RTS; uart0_cfg_extended.flow_control_pin = (bsp_io_port_pin_t) AT_TRANSPORT_DA16XXX_BSP_PIN_PORT_INVALID; +#else + #if (0 == SAU_UART_CFG_FIXED_BAUDRATE_ENABLE) + (*p_sau_uart_baud_calculate)((rm_at_transport_da16xxx_uart_instance_ctrl_t *) p_uart->p_ctrl, curr_uart_baud, + &g_baud_setting); + + uart0_cfg_extended.p_baudrate = &g_baud_setting; + #else + FSP_PARAMETER_NOT_USED(g_baud_setting); + FSP_PARAMETER_NOT_USED(p_sau_uart_baud_calculate); + #endif +#endif + uart0_cfg.p_extend = (void *) &uart0_cfg_extended; - uart0_cfg.p_extend = (void *) &uart0_cfg_extended; - uart0_cfg.p_callback = rm_at_transport_da16xxx_uart_callback; - uart0_cfg.p_context = p_instance_ctrl; + if (index > 0) + { + uart0_cfg.p_callback = rm_at_transport_da16xxx_uart_callback; + uart0_cfg.p_context = p_instance_ctrl; - /* Open UART */ - p_uart = p_instance_ctrl->uart_instance_objects[AT_TRANSPORT_DA16XXX_UART_INITIAL_PORT]; - err = p_uart->p_api->open(p_uart->p_ctrl, &uart0_cfg); + /* Open UART */ + p_uart = p_instance_ctrl->uart_instance_objects[AT_TRANSPORT_DA16XXX_UART_INITIAL_PORT]; + err = p_uart->p_api->open(p_uart->p_ctrl, &uart0_cfg); + } if (FSP_SUCCESS != err) { @@ -710,7 +743,14 @@ fsp_err_t rm_at_transport_da16xxx_uart_atCommandSendThreadSafe (at_transport_da1 FSP_ERROR_RETURN(AT_TRANSPORT_DA16XXX_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); #endif - mutex_flag = (AT_TRANSPORT_DA16XXX_MUTEX_TX | AT_TRANSPORT_DA16XXX_MUTEX_RX); + if (p_at_cmd->p_expect_code == NULL) + { + mutex_flag = AT_TRANSPORT_DA16XXX_MUTEX_TX; + } + else + { + mutex_flag = (AT_TRANSPORT_DA16XXX_MUTEX_TX | AT_TRANSPORT_DA16XXX_MUTEX_RX); + } FSP_ERROR_RETURN(FSP_SUCCESS == rm_at_transport_da16xxx_uart_takeMutex(p_instance_ctrl, mutex_flag), FSP_ERR_WIFI_FAILED); @@ -720,6 +760,10 @@ fsp_err_t rm_at_transport_da16xxx_uart_atCommandSendThreadSafe (at_transport_da1 rm_at_transport_da16xxx_uart_giveMutex(p_instance_ctrl, mutex_flag); +#if (BSP_CFG_RTOS == 2) /* FreeRTOS */ + vTaskDelay(pdMS_TO_TICKS(AT_TRANSPORT_DA16XXX_TIMEOUT_1MS)); +#endif + /* Check response for 'OK' */ FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_FAILED); @@ -805,6 +849,10 @@ size_t rm_at_transport_da16xxx_uart_bufferRecv (at_transport_da16xxx_ctrl_t * co rm_at_transport_da16xxx_uart_giveMutex(p_instance_ctrl, mutex_flag); +#if (BSP_CFG_RTOS == 2) /* FreeRTOS */ + vTaskDelay(pdMS_TO_TICKS(AT_TRANSPORT_DA16XXX_TIMEOUT_1MS)); +#endif + return xReceivedBytes; } diff --git a/ra/fsp/src/rm_comms_i2c/rm_comms_i2c.c b/ra/fsp/src/rm_comms_i2c/rm_comms_i2c.c index 96a5845eb..d575c764e 100644 --- a/ra/fsp/src/rm_comms_i2c/rm_comms_i2c.c +++ b/ra/fsp/src/rm_comms_i2c/rm_comms_i2c.c @@ -108,8 +108,9 @@ fsp_err_t RM_COMMS_I2C_Open (rm_comms_ctrl_t * const p_api_ctrl, rm_comms_cfg_t p_ctrl->p_lower_level_cfg = (void *) p_cfg->p_lower_level_cfg; /* Set callback and context */ - p_ctrl->p_callback = p_cfg->p_callback; - p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->smbus_operation = false; /* Set open flag */ p_ctrl->open = RM_COMMS_I2C_OPEN; diff --git a/ra/fsp/src/rm_comms_i2c/rm_comms_i2c_driver_ra.c b/ra/fsp/src/rm_comms_i2c/rm_comms_i2c_driver_ra.c index 3bb20ba9f..b2005af3a 100644 --- a/ra/fsp/src/rm_comms_i2c/rm_comms_i2c_driver_ra.c +++ b/ra/fsp/src/rm_comms_i2c/rm_comms_i2c_driver_ra.c @@ -20,19 +20,23 @@ /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ -static void rm_comms_i2c_process_in_callback(rm_comms_ctrl_t * const p_api_ctrl, - rm_comms_callback_args_t * const p_args); static fsp_err_t rm_comms_i2c_bus_reconfigure(rm_comms_ctrl_t * const p_api_ctrl); #if BSP_CFG_RTOS -static fsp_err_t rm_comms_i2c_os_recursive_mutex_acquire(rm_comms_i2c_mutex_t const * p_mutex, uint32_t const timeout); -static fsp_err_t rm_comms_i2c_os_recursive_mutex_release(rm_comms_i2c_mutex_t const * p_mutex); static fsp_err_t rm_comms_i2c_os_semaphore_acquire(rm_comms_i2c_semaphore_t const * p_semaphore, uint32_t const timeout); static fsp_err_t rm_comms_i2c_os_semaphore_release_from_ISR(rm_comms_i2c_semaphore_t const * p_semaphore); #endif +/********************************************************************************************************************** + * Extern functions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Extern variables + **********************************************************************************************************************/ + /*********************************************************************************************************************** * Private global variables **********************************************************************************************************************/ @@ -41,6 +45,13 @@ fsp_err_t rm_comms_i2c_bus_read(rm_comms_ctrl_t * const p_api_ctrl, uint8_t * co fsp_err_t rm_comms_i2c_bus_write(rm_comms_ctrl_t * const p_api_ctrl, uint8_t * const p_src, uint32_t const bytes); fsp_err_t rm_comms_i2c_bus_write_read(rm_comms_ctrl_t * const p_api_ctrl, rm_comms_write_read_params_t const write_read_params); +void rm_comms_i2c_process_in_callback(rm_comms_ctrl_t * const p_api_ctrl, rm_comms_callback_args_t * const p_args); + +#if BSP_CFG_RTOS +fsp_err_t rm_comms_i2c_os_recursive_mutex_acquire(rm_comms_i2c_mutex_t const * p_mutex, uint32_t const timeout); +fsp_err_t rm_comms_i2c_os_recursive_mutex_release(rm_comms_i2c_mutex_t const * p_mutex); + +#endif /*********************************************************************************************************************** * Global variables @@ -87,27 +98,42 @@ fsp_err_t rm_comms_i2c_bus_read (rm_comms_ctrl_t * const p_api_ctrl, uint8_t * c FSP_ERROR_RETURN(FSP_SUCCESS == err, err); /* Clear transfer data */ - p_ctrl->p_transfer_data = NULL; - p_ctrl->transfer_data_bytes = 0; + if (!p_ctrl->smbus_operation) + { + p_ctrl->p_transfer_data = NULL; + p_ctrl->transfer_data_bytes = 0; + } + else + { + /* In case SMBus is used, store the destination buffer for PEC byte calculation at SMBus callback */ + p_ctrl->p_transfer_data = p_dest; + p_ctrl->transfer_data_bytes = bytes; + } /* Use RA I2C driver to read data */ err = p_driver_instance->p_api->read(p_driver_instance->p_ctrl, p_dest, bytes, false); - FSP_ERROR_RETURN(FSP_SUCCESS == err, err); #if BSP_CFG_RTOS - if (NULL != p_ctrl->p_bus->p_blocking_semaphore) + fsp_err_t sem_err = FSP_SUCCESS; + fsp_err_t mutex_err = FSP_SUCCESS; + if ((FSP_SUCCESS == err) && (NULL != p_ctrl->p_bus->p_blocking_semaphore)) { /* Acquire a semaphore for blocking */ - err = rm_comms_i2c_os_semaphore_acquire(p_ctrl->p_bus->p_blocking_semaphore, p_ctrl->p_cfg->semaphore_timeout); - FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + sem_err = rm_comms_i2c_os_semaphore_acquire(p_ctrl->p_bus->p_blocking_semaphore, + p_ctrl->p_cfg->semaphore_timeout); } if (NULL != p_ctrl->p_bus->p_bus_recursive_mutex) { /* Release a mutex for bus */ - err = rm_comms_i2c_os_recursive_mutex_release(p_ctrl->p_bus->p_bus_recursive_mutex); - FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + mutex_err = rm_comms_i2c_os_recursive_mutex_release(p_ctrl->p_bus->p_bus_recursive_mutex); } + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(FSP_SUCCESS == sem_err, sem_err); + FSP_ERROR_RETURN(FSP_SUCCESS == mutex_err, mutex_err); +#else + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); #endif return FSP_SUCCESS; @@ -134,22 +160,28 @@ fsp_err_t rm_comms_i2c_bus_write (rm_comms_ctrl_t * const p_api_ctrl, uint8_t * /* Use RA I2C driver to write data */ err = p_driver_instance->p_api->write(p_driver_instance->p_ctrl, p_src, bytes, false); - FSP_ERROR_RETURN(FSP_SUCCESS == err, err); #if BSP_CFG_RTOS - if (NULL != p_ctrl->p_bus->p_blocking_semaphore) + fsp_err_t sem_err = FSP_SUCCESS; + fsp_err_t mutex_err = FSP_SUCCESS; + if ((FSP_SUCCESS == err) && (NULL != p_ctrl->p_bus->p_blocking_semaphore)) { /* Acquire a semaphore for blocking */ - err = rm_comms_i2c_os_semaphore_acquire(p_ctrl->p_bus->p_blocking_semaphore, p_ctrl->p_cfg->semaphore_timeout); - FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + sem_err = rm_comms_i2c_os_semaphore_acquire(p_ctrl->p_bus->p_blocking_semaphore, + p_ctrl->p_cfg->semaphore_timeout); } if (NULL != p_ctrl->p_bus->p_bus_recursive_mutex) { /* Release a mutex for bus */ - err = rm_comms_i2c_os_recursive_mutex_release(p_ctrl->p_bus->p_bus_recursive_mutex); - FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + mutex_err = rm_comms_i2c_os_recursive_mutex_release(p_ctrl->p_bus->p_bus_recursive_mutex); } + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(FSP_SUCCESS == sem_err, sem_err); + FSP_ERROR_RETURN(FSP_SUCCESS == mutex_err, mutex_err); +#else + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); #endif return FSP_SUCCESS; @@ -180,22 +212,28 @@ fsp_err_t rm_comms_i2c_bus_write_read (rm_comms_ctrl_t * const p_api_ write_read_params.p_src, write_read_params.src_bytes, true); - FSP_ERROR_RETURN(FSP_SUCCESS == err, err); #if BSP_CFG_RTOS - if (NULL != p_ctrl->p_bus->p_blocking_semaphore) + fsp_err_t sem_err = FSP_SUCCESS; + fsp_err_t mutex_err = FSP_SUCCESS; + if ((FSP_SUCCESS == err) && (NULL != p_ctrl->p_bus->p_blocking_semaphore)) { /* Acquire a semaphore for blocking */ - err = rm_comms_i2c_os_semaphore_acquire(p_ctrl->p_bus->p_blocking_semaphore, p_ctrl->p_cfg->semaphore_timeout); - FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + sem_err = rm_comms_i2c_os_semaphore_acquire(p_ctrl->p_bus->p_blocking_semaphore, + p_ctrl->p_cfg->semaphore_timeout); } if (NULL != p_ctrl->p_bus->p_bus_recursive_mutex) { /* Release a mutex for bus */ - err = rm_comms_i2c_os_recursive_mutex_release(p_ctrl->p_bus->p_bus_recursive_mutex); - FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + mutex_err = rm_comms_i2c_os_recursive_mutex_release(p_ctrl->p_bus->p_bus_recursive_mutex); } + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(FSP_SUCCESS == sem_err, sem_err); + FSP_ERROR_RETURN(FSP_SUCCESS == mutex_err, mutex_err); +#else + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); #endif return FSP_SUCCESS; @@ -280,8 +318,7 @@ void rm_comms_i2c_callback (i2c_master_callback_args_t * p_args) /*******************************************************************************************************************//** * @brief Process in callback function. Release semaphores in RTOS and call user callback. **********************************************************************************************************************/ -static void rm_comms_i2c_process_in_callback (rm_comms_ctrl_t * const p_api_ctrl, - rm_comms_callback_args_t * const p_args) +void rm_comms_i2c_process_in_callback (rm_comms_ctrl_t * const p_api_ctrl, rm_comms_callback_args_t * const p_args) { rm_comms_i2c_instance_ctrl_t * p_ctrl = (rm_comms_i2c_instance_ctrl_t *) p_api_ctrl; @@ -334,7 +371,7 @@ static fsp_err_t rm_comms_i2c_bus_reconfigure (rm_comms_ctrl_t * const p_api_ctr /* Set callback function and current control block */ err = p_driver_instance->p_api->callbackSet(p_driver_instance->p_ctrl, - (void (*)(i2c_master_callback_args_t *))rm_comms_i2c_callback, + p_lower_level_cfg->p_callback, p_ctrl, NULL); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); @@ -351,7 +388,7 @@ static fsp_err_t rm_comms_i2c_bus_reconfigure (rm_comms_ctrl_t * const p_api_ctr * @retval FSP_SUCCESS successfully configured. * @retval FSP_ERR_INTERNAL RTOS internal error. *********************************************************************************************************************/ -static fsp_err_t rm_comms_i2c_os_recursive_mutex_acquire (rm_comms_i2c_mutex_t const * p_mutex, uint32_t const timeout) +fsp_err_t rm_comms_i2c_os_recursive_mutex_acquire (rm_comms_i2c_mutex_t const * p_mutex, uint32_t const timeout) { #if BSP_CFG_RTOS == 1 // ThreadX UINT status; @@ -372,7 +409,7 @@ static fsp_err_t rm_comms_i2c_os_recursive_mutex_acquire (rm_comms_i2c_mutex_t c * @retval FSP_SUCCESS successfully configured. * @retval FSP_ERR_INTERNAL RTOS internal error. *********************************************************************************************************************/ -static fsp_err_t rm_comms_i2c_os_recursive_mutex_release (rm_comms_i2c_mutex_t const * p_mutex) +fsp_err_t rm_comms_i2c_os_recursive_mutex_release (rm_comms_i2c_mutex_t const * p_mutex) { #if BSP_CFG_RTOS == 1 // ThreadX UINT status; diff --git a/ra/fsp/src/rm_comms_smbus/rm_comms_smbus.c b/ra/fsp/src/rm_comms_smbus/rm_comms_smbus.c new file mode 100644 index 000000000..686549e7c --- /dev/null +++ b/ra/fsp/src/rm_comms_smbus/rm_comms_smbus.c @@ -0,0 +1,874 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "rm_comms_smbus.h" +#include "rm_comms_i2c.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "OPEN" in ASCII, used to determine if middleware is open. */ +#define RM_COMMS_SMBUS_OPEN (0x4F50454EUL) // Open state + +/* This macro contains 32 data bytes + 1 command code byte + 2 count bytes + 1 PEC byte. Exclude 1 byte of slave + * address. */ +#define RM_COMMS_SMBUS_PROCESS_CALL_MAX_BYTE (RM_COMMS_SMBUS_TRANSMISSION_MAX_BYTES - 1U) + +/* This macro contains 32 data bytes + 1 command code byte + 1 count bytes + 1 PEC byte. Exclude 1 byte of slave + * address and and 1 count byte. */ +#define RM_COMMS_SMBUS_WRITE_MAX_BYTE (RM_COMMS_SMBUS_TRANSMISSION_MAX_BYTES - 2U) + +#define RM_COMMS_SMBUS_WRITE_OPERATION (0x0) +#define RM_COMMS_SMBUS_READ_OPERATION (0x1) + +#define RM_COMMS_SMBUS_CRC_SEED_VAL_0 (0U) // Seed value 0 for PEC byte calculation + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#define GPT_OPEN_FLAG (0x00475054ULL) +#define ELC_OPEN_FLAG (0x00454C43ULL) + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +__STATIC_INLINE void rm_comms_smbus_pec_byte_calculate(uint8_t const * p_data, uint32_t num_bytes, uint8_t * p_crc_val); +static fsp_err_t rm_comms_smbus_setup_timer(rm_comms_smbus_instance_ctrl_t * const p_ctrl); + +__STATIC_INLINE fsp_err_t rm_comms_smbus_update_mext_val(rm_comms_smbus_instance_ctrl_t * const p_ctrl); + +#if BSP_CFG_RTOS +__STATIC_INLINE fsp_err_t rm_comms_smbus_semaphore_err_handler(rm_comms_i2c_instance_ctrl_t * const p_ctrl, + fsp_err_t semphr_err); + +#endif + +/********************************************************************************************************************** + * Extern functions + **********************************************************************************************************************/ +extern fsp_err_t rm_comms_i2c_bus_status_check(rm_comms_ctrl_t * const p_api_ctrl); +extern fsp_err_t rm_comms_i2c_bus_read(rm_comms_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, + uint32_t const bytes); +extern fsp_err_t rm_comms_i2c_bus_write(rm_comms_ctrl_t * const p_api_ctrl, uint8_t * const p_src, + uint32_t const bytes); +extern fsp_err_t rm_comms_i2c_bus_write_read(rm_comms_ctrl_t * const p_api_ctrl, + rm_comms_write_read_params_t const write_read_params); +extern void rm_comms_i2c_process_in_callback(rm_comms_ctrl_t * const p_api_ctrl, + rm_comms_callback_args_t * const p_args); + +#if BSP_CFG_RTOS +extern fsp_err_t rm_comms_i2c_os_recursive_mutex_acquire(rm_comms_i2c_mutex_t const * p_mutex, uint32_t const timeout); +extern fsp_err_t rm_comms_i2c_os_recursive_mutex_release(rm_comms_i2c_mutex_t const * p_mutex); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* Store CRC 8-bit result as lookup table */ +uint8_t const g_crc_lookup_table[] = +{ + 0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, + 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d, + 0x70, 0x77, 0x7e, 0x79, 0x6c, 0x6b, 0x62, 0x65, + 0x48, 0x4f, 0x46, 0x41, 0x54, 0x53, 0x5a, 0x5d, + 0xe0, 0xe7, 0xee, 0xe9, 0xfc, 0xfb, 0xf2, 0xf5, + 0xd8, 0xdf, 0xd6, 0xd1, 0xc4, 0xc3, 0xca, 0xcd, + 0x90, 0x97, 0x9e, 0x99, 0x8c, 0x8b, 0x82, 0x85, + 0xa8, 0xaf, 0xa6, 0xa1, 0xb4, 0xb3, 0xba, 0xbd, + 0xc7, 0xc0, 0xc9, 0xce, 0xdb, 0xdc, 0xd5, 0xd2, + 0xff, 0xf8, 0xf1, 0xf6, 0xe3, 0xe4, 0xed, 0xea, + 0xb7, 0xb0, 0xb9, 0xbe, 0xab, 0xac, 0xa5, 0xa2, + 0x8f, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9d, 0x9a, + 0x27, 0x20, 0x29, 0x2e, 0x3b, 0x3c, 0x35, 0x32, + 0x1f, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0d, 0x0a, + 0x57, 0x50, 0x59, 0x5e, 0x4b, 0x4c, 0x45, 0x42, + 0x6f, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7d, 0x7a, + 0x89, 0x8e, 0x87, 0x80, 0x95, 0x92, 0x9b, 0x9c, + 0xb1, 0xb6, 0xbf, 0xb8, 0xad, 0xaa, 0xa3, 0xa4, + 0xf9, 0xfe, 0xf7, 0xf0, 0xe5, 0xe2, 0xeb, 0xec, + 0xc1, 0xc6, 0xcf, 0xc8, 0xdd, 0xda, 0xd3, 0xd4, + 0x69, 0x6e, 0x67, 0x60, 0x75, 0x72, 0x7b, 0x7c, + 0x51, 0x56, 0x5f, 0x58, 0x4d, 0x4a, 0x43, 0x44, + 0x19, 0x1e, 0x17, 0x10, 0x05, 0x02, 0x0b, 0x0c, + 0x21, 0x26, 0x2f, 0x28, 0x3d, 0x3a, 0x33, 0x34, + 0x4e, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5c, 0x5b, + 0x76, 0x71, 0x78, 0x7f, 0x6a, 0x6d, 0x64, 0x63, + 0x3e, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2c, 0x2b, + 0x06, 0x01, 0x08, 0x0f, 0x1a, 0x1d, 0x14, 0x13, + 0xae, 0xa9, 0xa0, 0xa7, 0xb2, 0xb5, 0xbc, 0xbb, + 0x96, 0x91, 0x98, 0x9f, 0x8a, 0x8d, 0x84, 0x83, + 0xde, 0xd9, 0xd0, 0xd7, 0xc2, 0xc5, 0xcc, 0xcb, + 0xe6, 0xe1, 0xe8, 0xef, 0xfa, 0xfd, 0xf4, 0xf3, +}; + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +rm_comms_api_t const g_comms_on_comms_smbus = +{ + .open = RM_COMMS_SMBUS_Open, + .read = RM_COMMS_SMBUS_Read, + .write = RM_COMMS_SMBUS_Write, + .writeRead = RM_COMMS_SMBUS_WriteRead, + .callbackSet = RM_COMMS_SMBUS_CallbackSet, + .close = RM_COMMS_SMBUS_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup RM_COMMS_SMBUS + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Opens and configures the SMBUS Comms module. Implements @ref rm_comms_api_t::open. + * + * @retval FSP_SUCCESS Communications Middle module successfully configured. + * @retval FSP_ERR_ASSERTION Null pointer, or one or more configuration options is invalid. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. This module can only be opened once. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + **********************************************************************************************************************/ +fsp_err_t RM_COMMS_SMBUS_Open (rm_comms_ctrl_t * const p_api_ctrl, rm_comms_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + rm_comms_smbus_instance_ctrl_t * p_ctrl = (rm_comms_smbus_instance_ctrl_t *) p_api_ctrl; + +#if RM_COMMS_SMBUS_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ERROR_RETURN(RM_COMMS_SMBUS_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + rm_comms_smbus_extended_cfg_t * p_smbus_extend_cfg = (rm_comms_smbus_extended_cfg_t *) p_cfg->p_extend; + +#if RM_COMMS_SMBUS_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_smbus_extend_cfg); + FSP_ASSERT(NULL != p_smbus_extend_cfg->p_comms_i2c_ctrl); + FSP_ASSERT(NULL != p_smbus_extend_cfg->p_comms_i2c_extend_cfg); + FSP_ASSERT(NULL != p_smbus_extend_cfg->p_comms_i2c_extend_cfg->p_driver_instance); + FSP_ASSERT(NULL != p_smbus_extend_cfg->p_comms_i2c_extend_cfg->p_elc); + FSP_ASSERT(NULL != p_smbus_extend_cfg->p_comms_i2c_extend_cfg->p_timer); + FSP_ASSERT(NULL != p_cfg->p_lower_level_cfg); +#endif + + p_ctrl->p_comms_i2c_ctrl = p_smbus_extend_cfg->p_comms_i2c_ctrl; + rm_comms_i2c_instance_ctrl_t * p_comms_i2c_ctrl = p_ctrl->p_comms_i2c_ctrl; + + p_comms_i2c_ctrl->p_cfg = p_cfg; + p_comms_i2c_ctrl->p_bus = p_smbus_extend_cfg->p_comms_i2c_extend_cfg; + p_comms_i2c_ctrl->p_callback = p_cfg->p_callback; + p_comms_i2c_ctrl->p_context = p_ctrl; + p_comms_i2c_ctrl->smbus_operation = true; + p_ctrl->p_context = p_cfg->p_context; + + /* Set lower level driver configuration */ + p_comms_i2c_ctrl->p_lower_level_cfg = (void *) p_cfg->p_lower_level_cfg; + +#if RM_COMMS_SMBUS_CFG_PARAM_CHECKING_ENABLE + + /* Ensure that IIC already opened */ + FSP_ERROR_RETURN(FSP_SUCCESS == rm_comms_i2c_bus_status_check(p_comms_i2c_ctrl), FSP_ERR_COMMS_BUS_NOT_OPEN); + + /* If both ELC and GPT instance pointers are not NULL, which mean SMBus is being used. Check open flag of ELC and + * GPT to ensure that those modules already opened. + */ + elc_instance_t * p_elc_instance = (elc_instance_t *) p_comms_i2c_ctrl->p_bus->p_elc; + timer_instance_t * p_timer_instance = (timer_instance_t *) p_comms_i2c_ctrl->p_bus->p_timer; + + FSP_ERROR_RETURN(ELC_OPEN_FLAG == ((elc_instance_ctrl_t *) p_elc_instance->p_ctrl)->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(GPT_OPEN_FLAG == ((gpt_instance_ctrl_t *) p_timer_instance->p_ctrl)->open, FSP_ERR_NOT_OPEN); +#endif + + err = + ((elc_instance_t *) p_comms_i2c_ctrl->p_bus->p_elc)->p_api->enable(((elc_instance_t *) p_comms_i2c_ctrl->p_bus-> + p_elc)->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Set open flag */ + p_ctrl->open = RM_COMMS_SMBUS_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @brief Disables specified SMBUS Comms module. Implements @ref rm_comms_api_t::close. + * + * @retval FSP_SUCCESS Successfully closed. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * + **********************************************************************************************************************/ +fsp_err_t RM_COMMS_SMBUS_Close (rm_comms_ctrl_t * const p_api_ctrl) +{ + rm_comms_smbus_instance_ctrl_t * p_ctrl = (rm_comms_smbus_instance_ctrl_t *) p_api_ctrl; + +#if RM_COMMS_SMBUS_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(RM_COMMS_SMBUS_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Clear open flag */ + p_ctrl->open = 0; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @brief Updates the SMBUS Comms callback. Implements @ref rm_comms_api_t::callbackSet. + * + * @retval FSP_SUCCESS Successfully set. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * + **********************************************************************************************************************/ +fsp_err_t RM_COMMS_SMBUS_CallbackSet (rm_comms_ctrl_t * const p_api_ctrl, + void ( * p_callback)(rm_comms_callback_args_t *), + void const * const p_context) +{ + rm_comms_smbus_instance_ctrl_t * p_ctrl = (rm_comms_smbus_instance_ctrl_t *) p_api_ctrl; + +#if RM_COMMS_SMBUS_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_callback); + FSP_ERROR_RETURN(RM_COMMS_SMBUS_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + p_ctrl->p_comms_i2c_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @brief Performs a read from the SMBUS device. Implements @ref rm_comms_api_t::read. + * + * @note When Packet Error Check (PEC) is used, size of destination buffer and the number of reading bytes must have + * 1-byte in addition for PEC byte. + * + * @retval FSP_SUCCESS Successfully data decoded. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_SIZE Read data size is invalid. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + **********************************************************************************************************************/ +fsp_err_t RM_COMMS_SMBUS_Read (rm_comms_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ + /* This API only handle for Receive byte command of SMBus. As the result, bytes will be 1 or 2 (1 data byte and + * 1 optional PEC byte) for following the SMBus protocol standard. Ignore the param to eliminate compile warning. + */ + FSP_PARAMETER_NOT_USED(bytes); + + fsp_err_t err = FSP_SUCCESS; + + rm_comms_smbus_instance_ctrl_t * p_ctrl = (rm_comms_smbus_instance_ctrl_t *) p_api_ctrl; + +#if RM_COMMS_SMBUS_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_dest); + FSP_ERROR_RETURN(1 == bytes, FSP_ERR_INVALID_SIZE); + FSP_ERROR_RETURN(RM_COMMS_SMBUS_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + uint8_t read_size = 1U; + + rm_comms_i2c_instance_ctrl_t * p_comms_i2c_ctrl = p_ctrl->p_comms_i2c_ctrl; + + if (((rm_comms_smbus_extended_cfg_t *) (p_comms_i2c_ctrl->p_cfg->p_extend))->pec_enable) + { + read_size = 2U; // 1 data byte + PEC byte + } + + /* Assign read buffer, size and crc_seed value for processing in callback function */ + p_ctrl->receive_crc_seed = RM_COMMS_SMBUS_CRC_SEED_VAL_0; + + err = rm_comms_smbus_setup_timer(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + p_ctrl->timer_is_enabled = false; + + err = rm_comms_i2c_bus_read(p_comms_i2c_ctrl, p_dest, read_size); + +#if BSP_CFG_RTOS + + /* Check the error returned from lower layer */ + err = rm_comms_smbus_semaphore_err_handler(p_comms_i2c_ctrl, err); +#endif + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @brief Performs a write from the SMBUS device. Implements @ref rm_comms_api_t::write. + * + * @retval FSP_SUCCESS Successfully writing data . + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_SIZE Transfer data size is invalid. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + **********************************************************************************************************************/ +fsp_err_t RM_COMMS_SMBUS_Write (rm_comms_ctrl_t * const p_api_ctrl, uint8_t * const p_src, uint32_t const bytes) +{ + fsp_err_t err = FSP_SUCCESS; + + rm_comms_smbus_instance_ctrl_t * p_ctrl = (rm_comms_smbus_instance_ctrl_t *) p_api_ctrl; + +#if RM_COMMS_SMBUS_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_src); + FSP_ERROR_RETURN(RM_COMMS_SMBUS_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rm_comms_i2c_instance_ctrl_t * p_comms_i2c_ctrl = p_ctrl->p_comms_i2c_ctrl; + +#if RM_COMMS_SMBUS_CFG_PARAM_CHECKING_ENABLE + if (((rm_comms_smbus_extended_cfg_t *) (p_comms_i2c_ctrl->p_cfg->p_extend))->pec_enable) + { + FSP_ERROR_RETURN(RM_COMMS_SMBUS_WRITE_MAX_BYTE >= bytes, FSP_ERR_INVALID_SIZE); + } + else + { + FSP_ERROR_RETURN(RM_COMMS_SMBUS_WRITE_MAX_BYTE > bytes, FSP_ERR_INVALID_SIZE); + } +#endif + + uint8_t * p_write; + uint32_t write_byte; + + if (!(((rm_comms_smbus_extended_cfg_t *) (p_comms_i2c_ctrl->p_cfg->p_extend))->pec_enable) || (0 == bytes)) + { + /* Handle for SMBus command Write API without PEC and Quick command */ + write_byte = bytes; + p_write = p_src; + } + else + { + /* Handle for SMBus command Write API with PEC byte */ + uint8_t slave_addr; + uint8_t pec_byte = RM_COMMS_SMBUS_CRC_SEED_VAL_0; + + i2c_master_cfg_t * p_lower_level_cfg = (i2c_master_cfg_t *) p_comms_i2c_ctrl->p_lower_level_cfg; + + slave_addr = (uint8_t) ((p_lower_level_cfg->slave << 1) | (uint8_t) RM_COMMS_SMBUS_WRITE_OPERATION); + + /* Prepare data for PEC byte calculation */ + p_ctrl->write_buff[0] = slave_addr; + memcpy(&p_ctrl->write_buff[1], p_src, bytes); + + write_byte = bytes + 1U; // numbers of byte of p_src + 1 PEC byte + + /* Calculate PEC byte for transmit data with seed value of 0 */ + rm_comms_smbus_pec_byte_calculate(p_ctrl->write_buff, write_byte, &pec_byte); + + p_ctrl->write_buff[write_byte] = pec_byte; // Assign PEC byte to last byte of data stream + + p_write = &p_ctrl->write_buff[1]; + } + + err = rm_comms_smbus_setup_timer(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + p_ctrl->timer_is_enabled = false; + + err = rm_comms_i2c_bus_write(p_comms_i2c_ctrl, p_write, write_byte); + +#if BSP_CFG_RTOS + + /* Check the error returned from lower layer */ + err = rm_comms_smbus_semaphore_err_handler(p_comms_i2c_ctrl, err); +#endif + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @brief Performs a write to, then a read from the SMBUS device. Implements @ref rm_comms_api_t::writeRead. + * + * @note When Packet Error Check (PEC) is used, size of destination buffer and the number of reading bytes must have + * 1-byte in addition for PEC byte. + * + * @retval FSP_SUCCESS Successfully data decoded. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_SIZE Transfer data size is invalid. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + **********************************************************************************************************************/ +fsp_err_t RM_COMMS_SMBUS_WriteRead (rm_comms_ctrl_t * const p_api_ctrl, + rm_comms_write_read_params_t const write_read_params) +{ + fsp_err_t err = FSP_SUCCESS; + + rm_comms_smbus_instance_ctrl_t * p_ctrl = (rm_comms_smbus_instance_ctrl_t *) p_api_ctrl; + +#if RM_COMMS_SMBUS_CFG_PARAM_CHECKING_ENABLE + uint8_t total_bytes = write_read_params.src_bytes + write_read_params.dest_bytes; + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != write_read_params.p_src); + FSP_ASSERT(NULL != write_read_params.p_dest); + FSP_ASSERT(0 < write_read_params.src_bytes); + FSP_ASSERT(1 < write_read_params.dest_bytes); + + FSP_ERROR_RETURN(RM_COMMS_SMBUS_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rm_comms_i2c_instance_ctrl_t * p_comms_i2c_ctrl = p_ctrl->p_comms_i2c_ctrl; + +#if RM_COMMS_SMBUS_CFG_PARAM_CHECKING_ENABLE + if (((rm_comms_smbus_extended_cfg_t *) (p_comms_i2c_ctrl->p_cfg->p_extend))->pec_enable) + { + FSP_ERROR_RETURN(RM_COMMS_SMBUS_PROCESS_CALL_MAX_BYTE >= total_bytes, FSP_ERR_INVALID_SIZE); + } + else + { + FSP_ERROR_RETURN(RM_COMMS_SMBUS_PROCESS_CALL_MAX_BYTE > total_bytes, FSP_ERR_INVALID_SIZE); + } +#endif + + if (((rm_comms_smbus_extended_cfg_t *) (p_comms_i2c_ctrl->p_cfg->p_extend))->pec_enable) + { + uint8_t slave_addr; + uint32_t crc_calculate_num_byte; + + i2c_master_cfg_t * p_lower_level_cfg = (i2c_master_cfg_t *) p_comms_i2c_ctrl->p_lower_level_cfg; + + crc_calculate_num_byte = write_read_params.src_bytes + 1U; // 1 slave addr byte + n-bytes data of p_src + slave_addr = (uint8_t) ((p_lower_level_cfg->slave << 1) | (uint8_t) RM_COMMS_SMBUS_WRITE_OPERATION); + + /* Prepare data for PEC byte calculation */ + p_ctrl->write_buff[0] = slave_addr; + memcpy(&p_ctrl->write_buff[1], write_read_params.p_src, write_read_params.src_bytes); + + /* Calculate PEC byte */ + p_ctrl->receive_crc_seed = RM_COMMS_SMBUS_CRC_SEED_VAL_0; + rm_comms_smbus_pec_byte_calculate(p_ctrl->write_buff, crc_calculate_num_byte, &(p_ctrl->receive_crc_seed)); + } + + err = rm_comms_smbus_setup_timer(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + p_ctrl->timer_is_enabled = false; + + err = rm_comms_i2c_bus_write_read(p_comms_i2c_ctrl, write_read_params); + +#if BSP_CFG_RTOS + + /* Check the error returned from lower layer */ + err = rm_comms_smbus_semaphore_err_handler(p_comms_i2c_ctrl, err); +#endif + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup RM_COMM_SMBUS) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Calculate PEC byte with CRC-8 (x^8 + x^2 + x + 1) format by using lookup table. + * + * @retval PEC byte. + **********************************************************************************************************************/ +__STATIC_INLINE void rm_comms_smbus_pec_byte_calculate (uint8_t const * p_data, uint32_t num_bytes, uint8_t * p_crc_val) +{ + uint8_t cur_data; + uint8_t prv_data; + + /* Init the first value */ + prv_data = *p_crc_val; + + /* The CRC 8 has 255 possible result which stored at g_crc_lookup_table. For each input byte (except the seed value) + * we will perform the XOR operation between current and previous data byte. + * + * The result of XOR operation above is the location of the CRC result in lookup table. After got the CRC value from + * the table, assign back to prv_data for next calculation. When all bytes of data calculated, prv_data is returned + * as PEC byte of entire data stream. + */ + for (uint16_t i = 0; i < num_bytes; i++) + { + cur_data = prv_data ^ p_data[i]; + prv_data = g_crc_lookup_table[cur_data]; + } + + *p_crc_val = prv_data; +} + +/*******************************************************************************************************************//** + * @brief Update MEXT count value. + * + * @retval FSP_SUCCESS Update value for MEXT succesfully. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + **********************************************************************************************************************/ +__STATIC_INLINE fsp_err_t rm_comms_smbus_update_mext_val (rm_comms_smbus_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + + rm_comms_i2c_instance_ctrl_t * p_comms_i2c_ctrl = p_ctrl->p_comms_i2c_ctrl; + + timer_instance_t * p_timer_instance = (timer_instance_t *) p_comms_i2c_ctrl->p_bus->p_timer; + + timer_api_t * p_gpt_api = (timer_api_t *) p_timer_instance->p_api; + gpt_instance_ctrl_t * p_gpt_ctrl = (gpt_instance_ctrl_t *) p_timer_instance->p_ctrl; + gpt_extended_cfg_t * p_gpt_extend_cfg = (gpt_extended_cfg_t *) p_timer_instance->p_cfg->p_extend; + + if (!p_ctrl->timer_is_enabled) + { + err = p_gpt_api->stop(p_gpt_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + err = p_gpt_api->enable(p_gpt_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + p_ctrl->timer_is_enabled = true; + } + + /* Get current count and set new value for compare match, this operation help to ensure transmission time between + * ACK events will not exceed 10 (ms). */ + timer_status_t cur_status; + + err = p_gpt_api->statusGet(p_gpt_ctrl, &cur_status); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + uint32_t next_val = cur_status.counter + p_gpt_extend_cfg->compare_match_value[0]; + + err = p_gpt_api->compareMatchSet(p_gpt_ctrl, next_val, TIMER_COMPARE_MATCH_A); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Start the GPT again */ + err = p_gpt_api->start(p_gpt_ctrl); + + return err; +} + +/*******************************************************************************************************************//** + * @brief Setup timer for SMBus before starting the transmission when using I2C Shared Bus. + * + * @retval FSP_SUCCESS Successfully configured. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + **********************************************************************************************************************/ +static fsp_err_t rm_comms_smbus_setup_timer (rm_comms_smbus_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + + rm_comms_i2c_instance_ctrl_t * p_iic_ctrl = p_ctrl->p_comms_i2c_ctrl; + + timer_instance_t * p_timer_instance = (timer_instance_t *) p_iic_ctrl->p_bus->p_timer; + + timer_api_t * p_timer_api = (timer_api_t *) p_timer_instance->p_api; + timer_ctrl_t * p_timer_ctrl = p_timer_instance->p_ctrl; + gpt_extended_cfg_t * p_gpt_extend_cfg = (gpt_extended_cfg_t *) p_timer_instance->p_cfg->p_extend; + +#if BSP_CFG_RTOS + err = rm_comms_i2c_os_recursive_mutex_acquire(p_iic_ctrl->p_bus->p_bus_recursive_mutex, + p_iic_ctrl->p_bus->bus_timeout); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Disable a linkage between elc and timers before starting off a new operation */ + err = p_timer_api->disable(p_timer_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Reset timer counter before starting off a new operation */ + err = p_timer_api->reset(p_timer_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Set callback function and current control block */ + err = p_timer_api->callbackSet(p_timer_ctrl, rm_comms_smbus_timeout_callback, p_ctrl, NULL); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Set 10 (ms) as compare match value */ + err = p_timer_api->compareMatchSet(p_timer_ctrl, p_gpt_extend_cfg->compare_match_value[0], TIMER_COMPARE_MATCH_A); + + return err; +} + +#if BSP_CFG_RTOS + +/*******************************************************************************************************************//** + * @brief Handling error when failed to acquire semaphore. + * + * @retval FSP_SUCCESS Handling error successfully. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + **********************************************************************************************************************/ +__STATIC_INLINE fsp_err_t rm_comms_smbus_semaphore_err_handler (rm_comms_i2c_instance_ctrl_t * const p_api_ctrl, + fsp_err_t semphr_err) +{ + fsp_err_t timer_err = FSP_SUCCESS; + fsp_err_t i2c_err = FSP_SUCCESS; + fsp_err_t mutex_err = FSP_SUCCESS; + + if (FSP_SUCCESS != semphr_err) + { + i2c_master_instance_t * p_driver_instance = (i2c_master_instance_t *) p_api_ctrl->p_bus->p_driver_instance; + i2c_err = p_driver_instance->p_api->abort(p_driver_instance->p_ctrl); + + timer_instance_t * p_timer_instance = (timer_instance_t *) p_api_ctrl->p_bus->p_timer; + timer_err = p_timer_instance->p_api->stop(p_timer_instance->p_ctrl); + } + + /* Because mutex was locked 2 times, at rm_comms_smbus_setup_timer() and rm_comms_i2c_bus_reconfigure(), it's + * necessary to release mutex 1 more time here, the other was released at lower layer. */ + if (NULL != p_api_ctrl->p_bus->p_bus_recursive_mutex) + { + mutex_err = rm_comms_i2c_os_recursive_mutex_release(p_api_ctrl->p_bus->p_bus_recursive_mutex); + } + + FSP_ERROR_RETURN(FSP_SUCCESS == i2c_err, i2c_err); + FSP_ERROR_RETURN(FSP_SUCCESS == timer_err, timer_err); + FSP_ERROR_RETURN(FSP_SUCCESS == mutex_err, mutex_err); + + return semphr_err; +} + +#endif + +/*******************************************************************************************************************//** + * @brief Common callback function called in the I2C driver callback function when SMBus is used. + **********************************************************************************************************************/ +void rm_comms_smbus_transmission_callback (i2c_master_callback_args_t * p_args) +{ + fsp_err_t err = FSP_SUCCESS; + + rm_comms_i2c_instance_ctrl_t * p_comms_i2c_ctrl = (rm_comms_i2c_instance_ctrl_t *) (p_args->p_context); + rm_comms_smbus_instance_ctrl_t * p_ctrl = + (rm_comms_smbus_instance_ctrl_t *) (p_comms_i2c_ctrl->p_context); + + rm_comms_callback_args_t comms_smbus_args; + bool transition_complete_flag = false; + + /* Initialize the event */ + comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + + /* Set context */ + comms_smbus_args.p_context = p_ctrl->p_context; + + /* Set event */ + switch (p_args->event) + { + case I2C_MASTER_EVENT_RX_COMPLETE: + { + /* Update the transition complete flag to call user callback */ + transition_complete_flag = true; + + comms_smbus_args.event = RM_COMMS_EVENT_OPERATION_COMPLETE; + + /* If PEC is used, calculate PEC byte from received data and compare with PEC byte with PEC byte from + * received data. + */ + if (((rm_comms_smbus_extended_cfg_t *) (p_comms_i2c_ctrl->p_cfg->p_extend))->pec_enable) + { + /* If PEC is used, start checking the PEC byte */ + uint8_t slave_addr; + uint8_t ref_pec; + uint8_t * p_read_buff; + uint8_t data_pec; + + i2c_master_cfg_t * p_lower_level_cfg = (i2c_master_cfg_t *) p_comms_i2c_ctrl->p_lower_level_cfg; + + p_read_buff = p_comms_i2c_ctrl->p_transfer_data; + + slave_addr = + (uint8_t) ((p_lower_level_cfg->slave << 1) | (uint8_t) RM_COMMS_SMBUS_READ_OPERATION); + + /* Calculate CRC value of slave address */ + data_pec = p_ctrl->receive_crc_seed; + rm_comms_smbus_pec_byte_calculate(&slave_addr, 1U, &data_pec); + + /* After acquired CRC value of slave addr, this value will play as seed to generate the CRC value of + * read data. + * + * PEC byte in destination buffer will be excluded when calculate CRC value of read data. + */ + rm_comms_smbus_pec_byte_calculate(p_read_buff, (p_comms_i2c_ctrl->transfer_data_bytes - 1U), &data_pec); + + /* Get PEC byte from dest buffer */ + ref_pec = p_read_buff[p_comms_i2c_ctrl->transfer_data_bytes - 1U]; // PEC byte place at last byte of data stream + + /* Compare PEC byte and return event */ + if (ref_pec != data_pec) + { + comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + } + } + + break; + } + + case I2C_MASTER_EVENT_TX_COMPLETE: + { + /* If p_read_buff is NULL which mean middleware is implementing SMBus Write command, I2C raise TX complete + * mean all data was written, middleware update event and invoke user's callback. + */ + if (NULL == p_comms_i2c_ctrl->p_transfer_data) + { + comms_smbus_args.event = RM_COMMS_EVENT_OPERATION_COMPLETE; + + /* Set the transition flag as true to call user callback function */ + transition_complete_flag = true; + } + else + { + i2c_master_instance_t * p_iic_instance = + (i2c_master_instance_t *) p_comms_i2c_ctrl->p_bus->p_driver_instance; + + /* Update the compare match value and start the timer again, we do not need to stop the timer here + * because when IIC completed the transmission, interrupt raises and GPT was stopped by ELC. */ + err = rm_comms_smbus_update_mext_val(p_ctrl); + + if (FSP_SUCCESS != err) + { + transition_complete_flag = true; + comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + } + else + { + /* When NULL != p_comms_i2c_ctrl->p_transfer_data, SMBus middleware is implementing WriteRead API. After receive I2C + * TX complete, invoke I2C Read API for start reading with restart. + */ + err = + p_iic_instance->p_api->read(p_iic_instance->p_ctrl, + p_comms_i2c_ctrl->p_transfer_data, + p_comms_i2c_ctrl->transfer_data_bytes, + false); + + if (FSP_SUCCESS != err) + { + transition_complete_flag = true; + comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + } + else + { + /* Update the flag to avoid calling user callback since the transition has not complete */ + transition_complete_flag = false; + } + } + } + + break; + } + + case I2C_MASTER_EVENT_START: + { + timer_instance_t * p_timer_instance = (timer_instance_t *) p_comms_i2c_ctrl->p_bus->p_timer; + + err = p_timer_instance->p_api->start(p_timer_instance->p_ctrl); + + if (FSP_SUCCESS != err) + { + transition_complete_flag = true; + comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + } + + break; + } + + case I2C_MASTER_EVENT_BYTE_ACK: + { + err = rm_comms_smbus_update_mext_val(p_ctrl); + + if (FSP_SUCCESS != err) + { + transition_complete_flag = true; + comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + } + + break; + } + + case I2C_MASTER_EVENT_ABORTED: + { + i2c_master_instance_t * p_iic_instance = + (i2c_master_instance_t *) p_comms_i2c_ctrl->p_bus->p_driver_instance; + + /* If IIC returned error before timer is enabled, which mean ELC cannot stop the timer via IIC event , + * stopping timer by software is needed. */ + if (!p_ctrl->timer_is_enabled) + { + timer_instance_t * p_timer_instance = (timer_instance_t *) p_comms_i2c_ctrl->p_bus->p_timer; + + p_timer_instance->p_api->stop(p_timer_instance->p_ctrl); + } + + /* Safely abort RA I2C driver */ + p_iic_instance->p_api->abort(p_iic_instance->p_ctrl); + + /* Update the transition complete flag to call user callback*/ + transition_complete_flag = true; + + /* Update the event which returned to user's callback */ + comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + + break; + } + + default: + { + /* All possible events are handled by above case. Nothing to do here. */ + } + } + + if (transition_complete_flag) + { + rm_comms_i2c_process_in_callback(p_comms_i2c_ctrl, &comms_smbus_args); + } +} + +/*******************************************************************************************************************//** + * @brief Callback function called in the GPT driver callback function when SMBus is used. + **********************************************************************************************************************/ +void rm_comms_smbus_timeout_callback (timer_callback_args_t * p_args) +{ + rm_comms_smbus_instance_ctrl_t * p_ctrl = (rm_comms_smbus_instance_ctrl_t *) (p_args->p_context); + + rm_comms_i2c_instance_ctrl_t * p_comms_i2c = p_ctrl->p_comms_i2c_ctrl; + + rm_comms_callback_args_t comms_smbus_args; + + /* Set context and return event */ + comms_smbus_args.p_context = p_comms_i2c->p_context; + comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + + i2c_master_instance_t const * p_iic_instance = p_comms_i2c->p_bus->p_driver_instance; + + /* Abort the current transmission */ + p_iic_instance->p_api->abort(p_iic_instance->p_ctrl); + + /* Because HW will not stop timer when compare match event hits, it's necessary to be stopped by software */ + if (TIMER_EVENT_COMPARE_A == p_args->event) + { + timer_instance_t * p_timer_instance = (timer_instance_t *) p_comms_i2c->p_bus->p_timer; + + p_timer_instance->p_api->stop(p_timer_instance->p_ctrl); + } + + rm_comms_i2c_process_in_callback(p_comms_i2c, &comms_smbus_args); +} diff --git a/ra/fsp/src/rm_comms_usb_pcdc/rm_comms_usb_pcdc.c b/ra/fsp/src/rm_comms_usb_pcdc/rm_comms_usb_pcdc.c index 1ccc26834..6cfeb5e06 100644 --- a/ra/fsp/src/rm_comms_usb_pcdc/rm_comms_usb_pcdc.c +++ b/ra/fsp/src/rm_comms_usb_pcdc/rm_comms_usb_pcdc.c @@ -141,10 +141,8 @@ fsp_err_t RM_COMMS_USB_PCDC_Open (rm_comms_ctrl_t * const p_api_ctrl, rm_comms_c FSP_ERROR_RETURN(FSP_SUCCESS == err || FSP_ERR_ALREADY_OPEN == err, err); /* Set callback function for Timer driver */ - err = p_timer_api->callbackSet(p_extend->p_gpt->p_ctrl, - rm_comms_usb_pcdc_timer_handler, - p_usb_instance->p_api, - NULL); + err = + p_timer_api->callbackSet(p_extend->p_gpt->p_ctrl, rm_comms_usb_pcdc_timer_handler, p_usb_instance->p_api, NULL); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); #endif @@ -155,6 +153,7 @@ fsp_err_t RM_COMMS_USB_PCDC_Open (rm_comms_ctrl_t * const p_api_ctrl, rm_comms_c FSP_ERROR_RETURN(FSP_SUCCESS == err, err); #if BSP_CFG_RTOS == 2 + /* Set callback function for USB driver */ err = p_usb_api->callback(rm_comms_usb_pcdc_callback_handler); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); @@ -552,7 +551,7 @@ void rm_comms_usb_pcdc_callback_handler (usb_callback_args_t * p_args) **********************************************************************************************************************/ void rm_comms_usb_pcdc_timer_handler (timer_callback_args_t * p_args) { - usb_api_t const * p_usb_api = (usb_api_t const *) (p_args->p_context); + usb_api_t const * p_usb_api = (usb_api_t const *) (p_args->p_context); usb_instance_ctrl_t ctrl; p_usb_api->eventGet(&ctrl, &ctrl.event); @@ -561,4 +560,5 @@ void rm_comms_usb_pcdc_timer_handler (timer_callback_args_t * p_args) rm_comms_usb_pcdc_callback_handler(&ctrl); } } + #endif diff --git a/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c b/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c index ad351123d..2212be9e9 100644 --- a/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c +++ b/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c @@ -235,7 +235,7 @@ void vEtherISRCallback (ether_callback_args_t * p_args) { /* If EDMAC FR (Frame Receive Event) or FDE (Receive Descriptor Empty Event) * interrupt occurs, wake up xRxHanderTask. */ - if (p_args->status_eesr & ETHER_EDMAC_INTERRUPT_FACTOR_RECEPTION) + if (p_args->event & ETHER_EVENT_RX_COMPLETE || p_args->event & ETHER_EVENT_RX_MESSAGE_LOST) { if (xRxHanderTaskHandle != NULL) { diff --git a/ra/fsp/src/rm_freertos_port/port.c b/ra/fsp/src/rm_freertos_port/port.c index 8ea752651..6ea2ff67b 100644 --- a/ra/fsp/src/rm_freertos_port/port.c +++ b/ra/fsp/src/rm_freertos_port/port.c @@ -126,7 +126,7 @@ #define RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS (0xA500U) /* Determine which stack monitor to use. */ -#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) // CM33, CM85 +#if defined(RENESAS_CORTEX_M33) || defined(RENESAS_CORTEX_M85) #define RM_FREERTOS_PORT_PSPLIM_PRESENT (1) #define RM_FREERTOS_PORT_SPMON_PRESENT (0) #else @@ -171,7 +171,7 @@ #endif /* CM23 does not support the IT instruction. */ -#if defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) // CM4, CM33, or CM85 +#if defined(RENESAS_CORTEX_M4) || defined(RENESAS_CORTEX_M33) || defined(RENESAS_CORTEX_M85) #define RM_FREERTOS_PORT_ISA_IT_SUPPORTED (1) #else #define RM_FREERTOS_PORT_ISA_IT_SUPPORTED (0) @@ -1551,7 +1551,7 @@ void vPortValidateInterruptPriority (void) configASSERT(ulCurrentPriority >= (configMAX_SYSCALL_INTERRUPT_PRIORITY) >> (8 - __NVIC_PRIO_BITS)); } - #ifndef __ARM_ARCH_8M_BASE__ + #ifndef RENESAS_CORTEX_M23 /* Priority grouping: The interrupt controller (NVIC) allows the bits * that define each interrupt's priority to be split between bits that diff --git a/ra/fsp/src/rm_freertos_port/portmacro.h b/ra/fsp/src/rm_freertos_port/portmacro.h index a8a9924e7..0f6347d27 100644 --- a/ra/fsp/src/rm_freertos_port/portmacro.h +++ b/ra/fsp/src/rm_freertos_port/portmacro.h @@ -93,7 +93,7 @@ typedef uint32_t TickType_t; #define portTICK_PERIOD_MS ((TickType_t) 1000 / configTICK_RATE_HZ) #define portBYTE_ALIGNMENT 8 - #if BSP_FEATURE_BSP_HAS_SP_MON || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) + #if BSP_FEATURE_BSP_HAS_SP_MON || defined(RENESAS_CORTEX_M33) || defined(RENESAS_CORTEX_M85) #define portHAS_STACK_OVERFLOW_CHECKING (1) #endif @@ -151,7 +151,7 @@ void vResetPrivilege(void) RM_FREERTOS_PORT_NAKED_FUNCTION; #endif - #if defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) // CM4, CM33, or CM85 + #if defined(RENESAS_CORTEX_M4) || defined(RENESAS_CORTEX_M33) || defined(RENESAS_CORTEX_M85) #define RM_FREERTOS_PORT_HAS_BASEPRI (1) #else #define RM_FREERTOS_PORT_HAS_BASEPRI (0) @@ -217,7 +217,7 @@ void vApplicationIdleHook(void); /* Generic helper function. */ __attribute__((always_inline)) static inline uint8_t ucPortCountLeadingZeros (uint32_t ulBitmap) { - return __CLZ(ulBitmap); + return (uint8_t) __CLZ(ulBitmap); } /* Check the configuration. */ diff --git a/ra/fsp/src/rm_http_onchip_da16xxx/rm_http_onchip_da16xxx.c b/ra/fsp/src/rm_http_onchip_da16xxx/rm_http_onchip_da16xxx.c index becdd063e..9c1584911 100644 --- a/ra/fsp/src/rm_http_onchip_da16xxx/rm_http_onchip_da16xxx.c +++ b/ra/fsp/src/rm_http_onchip_da16xxx/rm_http_onchip_da16xxx.c @@ -477,7 +477,6 @@ static fsp_err_t rm_http_da16xxx_read_header (http_onchip_da16xxx_instance_ctrl_ /* Advance pointer and track start of header data length */ ptr = ptr + strlen("+NWHTCDATA:"); - char * start_ptr = ptr; /* Parse data length for response header */ header_size = strtol(ptr, NULL, 10); @@ -492,7 +491,7 @@ static fsp_err_t rm_http_da16xxx_read_header (http_onchip_da16xxx_instance_ctrl_ FSP_ERROR_RETURN(NULL != ptr, FSP_ERR_INVALID_DATA); - /* Check for length of data (especially if 1460 bytes exactly) */ + /* Check for length of data */ ptr = strstr(ptr, "Content-Length: "); FSP_ERROR_RETURN(NULL != ptr, FSP_ERR_INVALID_DATA); @@ -500,7 +499,7 @@ static fsp_err_t rm_http_da16xxx_read_header (http_onchip_da16xxx_instance_ctrl_ /* Advance pointer and track start of header data length */ ptr = ptr + strlen("Content-Length: "); - /* Parse data length for payload */ + /* Parse data length for payload size (expected length) */ content_length = strtol(ptr, NULL, 10); FSP_ERROR_RETURN(0 != content_length, FSP_ERR_INVALID_DATA); @@ -510,11 +509,6 @@ static fsp_err_t rm_http_da16xxx_read_header (http_onchip_da16xxx_instance_ctrl_ FSP_ERROR_RETURN(NULL != ptr, FSP_ERR_INVALID_DATA); - char * check_ptr = (char *) (ptr - start_ptr); - - /* Compare expected length with current length */ - FSP_ERROR_RETURN(0 == *check_ptr, FSP_ERR_INVALID_DATA); - /* Loop around to check the data size matches the expected content length */ do { diff --git a/ra/fsp/src/rm_mbedtls/x509_crt.c b/ra/fsp/src/rm_mbedtls/x509_crt.c index 65a994743..5b53a7c47 100644 --- a/ra/fsp/src/rm_mbedtls/x509_crt.c +++ b/ra/fsp/src/rm_mbedtls/x509_crt.c @@ -48,9 +48,10 @@ #if defined(MBEDTLS_USE_PSA_CRYPTO) #include "psa/crypto.h" -#include "mbedtls/psa_util.h" +#include "psa_util_internal.h" +#include "md_psa.h" #endif /* MBEDTLS_USE_PSA_CRYPTO */ -#include "hash_info.h" +#include "pk_internal.h" #include "mbedtls/platform.h" @@ -60,6 +61,7 @@ #if defined(MBEDTLS_HAVE_TIME) #if defined(_WIN32) && !defined(EFIX64) && !defined(EFI32) +#define WIN32_LEAN_AND_MEAN #include #else #include @@ -105,7 +107,7 @@ const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_default = MBEDTLS_X509_ID_FLAG(MBEDTLS_MD_SHA384) | MBEDTLS_X509_ID_FLAG(MBEDTLS_MD_SHA512), 0xFFFFFFF, /* Any PK alg */ -#if defined(MBEDTLS_ECP_C) +#if defined(MBEDTLS_PK_HAVE_ECC_KEYS) /* Curves at or above 128-bit security level. Note that this selection * should be aligned with ssl_preset_default_curves in ssl_tls.c. */ MBEDTLS_X509_ID_FLAG(MBEDTLS_ECP_DP_SECP256R1) | @@ -115,9 +117,9 @@ const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_default = MBEDTLS_X509_ID_FLAG(MBEDTLS_ECP_DP_BP384R1) | MBEDTLS_X509_ID_FLAG(MBEDTLS_ECP_DP_BP512R1) | 0, -#else +#else /* MBEDTLS_PK_HAVE_ECC_KEYS */ 0, -#endif +#endif /* MBEDTLS_PK_HAVE_ECC_KEYS */ 2048, }; @@ -156,13 +158,13 @@ const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_suiteb = /* Only ECDSA */ MBEDTLS_X509_ID_FLAG(MBEDTLS_PK_ECDSA) | MBEDTLS_X509_ID_FLAG(MBEDTLS_PK_ECKEY), -#if defined(MBEDTLS_ECP_C) +#if defined(MBEDTLS_PK_HAVE_ECC_KEYS) /* Only NIST P-256 and P-384 */ MBEDTLS_X509_ID_FLAG(MBEDTLS_ECP_DP_SECP256R1) | MBEDTLS_X509_ID_FLAG(MBEDTLS_ECP_DP_SECP384R1), -#else +#else /* MBEDTLS_PK_HAVE_ECC_KEYS */ 0, -#endif +#endif /* MBEDTLS_PK_HAVE_ECC_KEYS */ 0, }; @@ -230,13 +232,13 @@ static int x509_profile_check_key(const mbedtls_x509_crt_profile *profile, return -1; } -#endif +#endif /* MBEDTLS_RSA_C */ -#if defined(MBEDTLS_ECP_C) +#if defined(MBEDTLS_PK_HAVE_ECC_KEYS) if (pk_alg == MBEDTLS_PK_ECDSA || pk_alg == MBEDTLS_PK_ECKEY || pk_alg == MBEDTLS_PK_ECKEY_DH) { - const mbedtls_ecp_group_id gid = mbedtls_pk_ec(*pk)->grp.id; + const mbedtls_ecp_group_id gid = mbedtls_pk_get_group_id(pk); if (gid == MBEDTLS_ECP_DP_NONE) { return -1; @@ -248,7 +250,7 @@ static int x509_profile_check_key(const mbedtls_x509_crt_profile *profile, return -1; } -#endif +#endif /* MBEDTLS_PK_HAVE_ECC_KEYS */ return -1; } @@ -590,6 +592,114 @@ static int x509_get_ext_key_usage(unsigned char **p, return 0; } +/* + * SubjectKeyIdentifier ::= KeyIdentifier + * + * KeyIdentifier ::= OCTET STRING + */ +static int x509_get_subject_key_id(unsigned char **p, + const unsigned char *end, + mbedtls_x509_buf *subject_key_id) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t len = 0u; + + if ((ret = mbedtls_asn1_get_tag(p, end, &len, + MBEDTLS_ASN1_OCTET_STRING)) != 0) { + return MBEDTLS_ERROR_ADD(MBEDTLS_ERR_X509_INVALID_EXTENSIONS, ret); + } + + subject_key_id->len = len; + subject_key_id->tag = MBEDTLS_ASN1_OCTET_STRING; + subject_key_id->p = *p; + *p += len; + + if (*p != end) { + return MBEDTLS_ERROR_ADD(MBEDTLS_ERR_X509_INVALID_EXTENSIONS, + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH); + } + + return 0; +} + +/* + * AuthorityKeyIdentifier ::= SEQUENCE { + * keyIdentifier [0] KeyIdentifier OPTIONAL, + * authorityCertIssuer [1] GeneralNames OPTIONAL, + * authorityCertSerialNumber [2] CertificateSerialNumber OPTIONAL } + * + * KeyIdentifier ::= OCTET STRING + */ +static int x509_get_authority_key_id(unsigned char **p, + unsigned char *end, + mbedtls_x509_authority *authority_key_id) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t len = 0u; + + if ((ret = mbedtls_asn1_get_tag(p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE)) != 0) { + return MBEDTLS_ERROR_ADD(MBEDTLS_ERR_X509_INVALID_EXTENSIONS, ret); + } + + if (*p + len != end) { + return MBEDTLS_ERROR_ADD(MBEDTLS_ERR_X509_INVALID_EXTENSIONS, + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH); + } + + ret = mbedtls_asn1_get_tag(p, end, &len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC); + + /* KeyIdentifier is an OPTIONAL field */ + if (ret == 0) { + authority_key_id->keyIdentifier.len = len; + authority_key_id->keyIdentifier.p = *p; + /* Setting tag of the keyIdentfier intentionally to 0x04. + * Although the .keyIdentfier field is CONTEXT_SPECIFIC ([0] OPTIONAL), + * its tag with the content is the payload of on OCTET STRING primitive */ + authority_key_id->keyIdentifier.tag = MBEDTLS_ASN1_OCTET_STRING; + + *p += len; + } else if (ret != MBEDTLS_ERR_ASN1_UNEXPECTED_TAG) { + return MBEDTLS_ERROR_ADD(MBEDTLS_ERR_X509_INVALID_EXTENSIONS, ret); + } + + if (*p < end) { + /* Getting authorityCertIssuer using the required specific class tag [1] */ + if ((ret = mbedtls_asn1_get_tag(p, end, &len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC | MBEDTLS_ASN1_CONSTRUCTED | + 1)) != 0) { + /* authorityCertIssuer and authorityCertSerialNumber MUST both + be present or both be absent. At this point we expect to have both. */ + return MBEDTLS_ERROR_ADD(MBEDTLS_ERR_X509_INVALID_EXTENSIONS, ret); + } + /* "end" also includes the CertSerialNumber field so "len" shall be used */ + ret = mbedtls_x509_get_subject_alt_name_ext(p, + (*p+len), + &authority_key_id->authorityCertIssuer); + if (ret != 0) { + return ret; + } + + /* Getting authorityCertSerialNumber using the required specific class tag [2] */ + if ((ret = mbedtls_asn1_get_tag(p, end, &len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC | 2)) != 0) { + return MBEDTLS_ERROR_ADD(MBEDTLS_ERR_X509_INVALID_EXTENSIONS, ret); + } + authority_key_id->authorityCertSerialNumber.len = len; + authority_key_id->authorityCertSerialNumber.p = *p; + authority_key_id->authorityCertSerialNumber.tag = MBEDTLS_ASN1_INTEGER; + *p += len; + } + + if (*p != end) { + return MBEDTLS_ERR_X509_INVALID_EXTENSIONS + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH; + } + + return 0; +} + /* * id-ce-certificatePolicies OBJECT IDENTIFIER ::= { id-ce 32 } * @@ -888,8 +998,25 @@ static int x509_get_crt_ext(unsigned char **p, } break; + case MBEDTLS_X509_EXT_SUBJECT_KEY_IDENTIFIER: + /* Parse subject key identifier */ + if ((ret = x509_get_subject_key_id(p, end_ext_data, + &crt->subject_key_id)) != 0) { + return ret; + } + break; + + case MBEDTLS_X509_EXT_AUTHORITY_KEY_IDENTIFIER: + /* Parse authority key identifier */ + if ((ret = x509_get_authority_key_id(p, end_ext_octet, + &crt->authority_key_id)) != 0) { + return ret; + } + break; case MBEDTLS_X509_EXT_SUBJECT_ALT_NAME: - /* Parse subject alt name */ + /* Parse subject alt name + * SubjectAltName ::= GeneralNames + */ if ((ret = mbedtls_x509_get_subject_alt_name(p, end_ext_octet, &crt->subject_alt_names)) != 0) { return ret; @@ -1404,8 +1531,7 @@ int mbedtls_x509_crt_parse_file(mbedtls_x509_crt *chain, const char *path) ret = mbedtls_x509_crt_parse(chain, buf, n); - mbedtls_platform_zeroize(buf, n); - mbedtls_free(buf); + mbedtls_zeroize_and_free(buf, n); return ret; } @@ -1434,6 +1560,11 @@ int mbedtls_x509_crt_parse_path(mbedtls_x509_crt *chain, const char *path) p = filename + len; filename[len++] = '*'; + /* + * Note this function uses the code page CP_ACP which is the system default + * ANSI codepage. The input string is always described in BYTES and the + * output length is described in WCHARs. + */ w_ret = MultiByteToWideChar(CP_ACP, 0, filename, (int) len, szDir, MAX_PATH - 3); if (w_ret == 0) { @@ -1452,11 +1583,8 @@ int mbedtls_x509_crt_parse_path(mbedtls_x509_crt *chain, const char *path) if (file_data.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) { continue; } - w_ret = WideCharToMultiByte(CP_ACP, 0, file_data.cFileName, - -1, - p, (int) len, - NULL, NULL); + -1, p, (int) len, NULL, NULL); if (w_ret == 0) { ret = MBEDTLS_ERR_X509_FILE_IO_ERROR; goto cleanup; @@ -1551,6 +1679,27 @@ int mbedtls_x509_crt_parse_path(mbedtls_x509_crt *chain, const char *path) #endif /* FSP_NOT_DEFINED */ #if !defined(MBEDTLS_X509_REMOVE_INFO) +#define PRINT_ITEM(i) \ + do { \ + ret = mbedtls_snprintf(p, n, "%s" i, sep); \ + MBEDTLS_X509_SAFE_SNPRINTF; \ + sep = ", "; \ + } while (0) + +#define CERT_TYPE(type, name) \ + do { \ + if (ns_cert_type & (type)) { \ + PRINT_ITEM(name); \ + } \ + } while (0) + +#define KEY_USAGE(code, name) \ + do { \ + if (key_usage & (code)) { \ + PRINT_ITEM(name); \ + } \ + } while (0) + static int x509_info_ext_key_usage(char **buf, size_t *size, const mbedtls_x509_sequence *extended_key_usage) { @@ -1875,10 +2024,11 @@ int mbedtls_x509_crt_is_revoked(const mbedtls_x509_crt *crt, const mbedtls_x509_ */ static int x509_crt_verifycrl(mbedtls_x509_crt *crt, mbedtls_x509_crt *ca, mbedtls_x509_crl *crl_list, - const mbedtls_x509_crt_profile *profile) + const mbedtls_x509_crt_profile *profile, + const mbedtls_x509_time *now) { int flags = 0; - unsigned char hash[MBEDTLS_HASH_MAX_SIZE]; + unsigned char hash[MBEDTLS_MD_MAX_SIZE]; #if defined(MBEDTLS_USE_PSA_CRYPTO) psa_algorithm_t psa_algorithm; #else @@ -1918,7 +2068,7 @@ static int x509_crt_verifycrl(mbedtls_x509_crt *crt, mbedtls_x509_crt *ca, } #if defined(MBEDTLS_USE_PSA_CRYPTO) - psa_algorithm = mbedtls_hash_info_psa_from_md(crl_list->sig_md); + psa_algorithm = mbedtls_md_psa_alg_from_type(crl_list->sig_md); if (psa_hash_compute(psa_algorithm, crl_list->tbs.p, crl_list->tbs.len, @@ -1953,16 +2103,20 @@ static int x509_crt_verifycrl(mbedtls_x509_crt *crt, mbedtls_x509_crt *ca, break; } +#if defined(MBEDTLS_HAVE_TIME_DATE) /* * Check for validity of CRL (Do not drop out) */ - if (mbedtls_x509_time_is_past(&crl_list->next_update)) { + if (mbedtls_x509_time_cmp(&crl_list->next_update, now) < 0) { flags |= MBEDTLS_X509_BADCRL_EXPIRED; } - if (mbedtls_x509_time_is_future(&crl_list->this_update)) { + if (mbedtls_x509_time_cmp(&crl_list->this_update, now) > 0) { flags |= MBEDTLS_X509_BADCRL_FUTURE; } +#else + ((void) now); +#endif /* * Check if certificate is revoked @@ -1987,7 +2141,7 @@ static int x509_crt_check_signature(const mbedtls_x509_crt *child, mbedtls_x509_crt_restart_ctx *rs_ctx) { size_t hash_len; - unsigned char hash[MBEDTLS_HASH_MAX_SIZE]; + unsigned char hash[MBEDTLS_MD_MAX_SIZE]; #if !defined(MBEDTLS_USE_PSA_CRYPTO) const mbedtls_md_info_t *md_info; md_info = mbedtls_md_info_from_type(child->sig_md); @@ -1998,7 +2152,7 @@ static int x509_crt_check_signature(const mbedtls_x509_crt *child, return -1; } #else - psa_algorithm_t hash_alg = mbedtls_hash_info_psa_from_md(child->sig_md); + psa_algorithm_t hash_alg = mbedtls_md_psa_alg_from_type(child->sig_md); psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; status = psa_hash_compute(hash_alg, @@ -2120,7 +2274,8 @@ static int x509_crt_find_parent_in( int top, unsigned path_cnt, unsigned self_cnt, - mbedtls_x509_crt_restart_ctx *rs_ctx) + mbedtls_x509_crt_restart_ctx *rs_ctx, + const mbedtls_x509_time *now) { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_x509_crt *parent, *fallback_parent; @@ -2183,9 +2338,10 @@ static int x509_crt_find_parent_in( continue; } +#if defined(MBEDTLS_HAVE_TIME_DATE) /* optional time check */ - if (mbedtls_x509_time_is_past(&parent->valid_to) || - mbedtls_x509_time_is_future(&parent->valid_from)) { + if (mbedtls_x509_time_cmp(&parent->valid_to, now) < 0 || /* past */ + mbedtls_x509_time_cmp(&parent->valid_from, now) > 0) { /* future */ if (fallback_parent == NULL) { fallback_parent = parent; fallback_signature_is_good = signature_is_good; @@ -2193,6 +2349,9 @@ static int x509_crt_find_parent_in( continue; } +#else + ((void) now); +#endif *r_parent = parent; *r_signature_is_good = signature_is_good; @@ -2238,7 +2397,8 @@ static int x509_crt_find_parent( int *signature_is_good, unsigned path_cnt, unsigned self_cnt, - mbedtls_x509_crt_restart_ctx *rs_ctx) + mbedtls_x509_crt_restart_ctx *rs_ctx, + const mbedtls_x509_time *now) { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_x509_crt *search_list; @@ -2259,7 +2419,7 @@ static int x509_crt_find_parent( ret = x509_crt_find_parent_in(child, search_list, parent, signature_is_good, *parent_is_trusted, - path_cnt, self_cnt, rs_ctx); + path_cnt, self_cnt, rs_ctx, now); #if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) if (rs_ctx != NULL && ret == MBEDTLS_ERR_ECP_IN_PROGRESS) { @@ -2380,6 +2540,13 @@ static int x509_crt_verify_chain( int signature_is_good; unsigned self_cnt; mbedtls_x509_crt *cur_trust_ca = NULL; + mbedtls_x509_time now; + +#if defined(MBEDTLS_HAVE_TIME_DATE) + if (mbedtls_x509_time_gmtime(mbedtls_time(NULL), &now) != 0) { + return MBEDTLS_ERR_X509_FATAL_ERROR; + } +#endif #if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) /* resume if we had an operation in progress */ @@ -2410,14 +2577,16 @@ static int x509_crt_verify_chain( ver_chain->len++; flags = &cur->flags; +#if defined(MBEDTLS_HAVE_TIME_DATE) /* Check time-validity (all certificates) */ - if (mbedtls_x509_time_is_past(&child->valid_to)) { + if (mbedtls_x509_time_cmp(&child->valid_to, &now) < 0) { *flags |= MBEDTLS_X509_BADCERT_EXPIRED; } - if (mbedtls_x509_time_is_future(&child->valid_from)) { + if (mbedtls_x509_time_cmp(&child->valid_from, &now) > 0) { *flags |= MBEDTLS_X509_BADCERT_FUTURE; } +#endif /* Stop here for trusted roots (but not for trusted EE certs) */ if (child_is_trusted) { @@ -2468,7 +2637,8 @@ static int x509_crt_verify_chain( /* Look for a parent in trusted CAs or up the chain */ ret = x509_crt_find_parent(child, cur_trust_ca, &parent, &parent_is_trusted, &signature_is_good, - ver_chain->len - 1, self_cnt, rs_ctx); + ver_chain->len - 1, self_cnt, rs_ctx, + &now); #if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) if (rs_ctx != NULL && ret == MBEDTLS_ERR_ECP_IN_PROGRESS) { @@ -2517,7 +2687,7 @@ static int x509_crt_verify_chain( #if defined(MBEDTLS_X509_CRL_PARSE_C) /* Check trusted CA's CRL for the given crt */ - *flags |= x509_crt_verifycrl(child, parent, ca_crl, profile); + *flags |= x509_crt_verifycrl(child, parent, ca_crl, profile, &now); #else (void) ca_crl; #endif @@ -2530,6 +2700,202 @@ static int x509_crt_verify_chain( } } +#ifdef _WIN32 +#ifdef _MSC_VER +#pragma comment(lib, "ws2_32.lib") +#include +#include +#elif (defined(__MINGW32__) || defined(__MINGW64__)) && _WIN32_WINNT >= 0x0600 +#include +#include +#else +/* inet_pton() is not supported, fallback to software version */ +#define MBEDTLS_TEST_SW_INET_PTON +#endif +#elif defined(__sun) +/* Solaris requires -lsocket -lnsl for inet_pton() */ +#elif defined(__has_include) +#if __has_include() +#include +#endif +#if __has_include() +#include +#endif +#endif + +/* Use whether or not AF_INET6 is defined to indicate whether or not to use + * the platform inet_pton() or a local implementation (below). The local + * implementation may be used even in cases where the platform provides + * inet_pton(), e.g. when there are different includes required and/or the + * platform implementation requires dependencies on additional libraries. + * Specifically, Windows requires custom includes and additional link + * dependencies, and Solaris requires additional link dependencies. + * Also, as a coarse heuristic, use the local implementation if the compiler + * does not support __has_include(), or if the definition of AF_INET6 is not + * provided by headers included (or not) via __has_include() above. + * MBEDTLS_TEST_SW_INET_PTON is a bypass define to force testing of this code //no-check-names + * despite having a platform that has inet_pton. */ +#if !defined(AF_INET6) || defined(MBEDTLS_TEST_SW_INET_PTON) //no-check-names +/* Definition located further below to possibly reduce compiler inlining */ +static int x509_inet_pton_ipv4(const char *src, void *dst); + +#define li_cton(c, n) \ + (((n) = (c) - '0') <= 9 || (((n) = ((c)&0xdf) - 'A') <= 5 ? ((n) += 10) : 0)) + +static int x509_inet_pton_ipv6(const char *src, void *dst) +{ + const unsigned char *p = (const unsigned char *) src; + int nonzero_groups = 0, num_digits, zero_group_start = -1; + uint16_t addr[8]; + do { + /* note: allows excess leading 0's, e.g. 1:0002:3:... */ + uint16_t group = num_digits = 0; + for (uint8_t digit; num_digits < 4; num_digits++) { + if (li_cton(*p, digit) == 0) { + break; + } + group = (group << 4) | digit; + p++; + } + if (num_digits != 0) { + MBEDTLS_PUT_UINT16_BE(group, addr, nonzero_groups); + nonzero_groups++; + if (*p == '\0') { + break; + } else if (*p == '.') { + /* Don't accept IPv4 too early or late */ + if ((nonzero_groups == 0 && zero_group_start == -1) || + nonzero_groups >= 7) { + break; + } + + /* Walk back to prior ':', then parse as IPv4-mapped */ + int steps = 4; + do { + p--; + steps--; + } while (*p != ':' && steps > 0); + + if (*p != ':') { + break; + } + p++; + nonzero_groups--; + if (x509_inet_pton_ipv4((const char *) p, + addr + nonzero_groups) != 0) { + break; + } + + nonzero_groups += 2; + p = (const unsigned char *) ""; + break; + } else if (*p != ':') { + return -1; + } + } else { + /* Don't accept a second zero group or an invalid delimiter */ + if (zero_group_start != -1 || *p != ':') { + return -1; + } + zero_group_start = nonzero_groups; + + /* Accept a zero group at start, but it has to be a double colon */ + if (zero_group_start == 0 && *++p != ':') { + return -1; + } + + if (p[1] == '\0') { + ++p; + break; + } + } + ++p; + } while (nonzero_groups < 8); + + if (*p != '\0') { + return -1; + } + + if (zero_group_start != -1) { + if (nonzero_groups > 6) { + return -1; + } + int zero_groups = 8 - nonzero_groups; + int groups_after_zero = nonzero_groups - zero_group_start; + + /* Move the non-zero part to after the zeroes */ + if (groups_after_zero) { + memmove(addr + zero_group_start + zero_groups, + addr + zero_group_start, + groups_after_zero * sizeof(*addr)); + } + memset(addr + zero_group_start, 0, zero_groups * sizeof(*addr)); + } else { + if (nonzero_groups != 8) { + return -1; + } + } + memcpy(dst, addr, sizeof(addr)); + return 0; +} + +static int x509_inet_pton_ipv4(const char *src, void *dst) +{ + const unsigned char *p = (const unsigned char *) src; + uint8_t *res = (uint8_t *) dst; + uint8_t digit, num_digits = 0; + uint8_t num_octets = 0; + uint16_t octet; + + do { + octet = num_digits = 0; + do { + digit = *p - '0'; + if (digit > 9) { + break; + } + + /* Don't allow leading zeroes. These might mean octal format, + * which this implementation does not support. */ + if (octet == 0 && num_digits > 0) { + return -1; + } + + octet = octet * 10 + digit; + num_digits++; + p++; + } while (num_digits < 3); + + if (octet >= 256 || num_digits > 3 || num_digits == 0) { + return -1; + } + *res++ = (uint8_t) octet; + num_octets++; + } while (num_octets < 4 && *p++ == '.'); + return num_octets == 4 && *p == '\0' ? 0 : -1; +} + +#else + +static int x509_inet_pton_ipv6(const char *src, void *dst) +{ + return inet_pton(AF_INET6, src, dst) == 1 ? 0 : -1; +} + +static int x509_inet_pton_ipv4(const char *src, void *dst) +{ + return inet_pton(AF_INET, src, dst) == 1 ? 0 : -1; +} + +#endif /* !AF_INET6 || MBEDTLS_TEST_SW_INET_PTON */ //no-check-names + +size_t mbedtls_x509_crt_parse_cn_inet_pton(const char *cn, void *dst) +{ + return strchr(cn, ':') == NULL + ? x509_inet_pton_ipv4(cn, dst) == 0 ? 4 : 0 + : x509_inet_pton_ipv6(cn, dst) == 0 ? 16 : 0; +} + /* * Check for CN match */ @@ -2550,23 +2916,80 @@ static int x509_crt_check_cn(const mbedtls_x509_buf *name, return -1; } +static int x509_crt_check_san_ip(const mbedtls_x509_sequence *san, + const char *cn, size_t cn_len) +{ + uint32_t ip[4]; + cn_len = mbedtls_x509_crt_parse_cn_inet_pton(cn, ip); + if (cn_len == 0) { + return -1; + } + + for (const mbedtls_x509_sequence *cur = san; cur != NULL; cur = cur->next) { + const unsigned char san_type = (unsigned char) cur->buf.tag & + MBEDTLS_ASN1_TAG_VALUE_MASK; + if (san_type == MBEDTLS_X509_SAN_IP_ADDRESS && + cur->buf.len == cn_len && memcmp(cur->buf.p, ip, cn_len) == 0) { + return 0; + } + } + + return -1; +} + +static int x509_crt_check_san_uri(const mbedtls_x509_sequence *san, + const char *cn, size_t cn_len) +{ + for (const mbedtls_x509_sequence *cur = san; cur != NULL; cur = cur->next) { + const unsigned char san_type = (unsigned char) cur->buf.tag & + MBEDTLS_ASN1_TAG_VALUE_MASK; + if (san_type == MBEDTLS_X509_SAN_UNIFORM_RESOURCE_IDENTIFIER && + cur->buf.len == cn_len && memcmp(cur->buf.p, cn, cn_len) == 0) { + return 0; + } + } + + return -1; +} + /* * Check for SAN match, see RFC 5280 Section 4.2.1.6 */ -static int x509_crt_check_san(const mbedtls_x509_buf *name, +static int x509_crt_check_san(const mbedtls_x509_sequence *san, const char *cn, size_t cn_len) { - const unsigned char san_type = (unsigned char) name->tag & - MBEDTLS_ASN1_TAG_VALUE_MASK; - - /* dNSName */ - if (san_type == MBEDTLS_X509_SAN_DNS_NAME) { - return x509_crt_check_cn(name, cn, cn_len); + int san_ip = 0; + int san_uri = 0; + /* Prioritize DNS name over other subtypes due to popularity */ + for (const mbedtls_x509_sequence *cur = san; cur != NULL; cur = cur->next) { + switch ((unsigned char) cur->buf.tag & MBEDTLS_ASN1_TAG_VALUE_MASK) { + case MBEDTLS_X509_SAN_DNS_NAME: + if (x509_crt_check_cn(&cur->buf, cn, cn_len) == 0) { + return 0; + } + break; + case MBEDTLS_X509_SAN_IP_ADDRESS: + san_ip = 1; + break; + case MBEDTLS_X509_SAN_UNIFORM_RESOURCE_IDENTIFIER: + san_uri = 1; + break; + /* (We may handle other types here later.) */ + default: /* Unrecognized type */ + break; + } + } + if (san_ip) { + if (x509_crt_check_san_ip(san, cn, cn_len) == 0) { + return 0; + } + } + if (san_uri) { + if (x509_crt_check_san_uri(san, cn, cn_len) == 0) { + return 0; + } } - /* (We may handle other types here later.) */ - - /* Unrecognized type */ return -1; } @@ -2578,31 +3001,23 @@ static void x509_crt_verify_name(const mbedtls_x509_crt *crt, uint32_t *flags) { const mbedtls_x509_name *name; - const mbedtls_x509_sequence *cur; size_t cn_len = strlen(cn); if (crt->ext_types & MBEDTLS_X509_EXT_SUBJECT_ALT_NAME) { - for (cur = &crt->subject_alt_names; cur != NULL; cur = cur->next) { - if (x509_crt_check_san(&cur->buf, cn, cn_len) == 0) { - break; - } - } - - if (cur == NULL) { - *flags |= MBEDTLS_X509_BADCERT_CN_MISMATCH; + if (x509_crt_check_san(&crt->subject_alt_names, cn, cn_len) == 0) { + return; } } else { for (name = &crt->subject; name != NULL; name = name->next) { if (MBEDTLS_OID_CMP(MBEDTLS_OID_AT_CN, &name->oid) == 0 && x509_crt_check_cn(&name->val, cn, cn_len) == 0) { - break; + return; } } - if (name == NULL) { - *flags |= MBEDTLS_X509_BADCERT_CN_MISMATCH; - } } + + *flags |= MBEDTLS_X509_BADCERT_CN_MISMATCH; } /* @@ -2843,10 +3258,10 @@ void mbedtls_x509_crt_free(mbedtls_x509_crt *crt) mbedtls_asn1_sequence_free(cert_cur->ext_key_usage.next); mbedtls_asn1_sequence_free(cert_cur->subject_alt_names.next); mbedtls_asn1_sequence_free(cert_cur->certificate_policies.next); + mbedtls_asn1_sequence_free(cert_cur->authority_key_id.authorityCertIssuer.next); if (cert_cur->raw.p != NULL && cert_cur->own_buffer) { - mbedtls_platform_zeroize(cert_cur->raw.p, cert_cur->raw.len); - mbedtls_free(cert_cur->raw.p); + mbedtls_zeroize_and_free(cert_cur->raw.p, cert_cur->raw.len); } cert_prv = cert_cur; diff --git a/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_ecdsa_p256.h b/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_ecdsa_p256.h index d037bf20a..79870276b 100644 --- a/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_ecdsa_p256.h +++ b/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_ecdsa_p256.h @@ -35,14 +35,14 @@ typedef struct mcb_sce_ecc_public_wrapped_key extern "C" { #endif -typedef uintptr_t bootutil_ecdsa_p256_context; +typedef uintptr_t bootutil_ecdsa_context; -static inline void bootutil_ecdsa_p256_init (bootutil_ecdsa_p256_context * ctx) +static inline void bootutil_ecdsa_init (bootutil_ecdsa_context * ctx) { (void) ctx; } -static inline void bootutil_ecdsa_p256_drop (bootutil_ecdsa_p256_context * ctx) +static inline void bootutil_ecdsa_drop (bootutil_ecdsa_context * ctx) { (void) ctx; } diff --git a/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_image_ec256.c b/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_image_ec256.c index 6a6f11958..30e03b4eb 100644 --- a/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_image_ec256.c +++ b/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_image_ec256.c @@ -37,7 +37,7 @@ #include "mbedtls/oid.h" #include "mbedtls/asn1.h" - #include "bootutil/crypto/ecdsa_p256.h" + #include "bootutil/crypto/ecdsa.h" #include "bootutil_priv.h" #include "sce9_ecdsa_p256.h" @@ -52,7 +52,7 @@ static uint32_t aligned_sig[BOOTUTIL_CRYPTO_ECDSA_P256_SIGNATURE_SIZE_BYTES/4] = static uint32_t aligned_hash[BOOTUTIL_CRYPTO_SHA256_DIGEST_SIZE_BYTES/4] = {0}; static uint32_t aligned_pk[MCUBOOT_SCE9_ECC_PUBLIC_KEY_IDX_SIZE_BYTES/4] = {0}; -static int bootutil_ecdsa_p256_verify (bootutil_ecdsa_p256_context * ctx, +static int bootutil_ecdsa_verify (bootutil_ecdsa_context * ctx, const uint8_t * pk, const uint8_t * hash, const uint8_t * sig) @@ -196,7 +196,7 @@ bootutil_verify_sig(uint8_t *hash, uint32_t hlen, uint8_t *sig, size_t slen, uint8_t key_id) { int rc; - bootutil_ecdsa_p256_context ctx; + bootutil_ecdsa_context ctx; uint8_t *pubkey; uint8_t *end; @@ -234,9 +234,9 @@ bootutil_verify_sig(uint8_t *hash, uint32_t hlen, uint8_t *sig, size_t slen, return -1; } - bootutil_ecdsa_p256_init(&ctx); - rc = bootutil_ecdsa_p256_verify(&ctx, (uint8_t*)&public_key_installed.value, hash, signature); - bootutil_ecdsa_p256_drop(&ctx); + bootutil_ecdsa_init(&ctx); + rc = bootutil_ecdsa_verify(&ctx, (uint8_t*)&public_key_installed.value, hash, signature); + bootutil_ecdsa_drop(&ctx); return rc; } diff --git a/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_image_rsa.c b/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_image_rsa.c index e0888e66f..c3583faaa 100644 --- a/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_image_rsa.c +++ b/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_image_rsa.c @@ -33,7 +33,7 @@ #ifdef MCUBOOT_SIGN_RSA #if defined MCUBOOT_USE_USER_DEFINED_CRYPTO_STACK #include "bootutil/sign_key.h" - #include "bootutil/crypto/sha256.h" + #include "bootutil/crypto/sha.h" #include "bootutil_priv.h" #include "bootutil/fault_injection_hardening.h" @@ -96,17 +96,17 @@ extern fsp_err_t R_SCE_Rsa3072ModularExponentEncryptPrivate(uint32_t * InData_Ke static void pss_mgf1(uint8_t *mask, const uint8_t *hash) { - bootutil_sha256_context ctx; + bootutil_sha_context ctx; uint8_t counter[4] = { 0, 0, 0, 0 }; uint8_t htmp[PSS_HLEN]; int count = PSS_MASK_LEN; int bytes; while (count > 0) { - bootutil_sha256_init(&ctx); - bootutil_sha256_update(&ctx, hash, PSS_HLEN); - bootutil_sha256_update(&ctx, counter, 4); - bootutil_sha256_finish(&ctx, htmp); + bootutil_sha_init(&ctx); + bootutil_sha_update(&ctx, hash, PSS_HLEN); + bootutil_sha_update(&ctx, counter, 4); + bootutil_sha_finish(&ctx, htmp); counter[3]++; @@ -119,7 +119,7 @@ pss_mgf1(uint8_t *mask, const uint8_t *hash) count -= bytes; } - bootutil_sha256_drop(&ctx); + bootutil_sha_drop(&ctx); } /* @@ -131,7 +131,7 @@ static fih_int sce9_bootutil_cmp_rsasig(uint8_t * pub_key, uint8_t *hash, uint32_t hlen, uint8_t *sig) { - bootutil_sha256_context shactx; + bootutil_sha_context shactx; uint8_t em[PSS_EMLEN]; uint8_t db_mask[PSS_MASK_LEN]; uint8_t h2[PSS_HLEN]; @@ -250,12 +250,12 @@ sce9_bootutil_cmp_rsasig(uint8_t * pub_key, uint8_t *hash, uint32_t hlen, /* Step 12. Let M' = 0x00 00 00 00 00 00 00 00 || mHash || salt; */ /* Step 13. Let H' = Hash(M') */ - bootutil_sha256_init(&shactx); - bootutil_sha256_update(&shactx, pss_zeros, 8); - bootutil_sha256_update(&shactx, hash, PSS_HLEN); - bootutil_sha256_update(&shactx, &db_mask[PSS_MASK_SALT_POS], PSS_SLEN); - bootutil_sha256_finish(&shactx, h2); - bootutil_sha256_drop(&shactx); + bootutil_sha_init(&shactx); + bootutil_sha_update(&shactx, pss_zeros, 8); + bootutil_sha_update(&shactx, hash, PSS_HLEN); + bootutil_sha_update(&shactx, &db_mask[PSS_MASK_SALT_POS], PSS_SLEN); + bootutil_sha_finish(&shactx, h2); + bootutil_sha_drop(&shactx); /* Step 14. If H = H', output "consistent". Otherwise, output * "inconsistent". */ diff --git a/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_sha256.h b/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_sha256.h index 156886306..a72137e19 100644 --- a/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_sha256.h +++ b/ra/fsp/src/rm_mcuboot_port/custom_crypto_stacks/protected_mode/sce9_sha256.h @@ -17,18 +17,18 @@ extern "C" { #endif -typedef struct sce_sha_md5_handle bootutil_sha256_context; -static inline void bootutil_sha256_init (bootutil_sha256_context * ctx) +typedef struct sce_sha_md5_handle bootutil_sha_context; +static inline void bootutil_sha_init (bootutil_sha_context * ctx) { R_SCE_SHA256_Init(ctx); } -static inline void bootutil_sha256_drop (bootutil_sha256_context * ctx) +static inline void bootutil_sha_drop (bootutil_sha_context * ctx) { (void) ctx; } -static inline int bootutil_sha256_update (bootutil_sha256_context * ctx, const void * data, uint32_t data_len) +static inline int bootutil_sha_update (bootutil_sha_context * ctx, const void * data, uint32_t data_len) { fsp_err_t fsp_err = FSP_SUCCESS; fsp_err = R_SCE_SHA256_Update(ctx, (uint8_t *) data, data_len); @@ -40,7 +40,7 @@ static inline int bootutil_sha256_update (bootutil_sha256_context * ctx, const v return 0; } -static inline int bootutil_sha256_finish (bootutil_sha256_context * ctx, uint8_t * output) +static inline int bootutil_sha_finish (bootutil_sha_context * ctx, uint8_t * output) { fsp_err_t fsp_err = FSP_SUCCESS; uint32_t digest_length = 0; diff --git a/ra/fsp/src/rm_mcuboot_port/flash_map.c b/ra/fsp/src/rm_mcuboot_port/flash_map.c index a4aea2814..d6e968d18 100644 --- a/ra/fsp/src/rm_mcuboot_port/flash_map.c +++ b/ra/fsp/src/rm_mcuboot_port/flash_map.c @@ -16,8 +16,7 @@ #include "r_flash_lp.h" #endif -#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI - #include "r_qspi.h" +#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI #include "r_spi_flash_api.h" #endif @@ -47,10 +46,8 @@ extern void * const gp_mcuboot_flash_ctrl; extern flash_cfg_t const * const gp_mcuboot_flash_cfg; -#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI - -extern qspi_instance_ctrl_t * const gp_mcuboot_qspi_ctrl; -extern spi_flash_cfg_t const * const gp_mcuboot_qspi_cfg; +#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI +extern spi_flash_instance_t const * const gp_mcuboot_xspi_instance; #endif #if RM_MCUBOOT_PORT_BUFFERED_WRITE_ENABLE @@ -69,11 +66,11 @@ static rm_mcuboot_port_flush_buffer_t g_internal_flash_flush_buffer = .g_current_block = UINT32_MAX, }; - #ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI - #define RM_MCUBOOT_PORT_QSPI_FLUSH_BUFFER_SIZE_WORDS (256U) -uint32_t g_rm_mcuboot_port_qspi_write_ram[RM_MCUBOOT_PORT_QSPI_FLUSH_BUFFER_SIZE_WORDS]; + #ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI + #define RM_MCUBOOT_PORT_XSPI_FLUSH_BUFFER_SIZE_WORDS (256U) +uint32_t g_rm_mcuboot_port_xspi_write_ram[RM_MCUBOOT_PORT_XSPI_FLUSH_BUFFER_SIZE_WORDS]; -static rm_mcuboot_port_flush_buffer_t g_qspi_flush_buffer = +static rm_mcuboot_port_flush_buffer_t g_xspi_flush_buffer = { .g_current_block = UINT32_MAX, }; @@ -82,8 +79,8 @@ static rm_mcuboot_port_flush_buffer_t g_qspi_flush_buffer = static rm_mcuboot_port_flush_buffer_t * gp_flush_buffer_lookup[2] = { &g_internal_flash_flush_buffer, - #ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI - &g_qspi_flush_buffer + #ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI + &g_xspi_flush_buffer #endif }; #endif @@ -100,8 +97,8 @@ static const struct flash_area flash_map[] = }, { .fa_id = FLASH_AREA_2_ID, -#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI - .fa_device_id = FLASH_DEVICE_QSPI, +#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI + .fa_device_id = FLASH_DEVICE_EXTERNAL_FLASH, #else .fa_device_id = FLASH_DEVICE_INTERNAL_FLASH, #endif @@ -117,8 +114,8 @@ static const struct flash_area flash_map[] = }, { .fa_id = FLASH_AREA_3_ID, -#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI - .fa_device_id = FLASH_DEVICE_QSPI, +#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI + .fa_device_id = FLASH_DEVICE_EXTERNAL_FLASH, #else .fa_device_id = FLASH_DEVICE_INTERNAL_FLASH, #endif @@ -144,11 +141,11 @@ static const struct flash_area * prv_lookup_flash_area(int id); static const uint32_t flash_map_entry_num = sizeof(flash_map) / sizeof(struct flash_area); static bool g_internal_flash_driver_open = false; -#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI +#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI static bool g_external_flash_driver_open = false; #endif -#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI +#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI /*< Waits till QSPI write or erase is completed. */ static fsp_err_t get_flash_status (void) @@ -160,7 +157,7 @@ static fsp_err_t get_flash_status (void) do { /* Get status from QSPI flash device */ - err = R_QSPI_StatusGet(gp_mcuboot_qspi_ctrl, &status); + err = gp_mcuboot_xspi_instance->p_api->statusGet(gp_mcuboot_xspi_instance->p_ctrl, &status); if (FSP_SUCCESS != err) { return err; @@ -200,9 +197,9 @@ int flash_area_open (uint8_t id, const struct flash_area ** area) g_internal_flash_driver_open = true; } -#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI +#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI #if RM_MCUBOOT_PORT_BUFFERED_WRITE_ENABLE - g_qspi_flush_buffer.p_flush_buffer = g_rm_mcuboot_port_qspi_write_ram; + g_xspi_flush_buffer.p_flush_buffer = g_rm_mcuboot_port_xspi_write_ram; #endif /* The QSPI driver is expected to have been opened by the user and set up for DirectWrite mode. */ @@ -275,18 +272,18 @@ int flash_on_chip_flush (const struct flash_area * area) } else { - #ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI - BOOT_LOG_DBG("write flush qspi buffer, addr=%#x, len=%#x", + #ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI + BOOT_LOG_DBG("write flush xspi buffer, addr=%#x, len=%#x", (unsigned int) p_area_flush_buffer->g_current_block, - (unsigned int) (qspi_instance_ctrl_t *) gp_mcuboot_qspi_ctrl->p_cfg->page_size_bytes); + (unsigned int) gp_mcuboot_xspi_instance->p_cfg->page_size_bytes); err = (int) get_flash_status(); if (0 == err) { err = - (int) R_QSPI_Write(gp_mcuboot_qspi_ctrl, + (int) gp_mcuboot_xspi_instance->p_api->write(gp_mcuboot_xspi_instance->p_ctrl, (uint8_t *) p_area_flush_buffer->p_flush_buffer, (uint8_t *) p_area_flush_buffer->g_current_block, - (uint32_t) (qspi_instance_ctrl_t *) gp_mcuboot_qspi_ctrl->p_cfg->page_size_bytes); + (uint32_t) gp_mcuboot_xspi_instance->p_cfg->page_size_bytes); } #endif } @@ -321,9 +318,9 @@ int flash_area_write (const struct flash_area * area, uint32_t off, const void * } else { - #ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI - p_write_buffer = g_rm_mcuboot_port_qspi_write_ram; - write_align_size = (uint32_t) (qspi_instance_ctrl_t *) gp_mcuboot_qspi_ctrl->p_cfg->page_size_bytes; + #ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI + p_write_buffer = g_rm_mcuboot_port_xspi_write_ram; + write_align_size = (uint32_t) gp_mcuboot_xspi_instance->p_cfg->page_size_bytes; #endif } @@ -375,8 +372,8 @@ int flash_area_write (const struct flash_area * area, uint32_t off, const void * } else { -#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI - uint32_t page_size = (uint32_t) (qspi_instance_ctrl_t *) gp_mcuboot_qspi_ctrl->p_cfg->page_size_bytes; +#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI + uint32_t page_size = (uint32_t) gp_mcuboot_xspi_instance->p_cfg->page_size_bytes; uint32_t pages_to_write = len / page_size; uint32_t pages_written = 0; while (pages_to_write != 0) @@ -385,7 +382,7 @@ int flash_area_write (const struct flash_area * area, uint32_t off, const void * if (0 == err) { err = - (int) R_QSPI_Write(gp_mcuboot_qspi_ctrl, + (int) gp_mcuboot_xspi_instance->p_api->write(gp_mcuboot_xspi_instance->p_ctrl, (uint8_t *) ((uint32_t) src + (pages_written * page_size)), (uint8_t *) (write_addr + (pages_written * page_size)), page_size); pages_to_write--; @@ -451,13 +448,13 @@ int flash_area_erase (const struct flash_area * area, uint32_t off, uint32_t len else { err = FSP_ERR_UNSUPPORTED; -#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI +#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI if (!(len % BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE)) { err = get_flash_status(); if (FSP_SUCCESS == err) { - err = R_QSPI_Erase(gp_mcuboot_qspi_ctrl, (uint8_t *) erase_address, len); + err = gp_mcuboot_xspi_instance->p_api->erase(gp_mcuboot_xspi_instance->p_ctrl, (uint8_t *) erase_address, len); } } #endif @@ -476,8 +473,8 @@ uint32_t flash_area_align (const struct flash_area * area) } else { -#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI - write_alignment = (uint32_t) (qspi_instance_ctrl_t *) gp_mcuboot_qspi_ctrl->p_cfg->page_size_bytes; +#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI + write_alignment = (uint32_t) gp_mcuboot_xspi_instance->p_cfg->page_size_bytes; #endif } @@ -529,9 +526,9 @@ int flash_area_get_sectors (int fa_id, uint32_t * count, struct flash_sector * s *count = total_count; retval = 0; } - else if (fa->fa_device_id == FLASH_DEVICE_QSPI) + else if (fa->fa_device_id == FLASH_DEVICE_EXTERNAL_FLASH) { - #ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI +#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI uint32_t total_count = 0; for (size_t off = 0; off < fa->fa_size; off += sector_size) { @@ -647,7 +644,7 @@ int flash_on_chip_cleanup (void) g_internal_flash_driver_open = false; } -#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_QSPI +#ifdef RM_MCUBOOT_PORT_CFG_SECONDARY_USE_XSPI if (g_external_flash_driver_open) { #if RM_MCUBOOT_PORT_BUFFERED_WRITE_ENABLE @@ -663,7 +660,7 @@ int flash_on_chip_cleanup (void) fsp_err_t err = get_flash_status(); if (FSP_SUCCESS == err) { - err = R_QSPI_Close(gp_mcuboot_flash_ctrl); + err = gp_mcuboot_xspi_instance->p_api->close(gp_mcuboot_flash_ctrl); if (FSP_SUCCESS != err) { return -1; diff --git a/ra/fsp/src/rm_mcuboot_port/rm_mcuboot_port_sign.py b/ra/fsp/src/rm_mcuboot_port/rm_mcuboot_port_sign.py index 5c0a0a5d9..487331e02 100644 --- a/ra/fsp/src/rm_mcuboot_port/rm_mcuboot_port_sign.py +++ b/ra/fsp/src/rm_mcuboot_port/rm_mcuboot_port_sign.py @@ -6,6 +6,9 @@ # Determine root of bootloader project to find related files boot_project_root = os.path.abspath(os.path.join(os.path.abspath(os.path.dirname(__file__)), '../../../..')) +# Initialize an empty string for the message +message_str = "" + # Make sure python3 is used if not sys.version_info >= (3, 3): print("ERROR: The MCUboot signing script requires version Python version 3.3 or later. The python command can be modified in the MCUboot properties. Current Python version used is:\n" + sys.version) @@ -15,7 +18,7 @@ if os.getenv('MCUBOOT_IMAGE_VERSION') is not None: # Version defined in environment variable if '-v' in sys.argv or '--version' in sys.argv: - print('ERROR: Remove -v and --version from Signing Options > Custom and Signing Options > TrustZone > Custom (Image 2) to use MCUBOOT_IMAGE_VERSION.') + print('ERROR: Remove -v and --version from Signing Options > Custom and Signing Options > TrustZone > Custom (Image 2) to use MCUBOOT_IMAGE_VERSION.', file=sys.stderr) sys.exit(1) else: sys.argv.insert(sys.argv.index('sign') + 1, '--version') @@ -27,7 +30,7 @@ pass else: # Version missing - print('ERROR: The application image version must be defined. Pass version using "-v" or "--version" or by defining the environment variable MCUBOOT_IMAGE_VERSION.') + print('ERROR: The application image version must be defined. Pass version using "-v" or "--version" or by defining the environment variable MCUBOOT_IMAGE_VERSION.', file=sys.stderr) sys.exit(1) # Determine key @@ -36,11 +39,11 @@ # Key defined in environment variable # Verify the key exists if not os.path.exists(mcuboot_image_signing_key): - print('ERROR: Could not find conversion tool set in MCUBOOT_IMAGE_SIGNING_KEY: ' + mcuboot_image_signing_key) + print('ERROR: Could not find conversion tool set in MCUBOOT_IMAGE_SIGNING_KEY: ' + mcuboot_image_signing_key, file=sys.stderr) sys.exit(1) # Add key to command line if '-k' in sys.argv or '--key' in sys.argv: - print('ERROR: Remove -k and --key from Signing Options > Custom and Signing Options > TrustZone > Custom (Image 2) to use MCUBOOT_IMAGE_SIGNING_KEY.') + print('ERROR: Remove -k and --key from Signing Options > Custom and Signing Options > TrustZone > Custom (Image 2) to use MCUBOOT_IMAGE_SIGNING_KEY.', file=sys.stderr) sys.exit(1) else: sys.argv.insert(sys.argv.index('sign') + 1, '--key') @@ -53,11 +56,11 @@ # Key defined in environment variable # Verify the key exists if not os.path.exists(mcuboot_image_enc_key): - print('ERROR: Could not find conversion tool set in MCUBOOT_IMAGE_ENC_KEY: ' + mcuboot_image_enc_key) + print('ERROR: Could not find conversion tool set in MCUBOOT_IMAGE_ENC_KEY: ' + mcuboot_image_enc_key, file=sys.stderr) sys.exit(1) # Add key to command line if '-E' in sys.argv or '--encrypt' in sys.argv: - print('ERROR: Remove -E and --encrypt from Signing Options > Custom and Signing Options > TrustZone > Custom (Image 2) to use MCUBOOT_IMAGE_ENC_KEY.') + print('ERROR: Remove -E and --encrypt from Signing Options > Custom and Signing Options > TrustZone > Custom (Image 2) to use MCUBOOT_IMAGE_ENC_KEY.', file=sys.stderr) sys.exit(1) else: sys.argv.insert(sys.argv.index('sign') + 1, '--encrypt') @@ -73,7 +76,7 @@ # Determine if the input file is .elf or binary format input_file = sys.argv[-2] if not os.path.exists(input_file): - print('ERROR: Could not find input file: ' + input_file) + print('ERROR: Could not find input file: ' + input_file, file=sys.stderr) sys.exit(1) with open(input_file, 'rb') as f: contents = f.read(4) @@ -85,7 +88,7 @@ # Conversion tool defined in environment variable conversion_tool = os.getenv('MCUBOOT_APP_BIN_CONVERTER') if not os.path.exists(conversion_tool): - print('ERROR: Could not find conversion tool set in MCUBOOT_APP_BIN_CONVERTER: ' + conversion_tool) + print('ERROR: Could not find conversion tool set in MCUBOOT_APP_BIN_CONVERTER: ' + conversion_tool, file=sys.stderr) sys.exit(1) elif shutil.which('arm-none-eabi-objcopy') is not None: conversion_tool = 'arm-none-eabi-objcopy' @@ -96,7 +99,7 @@ elif shutil.which('ielftool') is not None: conversion_tool = 'ielftool' else: - print('ERROR: Conversion tool not found. Add objcopy, arm-none-eabi-objcopy, fromelf, or ielftool to the command line or define the full path to one of these in the environment variable MCUBOOT_APP_BIN_CONVERTER') + print('ERROR: Conversion tool not found. Add objcopy, arm-none-eabi-objcopy, fromelf, or ielftool to the command line or define the full path to one of these in the environment variable MCUBOOT_APP_BIN_CONVERTER', file=sys.stderr) sys.exit(1) # Determine conversion command line @@ -109,13 +112,13 @@ elif 'ielftool' in conversion_tool: conversion_command = [conversion_tool, '--bin', input_file, temp_unsigned_binary] else: - print('ERROR: Conversion tool not supported. MCUBOOT_APP_BIN_CONVERTER must be objcopy, arm-none-eabi-objcopy, fromelf, or ielftool.') + print('ERROR: Conversion tool not supported. MCUBOOT_APP_BIN_CONVERTER must be objcopy, arm-none-eabi-objcopy, fromelf, or ielftool.', file=sys.stderr) sys.exit(1) # Convert ELF to binary. subprocess.check_output(conversion_command) if not os.path.exists(temp_unsigned_binary): - print('ERROR: Conversion from elf to binary failed.') + print('ERROR: Conversion from elf to binary failed.', file=sys.stderr) sys.exit(1) # Update command line to pass binary instead of elf file to imgtool diff --git a/ra/fsp/src/rm_mqtt_onchip_da16xxx/rm_mqtt_onchip_da16xxx.c b/ra/fsp/src/rm_mqtt_onchip_da16xxx/rm_mqtt_onchip_da16xxx.c index 096accd73..1ace9e1d6 100644 --- a/ra/fsp/src/rm_mqtt_onchip_da16xxx/rm_mqtt_onchip_da16xxx.c +++ b/ra/fsp/src/rm_mqtt_onchip_da16xxx/rm_mqtt_onchip_da16xxx.c @@ -391,7 +391,7 @@ fsp_err_t RM_MQTT_DA16XXX_Publish (mqtt_onchip_da16xxx_instance_ctrl_t * p_ctrl atcmd.at_cmd_string_length = 0; atcmd.p_response_buffer = p_ctrl->cmd_rx_buff; atcmd.response_buffer_size = sizeof(p_ctrl->cmd_rx_buff); - atcmd.timeout_ms = MQTT_ONCHIP_DA16XXX_TIMEOUT_1SEC; + atcmd.timeout_ms = p_ctrl->p_cfg->tx_timeout; atcmd.p_expect_code = MQTT_ONCHIP_DA16XXX_RETURN_TEXT_OK; atcmd.comm_ch_id = 0; @@ -415,6 +415,7 @@ fsp_err_t RM_MQTT_DA16XXX_Publish (mqtt_onchip_da16xxx_instance_ctrl_t * p_ctrl p_pub_info->p_payload, p_pub_info->p_topic_name); + /* Only takes TX mutex if expected code is NULL, which enables simultaneous publish/subscribe */ atcmd.p_expect_code = NULL; FSP_ERROR_RETURN(FSP_SUCCESS == p_transport_instance->p_api->atCommandSendThreadSafe(p_transport_instance->p_ctrl, &atcmd), diff --git a/ra/fsp/src/rm_psa_crypto/aes_alt.c b/ra/fsp/src/rm_psa_crypto/aes_alt.c index 4bfbbc55c..6b815ea07 100644 --- a/ra/fsp/src/rm_psa_crypto/aes_alt.c +++ b/ra/fsp/src/rm_psa_crypto/aes_alt.c @@ -18,11 +18,10 @@ * * This file is part of mbed TLS (https://tls.mbed.org) */ - /* * The AES block cipher was designed by Vincent Rijmen and Joan Daemen. * - * http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf + * https://csrc.nist.gov/csrc/media/projects/cryptographic-standards-and-guidelines/documents/aes-development/rijndael-ammended.pdf * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf */ @@ -37,7 +36,36 @@ #include "mbedtls/platform.h" #include "mbedtls/platform_util.h" #include "mbedtls/error.h" - #if defined(MBEDTLS_PADLOCK_C) + +#if defined(MBEDTLS_ARCH_IS_ARM64) +#if !defined(MBEDTLS_AESCE_C) && defined(MBEDTLS_AES_USE_HARDWARE_ONLY) +#error "MBEDTLS_AES_USE_HARDWARE_ONLY defined, but not all prerequisites" +#endif +#endif + +#if defined(MBEDTLS_ARCH_IS_X64) +#if !defined(MBEDTLS_AESNI_C) && defined(MBEDTLS_AES_USE_HARDWARE_ONLY) +#error "MBEDTLS_AES_USE_HARDWARE_ONLY defined, but not all prerequisites" +#endif +#endif + +#if defined(MBEDTLS_ARCH_IS_X86) +#if defined(MBEDTLS_AES_USE_HARDWARE_ONLY) && !defined(MBEDTLS_AESNI_C) +#error "MBEDTLS_AES_USE_HARDWARE_ONLY defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PADLOCK_C) +#if !defined(MBEDTLS_HAVE_ASM) +#error "MBEDTLS_PADLOCK_C defined, but not all prerequisites" +#endif +#if defined(MBEDTLS_AES_USE_HARDWARE_ONLY) +#error "MBEDTLS_AES_USE_HARDWARE_ONLY cannot be defined when " \ + "MBEDTLS_PADLOCK_C is set" +#endif +#endif +#endif + +#if defined(MBEDTLS_PADLOCK_C) #include "mbedtls/padlock.h" #endif #if defined(MBEDTLS_AESNI_C) @@ -74,7 +102,7 @@ } #endif #ifdef FSP_NOT_DEFINED -#if defined(MBEDTLS_PADLOCK_C) && defined(MBEDTLS_HAVE_X86) +#if defined(MBEDTLS_VIA_PADLOCK_HAVE_CODE) static int aes_padlock_ace = -1; #endif @@ -82,6 +110,8 @@ static int aes_padlock_ace = -1; /* * Forward S-box */ + #if !defined(MBEDTLS_AES_ENCRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_ENC_ALT) || \ + !defined(MBEDTLS_AES_SETKEY_DEC_ALT) static const unsigned char FSb[256] = { 0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, @@ -117,6 +147,8 @@ static const unsigned char FSb[256] = 0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16 }; +#endif /* !defined(MBEDTLS_AES_ENCRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_ENC_ALT) || \ + !defined(MBEDTLS_AES_SETKEY_DEC_ALT) */ /* * Forward tables @@ -188,6 +220,7 @@ static const unsigned char FSb[256] = V(C3, 41, 41, 82), V(B0, 99, 99, 29), V(77, 2D, 2D, 5A), V(11, 0F, 0F, 1E), \ V(CB, B0, B0, 7B), V(FC, 54, 54, A8), V(D6, BB, BB, 6D), V(3A, 16, 16, 2C) +#if !defined(MBEDTLS_AES_ENCRYPT_ALT) #define V(a, b, c, d) 0x##a##b##c##d static const uint32_t FT0[256] = { FT }; #undef V @@ -208,8 +241,11 @@ static const uint32_t FT3[256] = { FT }; #endif /* !MBEDTLS_AES_FEWER_TABLES */ +#endif /* !defined(MBEDTLS_AES_ENCRYPT_ALT) */ + #undef FT +#if !defined(MBEDTLS_AES_DECRYPT_ALT) /* * Reverse S-box */ @@ -248,6 +284,7 @@ static const unsigned char RSb[256] = 0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26, 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D }; +#endif /* defined(MBEDTLS_AES_DECRYPT_ALT)) */ /* * Reverse tables @@ -319,6 +356,8 @@ static const unsigned char RSb[256] = V(71, 01, A8, 39), V(DE, B3, 0C, 08), V(9C, E4, B4, D8), V(90, C1, 56, 64), \ V(61, 84, CB, 7B), V(70, B6, 32, D5), V(74, 5C, 6C, 48), V(42, 57, B8, D0) +#if !defined(MBEDTLS_AES_DECRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) + #define V(a, b, c, d) 0x##a##b##c##d static const uint32_t RT0[256] = { RT }; #undef V @@ -339,8 +378,11 @@ static const uint32_t RT3[256] = { RT }; #endif /* !MBEDTLS_AES_FEWER_TABLES */ +#endif /* !defined(MBEDTLS_AES_DECRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) */ + #undef RT +#if !defined(MBEDTLS_AES_SETKEY_ENC_ALT) /* * Round constants */ @@ -350,31 +392,44 @@ static const uint32_t RCON[10] = 0x00000010, 0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036 }; +#endif /* !defined(MBEDTLS_AES_SETKEY_ENC_ALT) */ #else /* MBEDTLS_AES_ROM_TABLES */ /* * Forward S-box & tables */ +#if !defined(MBEDTLS_AES_ENCRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_ENC_ALT) || \ + !defined(MBEDTLS_AES_SETKEY_DEC_ALT) static unsigned char FSb[256]; +#endif /* !defined(MBEDTLS_AES_ENCRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_ENC_ALT) || \ + !defined(MBEDTLS_AES_SETKEY_DEC_ALT) */ +#if !defined(MBEDTLS_AES_ENCRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_ENC_ALT) static uint32_t FT0[256]; #if !defined(MBEDTLS_AES_FEWER_TABLES) static uint32_t FT1[256]; static uint32_t FT2[256]; static uint32_t FT3[256]; #endif /* !MBEDTLS_AES_FEWER_TABLES */ +#endif /* !defined(MBEDTLS_AES_ENCRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_ENC_ALT) */ /* * Reverse S-box & tables */ +#if !(defined(MBEDTLS_AES_SETKEY_ENC_ALT) && defined(MBEDTLS_AES_DECRYPT_ALT)) static unsigned char RSb[256]; +#endif /* !(defined(MBEDTLS_AES_SETKEY_ENC_ALT) && defined(MBEDTLS_AES_DECRYPT_ALT)) */ + +#if !defined(MBEDTLS_AES_DECRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) static uint32_t RT0[256]; #if !defined(MBEDTLS_AES_FEWER_TABLES) static uint32_t RT1[256]; static uint32_t RT2[256]; static uint32_t RT3[256]; #endif /* !MBEDTLS_AES_FEWER_TABLES */ +#endif /* !defined(MBEDTLS_AES_DECRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) */ +#if !defined(MBEDTLS_AES_SETKEY_ENC_ALT) /* * Round constants */ @@ -391,25 +446,26 @@ static int aes_init_done = 0; static void aes_gen_tables(void) { - int i, x, y, z; - int pow[256]; - int log[256]; + int i; + uint8_t x, y, z; + uint8_t pow[256]; + uint8_t log[256]; /* * compute pow and log tables over GF(2^8) */ for (i = 0, x = 1; i < 256; i++) { pow[i] = x; - log[x] = i; - x = MBEDTLS_BYTE_0(x ^ XTIME(x)); + log[x] = (uint8_t) i; + x ^= XTIME(x); } /* * calculate the round constants */ for (i = 0, x = 1; i < 10; i++) { - RCON[i] = (uint32_t) x; - x = MBEDTLS_BYTE_0(XTIME(x)); + RCON[i] = x; + x = XTIME(x); } /* @@ -421,13 +477,13 @@ static void aes_gen_tables(void) for (i = 1; i < 256; i++) { x = pow[255 - log[i]]; - y = x; y = MBEDTLS_BYTE_0((y << 1) | (y >> 7)); - x ^= y; y = MBEDTLS_BYTE_0((y << 1) | (y >> 7)); - x ^= y; y = MBEDTLS_BYTE_0((y << 1) | (y >> 7)); - x ^= y; y = MBEDTLS_BYTE_0((y << 1) | (y >> 7)); + y = x; y = (y << 1) | (y >> 7); + x ^= y; y = (y << 1) | (y >> 7); + x ^= y; y = (y << 1) | (y >> 7); + x ^= y; y = (y << 1) | (y >> 7); x ^= y ^ 0x63; - FSb[i] = (unsigned char) x; + FSb[i] = x; RSb[x] = (unsigned char) i; } @@ -436,8 +492,8 @@ static void aes_gen_tables(void) */ for (i = 0; i < 256; i++) { x = FSb[i]; - y = MBEDTLS_BYTE_0(XTIME(x)); - z = MBEDTLS_BYTE_0(y ^ x); + y = XTIME(x); + z = y ^ x; FT0[i] = ((uint32_t) y) ^ ((uint32_t) x << 8) ^ @@ -452,6 +508,7 @@ static void aes_gen_tables(void) x = RSb[i]; +#if !defined(MBEDTLS_AES_DECRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) RT0[i] = ((uint32_t) MUL(0x0E, x)) ^ ((uint32_t) MUL(0x09, x) << 8) ^ ((uint32_t) MUL(0x0D, x) << 16) ^ @@ -462,9 +519,12 @@ static void aes_gen_tables(void) RT2[i] = ROTL8(RT1[i]); RT3[i] = ROTL8(RT2[i]); #endif /* !MBEDTLS_AES_FEWER_TABLES */ +#endif /* !defined(MBEDTLS_AES_DECRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) */ } } +#endif /* !defined(MBEDTLS_AES_SETKEY_ENC_ALT) */ + #undef ROTL8 #endif /* MBEDTLS_AES_ROM_TABLES */ @@ -539,16 +599,19 @@ void mbedtls_aes_xts_free(mbedtls_aes_xts_context *ctx) * Note that the offset is in units of elements of buf, i.e. 32-bit words, * i.e. an offset of 1 means 4 bytes and so on. */ -#if (defined(MBEDTLS_PADLOCK_C) && defined(MBEDTLS_HAVE_X86)) || \ +#if (defined(MBEDTLS_VIA_PADLOCK_HAVE_CODE)) || \ (defined(MBEDTLS_AESNI_C) && MBEDTLS_AESNI_HAVE_CODE == 2) #define MAY_NEED_TO_ALIGN #endif + +#if defined(MAY_NEED_TO_ALIGN) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) || \ + !defined(MBEDTLS_AES_SETKEY_ENC_ALT) static unsigned mbedtls_aes_rk_offset(uint32_t *buf) { #if defined(MAY_NEED_TO_ALIGN) int align_16_bytes = 0; -#if defined(MBEDTLS_PADLOCK_C) && defined(MBEDTLS_HAVE_X86) +#if defined(MBEDTLS_VIA_PADLOCK_HAVE_CODE) if (aes_padlock_ace == -1) { aes_padlock_ace = mbedtls_padlock_has_support(MBEDTLS_PADLOCK_ACE); } @@ -579,6 +642,8 @@ static unsigned mbedtls_aes_rk_offset(uint32_t *buf) return 0; } +#endif /* defined(MAY_NEED_TO_ALIGN) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) || \ + !defined(MBEDTLS_AES_SETKEY_ENC_ALT) */ #ifdef FSP_NOT_DEFINED /* @@ -588,13 +653,14 @@ static unsigned mbedtls_aes_rk_offset(uint32_t *buf) int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits) { - unsigned int i; - uint32_t *RK; + uint32_t *RK; switch (keybits) { case 128: ctx->nr = 10; break; +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) case 192: ctx->nr = 12; break; case 256: ctx->nr = 14; break; +#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ default: return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; } @@ -614,20 +680,21 @@ int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, } #endif -#if defined(MBEDTLS_AESCE_C) && defined(MBEDTLS_HAVE_ARM64) - if (mbedtls_aesce_has_support()) { +#if defined(MBEDTLS_AESCE_HAVE_CODE) + if (MBEDTLS_AESCE_HAS_SUPPORT()) { return mbedtls_aesce_setkey_enc((unsigned char *) RK, key, keybits); } #endif - for (i = 0; i < (keybits >> 5); i++) { + #if !defined(MBEDTLS_AES_USE_HARDWARE_ONLY) + for (unsigned int i = 0; i < (keybits >> 5); i++) { RK[i] = MBEDTLS_GET_UINT32_LE(key, i << 2); } switch (ctx->nr) { case 10: - for (i = 0; i < 10; i++, RK += 4) { + for (unsigned int i = 0; i < 10; i++, RK += 4) { RK[4] = RK[0] ^ RCON[i] ^ ((uint32_t) FSb[MBEDTLS_BYTE_1(RK[3])]) ^ ((uint32_t) FSb[MBEDTLS_BYTE_2(RK[3])] << 8) ^ @@ -640,9 +707,10 @@ int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, } break; +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) case 12: - for (i = 0; i < 8; i++, RK += 6) { + for (unsigned int i = 0; i < 8; i++, RK += 6) { RK[6] = RK[0] ^ RCON[i] ^ ((uint32_t) FSb[MBEDTLS_BYTE_1(RK[5])]) ^ ((uint32_t) FSb[MBEDTLS_BYTE_2(RK[5])] << 8) ^ @@ -659,7 +727,7 @@ int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, case 14: - for (i = 0; i < 7; i++, RK += 8) { + for (unsigned int i = 0; i < 7; i++, RK += 8) { RK[8] = RK[0] ^ RCON[i] ^ ((uint32_t) FSb[MBEDTLS_BYTE_1(RK[7])]) ^ ((uint32_t) FSb[MBEDTLS_BYTE_2(RK[7])] << 8) ^ @@ -681,9 +749,11 @@ int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, RK[15] = RK[7] ^ RK[14]; } break; +#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ } return 0; +#endif /* !MBEDTLS_AES_USE_HARDWARE_ONLY */ } #endif /* !MBEDTLS_AES_SETKEY_ENC_ALT */ @@ -694,10 +764,13 @@ int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits) { - int i, j, ret; + #if !defined(MBEDTLS_AES_USE_HARDWARE_ONLY) + uint32_t *SK; +#endif + int ret; mbedtls_aes_context cty; uint32_t *RK; - uint32_t *SK; + mbedtls_aes_init(&cty); @@ -719,8 +792,8 @@ int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, } #endif -#if defined(MBEDTLS_AESCE_C) && defined(MBEDTLS_HAVE_ARM64) - if (mbedtls_aesce_has_support()) { +#if defined(MBEDTLS_AESCE_HAVE_CODE) + if (MBEDTLS_AESCE_HAS_SUPPORT()) { mbedtls_aesce_inverse_key( (unsigned char *) RK, (const unsigned char *) (cty.buf + cty.rk_offset), @@ -729,15 +802,16 @@ int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, } #endif +#if !defined(MBEDTLS_AES_USE_HARDWARE_ONLY) SK = cty.buf + cty.rk_offset + cty.nr * 4; *RK++ = *SK++; *RK++ = *SK++; *RK++ = *SK++; *RK++ = *SK++; - - for (i = ctx->nr - 1, SK -= 8; i > 0; i--, SK -= 8) { - for (j = 0; j < 4; j++, SK++) { +SK -= 8; + for (int i = ctx->nr - 1; i > 0; i--, SK -= 8) { + for (int j = 0; j < 4; j++, SK++) { *RK++ = AES_RT0(FSb[MBEDTLS_BYTE_0(*SK)]) ^ AES_RT1(FSb[MBEDTLS_BYTE_1(*SK)]) ^ AES_RT2(FSb[MBEDTLS_BYTE_2(*SK)]) ^ @@ -749,7 +823,7 @@ int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, *RK++ = *SK++; *RK++ = *SK++; *RK++ = *SK++; - +#endif /* !MBEDTLS_AES_USE_HARDWARE_ONLY */ exit: mbedtls_aes_free(&cty); @@ -1047,26 +1121,30 @@ int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx, } #endif -#if defined(MBEDTLS_AESCE_C) && defined(MBEDTLS_HAVE_ARM64) - if (mbedtls_aesce_has_support()) { +#if defined(MBEDTLS_AESCE_HAVE_CODE) + if (MBEDTLS_AESCE_HAS_SUPPORT()) { return mbedtls_aesce_crypt_ecb(ctx, mode, input, output); } #endif -#if defined(MBEDTLS_PADLOCK_C) && defined(MBEDTLS_HAVE_X86) +#if defined(MBEDTLS_VIA_PADLOCK_HAVE_CODE) if (aes_padlock_ace > 0) { return mbedtls_padlock_xcryptecb(ctx, mode, input, output); } #endif +#if !defined(MBEDTLS_AES_USE_HARDWARE_ONLY) if (mode == MBEDTLS_AES_ENCRYPT) { return mbedtls_internal_aes_encrypt(ctx, input, output); } else { return mbedtls_internal_aes_decrypt(ctx, input, output); } +#endif + } #if defined(MBEDTLS_CIPHER_MODE_CBC) + /* * AES-CBC buffer encryption/decryption */ @@ -1082,11 +1160,16 @@ int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx, return MBEDTLS_ERR_AES_BAD_INPUT_DATA; } + /* Nothing to do if length is zero. */ + if (length == 0) { + return 0; + } + if (length % 16) { return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; } -#if defined(MBEDTLS_PADLOCK_C) && defined(MBEDTLS_HAVE_X86) +#if defined(MBEDTLS_VIA_PADLOCK_HAVE_CODE) if (aes_padlock_ace > 0) { if (mbedtls_padlock_xcryptcbc(ctx, mode, length, iv, input, output) == 0) { return 0; @@ -1117,7 +1200,10 @@ typedef unsigned char mbedtls_be128[16]; * for machine endianness and hence works correctly on both big and little * endian machines. */ -static void mbedtls_gf128mul_x_ble(unsigned char r[16], +#if defined(MBEDTLS_AESCE_C) || defined(MBEDTLS_AESNI_C) +MBEDTLS_OPTIMIZE_FOR_PERFORMANCE +#endif +static inline void mbedtls_gf128mul_x_ble(unsigned char r[16], const unsigned char x[16]) { uint64_t a, b, ra, rb; @@ -1134,7 +1220,13 @@ static void mbedtls_gf128mul_x_ble(unsigned char r[16], /* * AES-XTS buffer encryption/decryption +* + * Use of MBEDTLS_OPTIMIZE_FOR_PERFORMANCE here and for mbedtls_gf128mul_x_ble() + * is a 3x performance improvement for gcc -Os, if we have hardware AES support. */ +#if defined(MBEDTLS_AESCE_C) || defined(MBEDTLS_AESNI_C) +MBEDTLS_OPTIMIZE_FOR_PERFORMANCE +#endif int mbedtls_aes_crypt_xts(mbedtls_aes_xts_context *ctx, int mode, size_t length, @@ -1178,7 +1270,7 @@ int mbedtls_aes_crypt_xts(mbedtls_aes_xts_context *ctx, } while (blocks--) { - if (leftover && (mode == MBEDTLS_AES_DECRYPT) && blocks == 0) { + if (MBEDTLS_UNLIKELY(leftover && (mode == MBEDTLS_AES_DECRYPT) && blocks == 0)) { /* We are on the last block in a decrypt operation that has * leftover bytes, so we need to use the next tweak for this block, * and this tweak for the leftover bytes. Save the current tweak for @@ -1474,45 +1566,53 @@ int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx, * * http://csrc.nist.gov/archive/aes/rijndael/rijndael-vals.zip */ -static const unsigned char aes_test_ecb_dec[3][16] = +static const unsigned char aes_test_ecb_dec[][16] = { { 0x44, 0x41, 0x6A, 0xC2, 0xD1, 0xF5, 0x3C, 0x58, 0x33, 0x03, 0x91, 0x7E, 0x6B, 0xE9, 0xEB, 0xE0 }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) { 0x48, 0xE3, 0x1E, 0x9E, 0x25, 0x67, 0x18, 0xF2, 0x92, 0x29, 0x31, 0x9C, 0x19, 0xF1, 0x5B, 0xA4 }, { 0x05, 0x8C, 0xCF, 0xFD, 0xBB, 0xCB, 0x38, 0x2D, 0x1F, 0x6F, 0x56, 0x58, 0x5D, 0x8A, 0x4A, 0xDE } +#endif }; -static const unsigned char aes_test_ecb_enc[3][16] = +static const unsigned char aes_test_ecb_enc[][16] = { { 0xC3, 0x4C, 0x05, 0x2C, 0xC0, 0xDA, 0x8D, 0x73, 0x45, 0x1A, 0xFE, 0x5F, 0x03, 0xBE, 0x29, 0x7F }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) { 0xF3, 0xF6, 0x75, 0x2A, 0xE8, 0xD7, 0x83, 0x11, 0x38, 0xF0, 0x41, 0x56, 0x06, 0x31, 0xB1, 0x14 }, { 0x8B, 0x79, 0xEE, 0xCC, 0x93, 0xA0, 0xEE, 0x5D, 0xFF, 0x30, 0xB4, 0xEA, 0x21, 0x63, 0x6D, 0xA4 } +#endif }; #if defined(MBEDTLS_CIPHER_MODE_CBC) -static const unsigned char aes_test_cbc_dec[3][16] = +static const unsigned char aes_test_cbc_dec[][16] = { { 0xFA, 0xCA, 0x37, 0xE0, 0xB0, 0xC8, 0x53, 0x73, 0xDF, 0x70, 0x6E, 0x73, 0xF7, 0xC9, 0xAF, 0x86 }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) { 0x5D, 0xF6, 0x78, 0xDD, 0x17, 0xBA, 0x4E, 0x75, 0xB6, 0x17, 0x68, 0xC6, 0xAD, 0xEF, 0x7C, 0x7B }, { 0x48, 0x04, 0xE1, 0x81, 0x8F, 0xE6, 0x29, 0x75, 0x19, 0xA3, 0xE8, 0x8C, 0x57, 0x31, 0x04, 0x13 } +#endif }; -static const unsigned char aes_test_cbc_enc[3][16] = +static const unsigned char aes_test_cbc_enc[][16] = { { 0x8A, 0x05, 0xFC, 0x5E, 0x09, 0x5A, 0xF4, 0x84, 0x8A, 0x08, 0xD3, 0x28, 0xD3, 0x68, 0x8E, 0x3D }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) { 0x7B, 0xD9, 0x66, 0xD5, 0x3A, 0xD8, 0xC1, 0xBB, 0x85, 0xD2, 0xAD, 0xFA, 0xE8, 0x7B, 0xB1, 0x04 }, { 0xFE, 0x3C, 0x53, 0x65, 0x3E, 0x2F, 0x45, 0xB5, 0x6F, 0xCD, 0x88, 0xB2, 0xCC, 0x89, 0x8F, 0xF0 } +#endif }; #endif /* MBEDTLS_CIPHER_MODE_CBC */ @@ -1522,10 +1622,11 @@ static const unsigned char aes_test_cbc_enc[3][16] = * * http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf */ -static const unsigned char aes_test_cfb128_key[3][32] = +static const unsigned char aes_test_cfb128_key[][32] = { { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) { 0x8E, 0x73, 0xB0, 0xF7, 0xDA, 0x0E, 0x64, 0x52, 0xC8, 0x10, 0xF3, 0x2B, 0x80, 0x90, 0x79, 0xE5, 0x62, 0xF8, 0xEA, 0xD2, 0x52, 0x2C, 0x6B, 0x7B }, @@ -1533,6 +1634,7 @@ static const unsigned char aes_test_cfb128_key[3][32] = 0x2B, 0x73, 0xAE, 0xF0, 0x85, 0x7D, 0x77, 0x81, 0x1F, 0x35, 0x2C, 0x07, 0x3B, 0x61, 0x08, 0xD7, 0x2D, 0x98, 0x10, 0xA3, 0x09, 0x14, 0xDF, 0xF4 } +#endif }; static const unsigned char aes_test_cfb128_iv[16] = @@ -1553,7 +1655,7 @@ static const unsigned char aes_test_cfb128_pt[64] = 0xAD, 0x2B, 0x41, 0x7B, 0xE6, 0x6C, 0x37, 0x10 }; -static const unsigned char aes_test_cfb128_ct[3][64] = +static const unsigned char aes_test_cfb128_ct[][64] = { { 0x3B, 0x3F, 0xD9, 0x2E, 0xB7, 0x2D, 0xAD, 0x20, 0x33, 0x34, 0x49, 0xF8, 0xE8, 0x3C, 0xFB, 0x4A, @@ -1563,6 +1665,7 @@ static const unsigned char aes_test_cfb128_ct[3][64] = 0xB1, 0x80, 0x8C, 0xF1, 0x87, 0xA4, 0xF4, 0xDF, 0xC0, 0x4B, 0x05, 0x35, 0x7C, 0x5D, 0x1C, 0x0E, 0xEA, 0xC4, 0xC6, 0x6F, 0x9F, 0xF7, 0xF2, 0xE6 }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) { 0xCD, 0xC8, 0x0D, 0x6F, 0xDD, 0xF1, 0x8C, 0xAB, 0x34, 0xC2, 0x59, 0x09, 0xC9, 0x9A, 0x41, 0x74, 0x67, 0xCE, 0x7F, 0x7F, 0x81, 0x17, 0x36, 0x21, @@ -1579,6 +1682,7 @@ static const unsigned char aes_test_cfb128_ct[3][64] = 0xA1, 0x3E, 0xD0, 0xA8, 0x26, 0x7A, 0xE2, 0xF9, 0x75, 0xA3, 0x85, 0x74, 0x1A, 0xB9, 0xCE, 0xF8, 0x20, 0x31, 0x62, 0x3D, 0x55, 0xB1, 0xE4, 0x71 } +#endif }; #endif /* MBEDTLS_CIPHER_MODE_CFB */ @@ -1588,10 +1692,11 @@ static const unsigned char aes_test_cfb128_ct[3][64] = * * https://csrc.nist.gov/publications/detail/sp/800-38a/final */ -static const unsigned char aes_test_ofb_key[3][32] = +static const unsigned char aes_test_ofb_key[][32] = { { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) { 0x8E, 0x73, 0xB0, 0xF7, 0xDA, 0x0E, 0x64, 0x52, 0xC8, 0x10, 0xF3, 0x2B, 0x80, 0x90, 0x79, 0xE5, 0x62, 0xF8, 0xEA, 0xD2, 0x52, 0x2C, 0x6B, 0x7B }, @@ -1599,6 +1704,7 @@ static const unsigned char aes_test_ofb_key[3][32] = 0x2B, 0x73, 0xAE, 0xF0, 0x85, 0x7D, 0x77, 0x81, 0x1F, 0x35, 0x2C, 0x07, 0x3B, 0x61, 0x08, 0xD7, 0x2D, 0x98, 0x10, 0xA3, 0x09, 0x14, 0xDF, 0xF4 } +#endif }; static const unsigned char aes_test_ofb_iv[16] = @@ -1619,7 +1725,7 @@ static const unsigned char aes_test_ofb_pt[64] = 0xAD, 0x2B, 0x41, 0x7B, 0xE6, 0x6C, 0x37, 0x10 }; -static const unsigned char aes_test_ofb_ct[3][64] = +static const unsigned char aes_test_ofb_ct[][64] = { { 0x3B, 0x3F, 0xD9, 0x2E, 0xB7, 0x2D, 0xAD, 0x20, 0x33, 0x34, 0x49, 0xF8, 0xE8, 0x3C, 0xFB, 0x4A, @@ -1629,6 +1735,7 @@ static const unsigned char aes_test_ofb_ct[3][64] = 0x43, 0x44, 0xf7, 0xa8, 0x22, 0x60, 0xed, 0xcc, 0x30, 0x4c, 0x65, 0x28, 0xf6, 0x59, 0xc7, 0x78, 0x66, 0xa5, 0x10, 0xd9, 0xc1, 0xd6, 0xae, 0x5e }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) { 0xCD, 0xC8, 0x0D, 0x6F, 0xDD, 0xF1, 0x8C, 0xAB, 0x34, 0xC2, 0x59, 0x09, 0xC9, 0x9A, 0x41, 0x74, 0xfc, 0xc2, 0x8b, 0x8d, 0x4c, 0x63, 0x83, 0x7c, @@ -1645,6 +1752,7 @@ static const unsigned char aes_test_ofb_ct[3][64] = 0xf3, 0x9d, 0x1c, 0x5b, 0xba, 0x97, 0xc4, 0x08, 0x01, 0x26, 0x14, 0x1d, 0x67, 0xf3, 0x7b, 0xe8, 0x53, 0x8f, 0x5a, 0x8b, 0xe7, 0x40, 0xe4, 0x84 } +#endif }; #endif /* MBEDTLS_CIPHER_MODE_OFB */ @@ -1655,7 +1763,7 @@ static const unsigned char aes_test_ofb_ct[3][64] = * http://www.faqs.org/rfcs/rfc3686.html */ -static const unsigned char aes_test_ctr_key[3][16] = +static const unsigned char aes_test_ctr_key[][16] = { { 0xAE, 0x68, 0x52, 0xF8, 0x12, 0x10, 0x67, 0xCC, 0x4B, 0xF7, 0xA5, 0x76, 0x55, 0x77, 0xF3, 0x9E }, @@ -1665,7 +1773,7 @@ static const unsigned char aes_test_ctr_key[3][16] = 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC } }; -static const unsigned char aes_test_ctr_nonce_counter[3][16] = +static const unsigned char aes_test_ctr_nonce_counter[][16] = { { 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }, @@ -1675,11 +1783,10 @@ static const unsigned char aes_test_ctr_nonce_counter[3][16] = 0x4A, 0x17, 0x86, 0xF0, 0x00, 0x00, 0x00, 0x01 } }; -static const unsigned char aes_test_ctr_pt[3][48] = +static const unsigned char aes_test_ctr_pt[][48] = { { 0x53, 0x69, 0x6E, 0x67, 0x6C, 0x65, 0x20, 0x62, 0x6C, 0x6F, 0x63, 0x6B, 0x20, 0x6D, 0x73, 0x67 }, - { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, @@ -1692,7 +1799,7 @@ static const unsigned char aes_test_ctr_pt[3][48] = 0x20, 0x21, 0x22, 0x23 } }; -static const unsigned char aes_test_ctr_ct[3][48] = +static const unsigned char aes_test_ctr_ct[][48] = { { 0xE4, 0x09, 0x5D, 0x4F, 0xB7, 0xA7, 0xB3, 0x79, 0x2D, 0x61, 0x75, 0xA3, 0x26, 0x13, 0x11, 0xB8 }, @@ -1816,29 +1923,44 @@ int mbedtls_aes_self_test(int verbose) #if defined(MBEDTLS_AES_ALT) mbedtls_printf(" AES note: alternative implementation.\n"); #else /* MBEDTLS_AES_ALT */ -#if defined(MBEDTLS_PADLOCK_C) && defined(MBEDTLS_HAVE_X86) - if (mbedtls_padlock_has_support(MBEDTLS_PADLOCK_ACE)) { - mbedtls_printf(" AES note: using VIA Padlock.\n"); - } else -#endif #if defined(MBEDTLS_AESNI_HAVE_CODE) +#if MBEDTLS_AESNI_HAVE_CODE == 1 + mbedtls_printf(" AES note: AESNI code present (assembly implementation).\n"); +#elif MBEDTLS_AESNI_HAVE_CODE == 2 + mbedtls_printf(" AES note: AESNI code present (intrinsics implementation).\n"); + #else +#error "Unrecognised value for MBEDTLS_AESNI_HAVE_CODE" +#endif if (mbedtls_aesni_has_support(MBEDTLS_AESNI_AES)) { mbedtls_printf(" AES note: using AESNI.\n"); } else #endif -#if defined(MBEDTLS_AESCE_C) && defined(MBEDTLS_HAVE_ARM64) - if (mbedtls_aesce_has_support()) { +#if defined(MBEDTLS_VIA_PADLOCK_HAVE_CODE) + if (mbedtls_padlock_has_support(MBEDTLS_PADLOCK_ACE)) { + mbedtls_printf(" AES note: using VIA Padlock.\n"); + } else +#endif +#if defined(MBEDTLS_AESCE_HAVE_CODE) + if (MBEDTLS_AESCE_HAS_SUPPORT()) { mbedtls_printf(" AES note: using AESCE.\n"); } else #endif +{ +#if !defined(MBEDTLS_AES_USE_HARDWARE_ONLY) mbedtls_printf(" AES note: built-in implementation.\n"); +#endif + } #endif /* MBEDTLS_AES_ALT */ } /* * ECB mode */ - for (i = 0; i < 6; i++) { + { + static const int num_tests = + sizeof(aes_test_ecb_dec) / sizeof(*aes_test_ecb_dec); + + for (i = 0; i < num_tests << 1; i++) { u = i >> 1; keybits = 128 + u * 64; mode = i & 1; @@ -1889,13 +2011,18 @@ int mbedtls_aes_self_test(int verbose) if (verbose != 0) { mbedtls_printf("\n"); +} } #if defined(MBEDTLS_CIPHER_MODE_CBC) /* * CBC mode */ - for (i = 0; i < 6; i++) { + { + static const int num_tests = + sizeof(aes_test_cbc_dec) / sizeof(*aes_test_cbc_dec); + + for (i = 0; i < num_tests << 1; i++) { u = i >> 1; keybits = 128 + u * 64; mode = i & 1; @@ -1957,6 +2084,7 @@ int mbedtls_aes_self_test(int verbose) if (verbose != 0) { mbedtls_printf("\n"); +} } #endif /* MBEDTLS_CIPHER_MODE_CBC */ @@ -1964,7 +2092,11 @@ int mbedtls_aes_self_test(int verbose) /* * CFB128 mode */ - for (i = 0; i < 6; i++) { + { + static const int num_tests = + sizeof(aes_test_cfb128_key) / sizeof(*aes_test_cfb128_key); + + for (i = 0; i < num_tests << 1; i++) { u = i >> 1; keybits = 128 + u * 64; mode = i & 1; @@ -2016,6 +2148,7 @@ int mbedtls_aes_self_test(int verbose) if (verbose != 0) { mbedtls_printf("\n"); +} } #endif /* MBEDTLS_CIPHER_MODE_CFB */ @@ -2023,7 +2156,11 @@ int mbedtls_aes_self_test(int verbose) /* * OFB mode */ - for (i = 0; i < 6; i++) { + { + static const int num_tests = + sizeof(aes_test_ofb_key) / sizeof(*aes_test_ofb_key); + + for (i = 0; i < num_tests << 1; i++) { u = i >> 1; keybits = 128 + u * 64; mode = i & 1; @@ -2075,6 +2212,7 @@ int mbedtls_aes_self_test(int verbose) if (verbose != 0) { mbedtls_printf("\n"); +} } #endif /* MBEDTLS_CIPHER_MODE_OFB */ @@ -2082,7 +2220,11 @@ int mbedtls_aes_self_test(int verbose) /* * CTR mode */ - for (i = 0; i < 6; i++) { + { + static const int num_tests = + sizeof(aes_test_ctr_key) / sizeof(*aes_test_ctr_key); + + for (i = 0; i < num_tests << 1; i++) { u = i >> 1; mode = i & 1; @@ -2122,6 +2264,7 @@ int mbedtls_aes_self_test(int verbose) if (verbose != 0) { mbedtls_printf("passed\n"); +} } } @@ -2131,15 +2274,15 @@ int mbedtls_aes_self_test(int verbose) #endif /* MBEDTLS_CIPHER_MODE_CTR */ #if defined(MBEDTLS_CIPHER_MODE_XTS) +/* + * XTS mode + */ { static const int num_tests = sizeof(aes_test_xts_key) / sizeof(*aes_test_xts_key); mbedtls_aes_xts_context ctx_xts; - /* - * XTS mode - */ - mbedtls_aes_xts_init(&ctx_xts); + mbedtls_aes_xts_init(&ctx_xts); for (i = 0; i < num_tests << 1; i++) { const unsigned char *data_unit; diff --git a/ra/fsp/src/rm_psa_crypto/aes_alt_process.c b/ra/fsp/src/rm_psa_crypto/aes_alt_process.c index 6738da47b..1580f9dc6 100644 --- a/ra/fsp/src/rm_psa_crypto/aes_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/aes_alt_process.c @@ -175,6 +175,7 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un break; } +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) case SIZE_AES_192BIT_KEYLEN_BITS: { #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || \ @@ -239,6 +240,7 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un break; } +#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ default: @@ -441,6 +443,7 @@ int mbedtls_internal_aes_encrypt (mbedtls_aes_context * ctx, const unsigned char err = HW_SCE_Aes128EncryptDecryptFinalSub(); } +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 else if (ctx->nr == 12) { @@ -463,6 +466,8 @@ int mbedtls_internal_aes_encrypt (mbedtls_aes_context * ctx, const unsigned char err = HW_SCE_Aes256EncryptDecryptFinalSub(); } +#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ + else { return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; @@ -503,6 +508,8 @@ int mbedtls_internal_aes_encrypt_cbc (mbedtls_aes_context * ctx, HW_SCE_Aes128EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], (length / 4U)); } + +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) else if (ctx->nr == 12) { if (SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT == ctx->state) @@ -533,6 +540,8 @@ int mbedtls_internal_aes_encrypt_cbc (mbedtls_aes_context * ctx, HW_SCE_Aes256EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], (length / 4U)); } +#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ + else { return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; @@ -692,6 +701,7 @@ int mbedtls_internal_aes_decrypt (mbedtls_aes_context * ctx, const unsigned char err = HW_SCE_Aes128EncryptDecryptFinalSub(); } +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 else if (ctx->nr == 12) { @@ -714,6 +724,8 @@ int mbedtls_internal_aes_decrypt (mbedtls_aes_context * ctx, const unsigned char err = HW_SCE_Aes256EncryptDecryptFinalSub(); } +#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ + else { ret = MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; @@ -753,6 +765,8 @@ int mbedtls_internal_aes_decrypt_cbc (mbedtls_aes_context * ctx, HW_SCE_Aes128EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], (length / 4U)); } + +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) else if (ctx->nr == 12) { if (SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT == ctx->state) @@ -783,6 +797,8 @@ int mbedtls_internal_aes_decrypt_cbc (mbedtls_aes_context * ctx, HW_SCE_Aes256EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], (length / 4U)); } +#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ + else { ret = MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; @@ -934,6 +950,8 @@ int mbedtls_internal_aes_encrypt_decrypt_ctr (mbedtls_aes_context * ctx, HW_SCE_Aes128EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], (length / 4U)); } + +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) else if (ctx->nr == 12) { if (SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT == ctx->state) @@ -964,6 +982,8 @@ int mbedtls_internal_aes_encrypt_decrypt_ctr (mbedtls_aes_context * ctx, HW_SCE_Aes256EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], (length / 4U)); } +#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ + else { ret = MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; @@ -986,6 +1006,7 @@ int mbedtls_internal_aes_crypt_ctr_finish (mbedtls_aes_context * ctx) { ret = HW_SCE_Aes128EncryptDecryptFinalSub(); } +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) else if (12 == key_rounds) { ret = HW_SCE_Aes192EncryptDecryptFinalSub(); @@ -994,6 +1015,7 @@ int mbedtls_internal_aes_crypt_ctr_finish (mbedtls_aes_context * ctx) { ret = HW_SCE_Aes256EncryptDecryptFinalSub(); } +#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ else { return -1; diff --git a/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c b/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c index 9ef833079..5ef5719d1 100644 --- a/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c +++ b/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c @@ -34,7 +34,8 @@ int ecp_gen_key_vendor (mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair * key) key->grp.vendor_ctx = (bool *) true; ret = mbedtls_ecp_gen_privkey(&key->grp, &key->d, NULL, NULL); - if (!ret) + + if (!ret) { ret = mbedtls_ecp_mul(&key->grp, &key->Q, &key->d, &key->grp.G, NULL, NULL); } diff --git a/ra/fsp/src/rm_psa_crypto/ccm_alt.c b/ra/fsp/src/rm_psa_crypto/ccm_alt.c index de4caf519..84f07f486 100644 --- a/ra/fsp/src/rm_psa_crypto/ccm_alt.c +++ b/ra/fsp/src/rm_psa_crypto/ccm_alt.c @@ -33,6 +33,7 @@ #include "mbedtls/ccm.h" #include "mbedtls/platform_util.h" #include "mbedtls/error.h" +#include "mbedtls/constant_time.h" #include @@ -70,7 +71,7 @@ int mbedtls_ccm_setkey(mbedtls_ccm_context *ctx, return MBEDTLS_ERR_CCM_BAD_INPUT; } - if (cipher_info->block_size != 16) { + if (mbedtls_cipher_info_get_block_size(cipher_info) != 16) { return MBEDTLS_ERR_CCM_BAD_INPUT; } @@ -411,7 +412,6 @@ int mbedtls_ccm_update(mbedtls_ccm_context *ctx, ctx->y[i + offset] ^= local_output[i]; memcpy(output, local_output, use_len); - mbedtls_platform_zeroize(local_output, 16); if (use_len + offset == 16 || ctx->processed == ctx->plaintext_len) { if ((ret = @@ -521,13 +521,8 @@ static int mbedtls_ccm_compare_tags(const unsigned char *tag1, const unsigned char *tag2, size_t tag_len) { - unsigned char i; - int diff; - - /* Check tag in "constant-time" */ - for (diff = 0, i = 0; i < tag_len; i++) { - diff |= tag1[i] ^ tag2[i]; - } + /* Check tag in "constant-time" */ + int diff = mbedtls_ct_memcmp(tag1, tag2, tag_len); if (diff != 0) { return MBEDTLS_ERR_CCM_AUTH_FAILED; diff --git a/ra/fsp/src/rm_psa_crypto/cipher_alt.c b/ra/fsp/src/rm_psa_crypto/cipher_alt.c index a65e3e97c..12486c53c 100644 --- a/ra/fsp/src/rm_psa_crypto/cipher_alt.c +++ b/ra/fsp/src/rm_psa_crypto/cipher_alt.c @@ -1,7 +1,7 @@ /** * \file cipher_alt.c * - * \brief Generic cipher wrapper for mbed TLS + * \brief Generic cipher wrapper for Mbed TLS * * \author Adriaan de Jong * @@ -32,6 +32,7 @@ #include "mbedtls/platform_util.h" #include "mbedtls/error.h" #include "mbedtls/constant_time.h" +#include "constant_time_internal.h" #include #include @@ -56,10 +57,9 @@ #include "mbedtls/cmac.h" #endif -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) #include "psa/crypto.h" -#include "mbedtls/psa_util.h" -#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ #if defined(MBEDTLS_NIST_KW_C) #include "mbedtls/nist_kw.h" @@ -73,7 +73,7 @@ static int sce_aes_cipher_final( mbedtls_cipher_context_t *ctx ) { fsp_err_t ret = FSP_SUCCESS; - unsigned int key_bitlen = ctx->cipher_info->key_bitlen; + unsigned int key_bitlen = (ctx->cipher_info->key_bitlen) << MBEDTLS_KEY_BITLEN_SHIFT; if (128U == key_bitlen) { @@ -106,6 +106,12 @@ static int sce_aes_cipher_final( mbedtls_cipher_context_t *ctx ) static int supported_init = 0; +static inline const mbedtls_cipher_base_t *mbedtls_cipher_get_base( + const mbedtls_cipher_info_t *info) +{ + return mbedtls_cipher_base_lookup_table[info->base_idx]; +} + const int *mbedtls_cipher_list(void) { const mbedtls_cipher_definition_t *def; @@ -167,8 +173,8 @@ const mbedtls_cipher_info_t *mbedtls_cipher_info_from_values( const mbedtls_cipher_definition_t *def; for (def = mbedtls_cipher_definitions; def->info != NULL; def++) { - if (def->info->base->cipher == cipher_id && - def->info->key_bitlen == (unsigned) key_bitlen && + if (mbedtls_cipher_get_base(def->info)->cipher == cipher_id && + mbedtls_cipher_info_get_key_bitlen(def->info) == (unsigned) key_bitlen && def->info->mode == mode) { return def->info; } @@ -177,6 +183,72 @@ const mbedtls_cipher_info_t *mbedtls_cipher_info_from_values( return NULL; } +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) +static inline psa_key_type_t mbedtls_psa_translate_cipher_type( + mbedtls_cipher_type_t cipher) +{ + switch (cipher) { + case MBEDTLS_CIPHER_AES_128_CCM: + case MBEDTLS_CIPHER_AES_192_CCM: + case MBEDTLS_CIPHER_AES_256_CCM: + case MBEDTLS_CIPHER_AES_128_CCM_STAR_NO_TAG: + case MBEDTLS_CIPHER_AES_192_CCM_STAR_NO_TAG: + case MBEDTLS_CIPHER_AES_256_CCM_STAR_NO_TAG: + case MBEDTLS_CIPHER_AES_128_GCM: + case MBEDTLS_CIPHER_AES_192_GCM: + case MBEDTLS_CIPHER_AES_256_GCM: + case MBEDTLS_CIPHER_AES_128_CBC: + case MBEDTLS_CIPHER_AES_192_CBC: + case MBEDTLS_CIPHER_AES_256_CBC: + case MBEDTLS_CIPHER_AES_128_ECB: + case MBEDTLS_CIPHER_AES_192_ECB: + case MBEDTLS_CIPHER_AES_256_ECB: + return PSA_KEY_TYPE_AES; + + /* ARIA not yet supported in PSA. */ + /* case MBEDTLS_CIPHER_ARIA_128_CCM: + case MBEDTLS_CIPHER_ARIA_192_CCM: + case MBEDTLS_CIPHER_ARIA_256_CCM: + case MBEDTLS_CIPHER_ARIA_128_CCM_STAR_NO_TAG: + case MBEDTLS_CIPHER_ARIA_192_CCM_STAR_NO_TAG: + case MBEDTLS_CIPHER_ARIA_256_CCM_STAR_NO_TAG: + case MBEDTLS_CIPHER_ARIA_128_GCM: + case MBEDTLS_CIPHER_ARIA_192_GCM: + case MBEDTLS_CIPHER_ARIA_256_GCM: + case MBEDTLS_CIPHER_ARIA_128_CBC: + case MBEDTLS_CIPHER_ARIA_192_CBC: + case MBEDTLS_CIPHER_ARIA_256_CBC: + return( PSA_KEY_TYPE_ARIA ); */ + + default: + return 0; + } +} + +static inline psa_algorithm_t mbedtls_psa_translate_cipher_mode( + mbedtls_cipher_mode_t mode, size_t taglen) +{ + switch (mode) { + case MBEDTLS_MODE_ECB: + return PSA_ALG_ECB_NO_PADDING; + case MBEDTLS_MODE_GCM: + return PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, taglen); + case MBEDTLS_MODE_CCM: + return PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, taglen); + case MBEDTLS_MODE_CCM_STAR_NO_TAG: + return PSA_ALG_CCM_STAR_NO_TAG; + case MBEDTLS_MODE_CBC: + if (taglen == 0) { + return PSA_ALG_CBC_NO_PADDING; + } else { + return 0; + } + default: + return 0; + } +} +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + void mbedtls_cipher_init(mbedtls_cipher_context_t *ctx) { memset(ctx, 0, sizeof(mbedtls_cipher_context_t)); @@ -188,7 +260,7 @@ void mbedtls_cipher_free(mbedtls_cipher_context_t *ctx) return; } -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) if (ctx->psa_enabled == 1) { if (ctx->cipher_ctx != NULL) { mbedtls_cipher_context_psa * const cipher_psa = @@ -199,25 +271,23 @@ void mbedtls_cipher_free(mbedtls_cipher_context_t *ctx) (void) psa_destroy_key(cipher_psa->slot); } - mbedtls_platform_zeroize(cipher_psa, sizeof(*cipher_psa)); - mbedtls_free(cipher_psa); - } + mbedtls_zeroize_and_free(cipher_psa, sizeof(*cipher_psa)); + } mbedtls_platform_zeroize(ctx, sizeof(mbedtls_cipher_context_t)); return; } -#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ #if defined(MBEDTLS_CMAC_C) if (ctx->cmac_ctx) { - mbedtls_platform_zeroize(ctx->cmac_ctx, + mbedtls_zeroize_and_free(ctx->cmac_ctx, sizeof(mbedtls_cmac_context_t)); - mbedtls_free(ctx->cmac_ctx); - } + } #endif if (ctx->cipher_ctx) { - ctx->cipher_info->base->ctx_free_func(ctx->cipher_ctx); + mbedtls_cipher_get_base(ctx->cipher_info)->ctx_free_func(ctx->cipher_ctx); } mbedtls_platform_zeroize(ctx, sizeof(mbedtls_cipher_context_t)); @@ -232,28 +302,16 @@ int mbedtls_cipher_setup(mbedtls_cipher_context_t *ctx, memset(ctx, 0, sizeof(mbedtls_cipher_context_t)); - if (NULL == (ctx->cipher_ctx = cipher_info->base->ctx_alloc_func())) { + if (NULL == (ctx->cipher_ctx = mbedtls_cipher_get_base(cipher_info)->ctx_alloc_func())) { return MBEDTLS_ERR_CIPHER_ALLOC_FAILED; } ctx->cipher_info = cipher_info; -#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING) - /* - * Ignore possible errors caused by a cipher mode that doesn't use padding - */ -#if defined(MBEDTLS_CIPHER_PADDING_PKCS7) - (void) mbedtls_cipher_set_padding_mode(ctx, MBEDTLS_PADDING_PKCS7); -#else - (void) mbedtls_cipher_set_padding_mode(ctx, MBEDTLS_PADDING_NONE); -#endif -#endif /* MBEDTLS_CIPHER_MODE_WITH_PADDING */ - return 0; } -#if defined(MBEDTLS_USE_PSA_CRYPTO) -#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) int mbedtls_cipher_setup_psa(mbedtls_cipher_context_t *ctx, const mbedtls_cipher_info_t *cipher_info, size_t taglen) @@ -267,11 +325,11 @@ int mbedtls_cipher_setup_psa(mbedtls_cipher_context_t *ctx, /* Check that the underlying cipher mode and cipher type are * supported by the underlying PSA Crypto implementation. */ - alg = mbedtls_psa_translate_cipher_mode(cipher_info->mode, taglen); + alg = mbedtls_psa_translate_cipher_mode(((mbedtls_cipher_mode_t) cipher_info->mode), taglen); if (alg == 0) { return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; } - if (mbedtls_psa_translate_cipher_type(cipher_info->type) == 0) { + if (mbedtls_psa_translate_cipher_type(((mbedtls_cipher_type_t) cipher_info->type)) == 0) { return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; } @@ -287,8 +345,7 @@ int mbedtls_cipher_setup_psa(mbedtls_cipher_context_t *ctx, ctx->psa_enabled = 1; return 0; } -#endif /* MBEDTLS_DEPRECATED_REMOVED */ -#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ int mbedtls_cipher_setkey(mbedtls_cipher_context_t *ctx, const unsigned char *key, @@ -302,7 +359,7 @@ int mbedtls_cipher_setkey(mbedtls_cipher_context_t *ctx, return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) if (ctx->psa_enabled == 1) { mbedtls_cipher_context_psa * const cipher_psa = (mbedtls_cipher_context_psa *) ctx->cipher_ctx; @@ -324,7 +381,7 @@ int mbedtls_cipher_setkey(mbedtls_cipher_context_t *ctx, } key_type = mbedtls_psa_translate_cipher_type( - ctx->cipher_info->type); + ((mbedtls_cipher_type_t) ctx->cipher_info->type)); if (key_type == 0) { return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; } @@ -335,7 +392,6 @@ int mbedtls_cipher_setkey(mbedtls_cipher_context_t *ctx, * and use it for AEAD decryption. Until tests relying on this * are changed, allow any usage in PSA. */ psa_set_key_usage_flags(&attributes, - /* mbedtls_psa_translate_cipher_operation( operation ); */ PSA_KEY_USAGE_ENCRYPT | PSA_KEY_USAGE_DECRYPT); psa_set_key_algorithm(&attributes, cipher_psa->alg); @@ -359,10 +415,10 @@ int mbedtls_cipher_setkey(mbedtls_cipher_context_t *ctx, ctx->operation = operation; return 0; } -#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ if ((ctx->cipher_info->flags & MBEDTLS_CIPHER_VARIABLE_KEY_LEN) == 0 && - (int) ctx->cipher_info->key_bitlen != key_bitlen) { + (int) mbedtls_cipher_info_get_key_bitlen(ctx->cipher_info) != key_bitlen) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } @@ -373,15 +429,15 @@ int mbedtls_cipher_setkey(mbedtls_cipher_context_t *ctx, * For OFB, CFB and CTR mode always use the encryption key schedule */ if (MBEDTLS_ENCRYPT == operation || - MBEDTLS_MODE_CFB == ctx->cipher_info->mode || - MBEDTLS_MODE_OFB == ctx->cipher_info->mode || - MBEDTLS_MODE_CTR == ctx->cipher_info->mode) { - return ctx->cipher_info->base->setkey_enc_func(ctx->cipher_ctx, key, + MBEDTLS_MODE_CFB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_OFB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_CTR == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + return mbedtls_cipher_get_base(ctx->cipher_info)->setkey_enc_func(ctx->cipher_ctx, key, ctx->key_bitlen); } if (MBEDTLS_DECRYPT == operation) { - return ctx->cipher_info->base->setkey_dec_func(ctx->cipher_ctx, key, + return mbedtls_cipher_get_base(ctx->cipher_info)->setkey_dec_func(ctx->cipher_ctx, key, ctx->key_bitlen); } @@ -397,14 +453,14 @@ int mbedtls_cipher_set_iv(mbedtls_cipher_context_t *ctx, if (ctx->cipher_info == NULL) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) if (ctx->psa_enabled == 1) { /* While PSA Crypto has an API for multipart * operations, we currently don't make it * accessible through the cipher layer. */ return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; } -#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ /* avoid buffer overflow in ctx->iv */ if (iv_len > MBEDTLS_MAX_IV_LENGTH) { @@ -414,7 +470,7 @@ int mbedtls_cipher_set_iv(mbedtls_cipher_context_t *ctx, if ((ctx->cipher_info->flags & MBEDTLS_CIPHER_VARIABLE_IV_LEN) != 0) { actual_iv_size = iv_len; } else { - actual_iv_size = ctx->cipher_info->iv_size; + actual_iv_size = mbedtls_cipher_info_get_iv_size(ctx->cipher_info); /* avoid reading past the end of input buffer */ if (actual_iv_size > iv_len) { @@ -423,7 +479,7 @@ int mbedtls_cipher_set_iv(mbedtls_cipher_context_t *ctx, } #if defined(MBEDTLS_CHACHA20_C) - if (ctx->cipher_info->type == MBEDTLS_CIPHER_CHACHA20) { + if (((mbedtls_cipher_type_t) ctx->cipher_info->type) == MBEDTLS_CIPHER_CHACHA20) { /* Even though the actual_iv_size is overwritten with a correct value * of 12 from the cipher info, return an error to indicate that * the input iv_len is wrong. */ @@ -438,7 +494,7 @@ int mbedtls_cipher_set_iv(mbedtls_cipher_context_t *ctx, } } #if defined(MBEDTLS_CHACHAPOLY_C) - if (ctx->cipher_info->type == MBEDTLS_CIPHER_CHACHA20_POLY1305 && + if (((mbedtls_cipher_type_t) ctx->cipher_info->type) == MBEDTLS_CIPHER_CHACHA20_POLY1305 && iv_len != 12) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } @@ -446,7 +502,7 @@ int mbedtls_cipher_set_iv(mbedtls_cipher_context_t *ctx, #endif #if defined(MBEDTLS_GCM_C) - if (MBEDTLS_MODE_GCM == ctx->cipher_info->mode) { + if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { return mbedtls_gcm_starts((mbedtls_gcm_context *) ctx->cipher_ctx, ctx->operation, iv, iv_len); @@ -454,7 +510,7 @@ int mbedtls_cipher_set_iv(mbedtls_cipher_context_t *ctx, #endif #if defined(MBEDTLS_CCM_C) - if (MBEDTLS_MODE_CCM_STAR_NO_TAG == ctx->cipher_info->mode) { + if (MBEDTLS_MODE_CCM_STAR_NO_TAG == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { int set_lengths_result; int ccm_star_mode; @@ -493,13 +549,13 @@ int mbedtls_cipher_reset(mbedtls_cipher_context_t *ctx) return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) if (ctx->psa_enabled == 1) { /* We don't support resetting PSA-based * cipher contexts, yet. */ return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; } -#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ ctx->unprocessed_len = 0; @@ -514,24 +570,24 @@ int mbedtls_cipher_update_ad(mbedtls_cipher_context_t *ctx, return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) if (ctx->psa_enabled == 1) { /* While PSA Crypto has an API for multipart * operations, we currently don't make it * accessible through the cipher layer. */ return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; } -#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ #if defined(MBEDTLS_GCM_C) - if (MBEDTLS_MODE_GCM == ctx->cipher_info->mode) { + if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { return mbedtls_gcm_update_ad((mbedtls_gcm_context *) ctx->cipher_ctx, ad, ad_len); } #endif #if defined(MBEDTLS_CHACHAPOLY_C) - if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ctx->cipher_info->type) { + if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) { int result; mbedtls_chachapoly_mode_t mode; @@ -565,14 +621,14 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) if (ctx->psa_enabled == 1) { /* While PSA Crypto has an API for multipart * operations, we currently don't make it * accessible through the cipher layer. */ return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; } -#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ *olen = 0; block_size = mbedtls_cipher_get_block_size(ctx); @@ -580,15 +636,16 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in return MBEDTLS_ERR_CIPHER_INVALID_CONTEXT; } - if (ctx->cipher_info->mode == MBEDTLS_MODE_ECB) { + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_ECB) { if (ilen != block_size) { return MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED; } *olen = ilen; - if (0 != (ret = ctx->cipher_info->base->ecb_func(ctx->cipher_ctx, - ctx->operation, input, output))) { + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->ecb_func(ctx->cipher_ctx, + ctx->operation, input, + output))) { return ret; } @@ -596,7 +653,7 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in } #if defined(MBEDTLS_GCM_C) - if (ctx->cipher_info->mode == MBEDTLS_MODE_GCM) { + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_GCM) { return mbedtls_gcm_update((mbedtls_gcm_context *) ctx->cipher_ctx, input, ilen, output, ilen, olen); @@ -604,7 +661,7 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in #endif #if defined(MBEDTLS_CCM_C) - if (ctx->cipher_info->mode == MBEDTLS_MODE_CCM_STAR_NO_TAG) { + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_CCM_STAR_NO_TAG) { return mbedtls_ccm_update((mbedtls_ccm_context *) ctx->cipher_ctx, input, ilen, output, ilen, olen); @@ -612,7 +669,7 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in #endif #if defined(MBEDTLS_CHACHAPOLY_C) - if (ctx->cipher_info->type == MBEDTLS_CIPHER_CHACHA20_POLY1305) { + if (((mbedtls_cipher_type_t) ctx->cipher_info->type) == MBEDTLS_CIPHER_CHACHA20_POLY1305) { *olen = ilen; return mbedtls_chachapoly_update((mbedtls_chachapoly_context *) ctx->cipher_ctx, ilen, input, output); @@ -625,7 +682,7 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in } #if defined(MBEDTLS_CIPHER_MODE_CBC) - if (ctx->cipher_info->mode == MBEDTLS_MODE_CBC) { + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_CBC) { size_t copy_len = 0; /* @@ -653,9 +710,12 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in memcpy(&(ctx->unprocessed_data[ctx->unprocessed_len]), input, copy_len); - if (0 != (ret = ctx->cipher_info->base->cbc_func(ctx->cipher_ctx, - ctx->operation, block_size, ctx->iv, - ctx->unprocessed_data, output))) { + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->cbc_func(ctx->cipher_ctx, + ctx->operation, + block_size, ctx->iv, + ctx-> + unprocessed_data, + output))) { return ret; } @@ -693,8 +753,10 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in * Process remaining full blocks */ if (ilen) { - if (0 != (ret = ctx->cipher_info->base->cbc_func(ctx->cipher_ctx, - ctx->operation, ilen, ctx->iv, input, + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->cbc_func(ctx->cipher_ctx, + ctx->operation, + ilen, ctx->iv, + input, output))) { return ret; } @@ -707,10 +769,11 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in #endif /* MBEDTLS_CIPHER_MODE_CBC */ #if defined(MBEDTLS_CIPHER_MODE_CFB) - if (ctx->cipher_info->mode == MBEDTLS_MODE_CFB) { - if (0 != (ret = ctx->cipher_info->base->cfb_func(ctx->cipher_ctx, + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_CFB) { + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->cfb_func(ctx->cipher_ctx, ctx->operation, ilen, - &ctx->unprocessed_len, ctx->iv, + &ctx->unprocessed_len, + ctx->iv, input, output))) { return ret; } @@ -722,9 +785,11 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in #endif /* MBEDTLS_CIPHER_MODE_CFB */ #if defined(MBEDTLS_CIPHER_MODE_OFB) - if (ctx->cipher_info->mode == MBEDTLS_MODE_OFB) { - if (0 != (ret = ctx->cipher_info->base->ofb_func(ctx->cipher_ctx, - ilen, &ctx->unprocessed_len, ctx->iv, + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_OFB) { + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->ofb_func(ctx->cipher_ctx, + ilen, + &ctx->unprocessed_len, + ctx->iv, input, output))) { return ret; } @@ -736,7 +801,7 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in #endif /* MBEDTLS_CIPHER_MODE_OFB */ #if defined(MBEDTLS_CIPHER_MODE_CTR) - if (ctx->cipher_info->mode == MBEDTLS_MODE_CTR) { + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_CTR) { size_t copy_len = 0; /* @@ -761,9 +826,10 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in memcpy( &( ctx->unprocessed_data[ctx->unprocessed_len] ), input, copy_len ); - if (0 != (ret = ctx->cipher_info->base->ctr_func(ctx->cipher_ctx, - block_size, NULL, ctx->iv, - NULL, ctx->unprocessed_data, output))) { + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->ctr_func(ctx->cipher_ctx, + block_size, + NULL, ctx->iv, + NULL, ctx->unprocessed_data, output))) { return ret; } @@ -793,8 +859,10 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in */ if( ilen ) { - if( 0 != ( ret = ctx->cipher_info->base->ctr_func( ctx->cipher_ctx, - ilen, NULL, ctx->iv, NULL, input, output ) ) ) + if( 0 != ( ret =mbedtls_cipher_get_base(ctx->cipher_info)->ctr_func(ctx->cipher_ctx, + ilen, NULL, + ctx->iv, NULL, + input, output))) { return( ret ); } @@ -807,14 +875,18 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in #endif /* MBEDTLS_CIPHER_MODE_CTR */ #if defined(MBEDTLS_CIPHER_MODE_XTS) - if (ctx->cipher_info->mode == MBEDTLS_MODE_XTS) { + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_XTS) { if (ctx->unprocessed_len > 0) { /* We can only process an entire data unit at a time. */ return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; } - ret = ctx->cipher_info->base->xts_func(ctx->cipher_ctx, - ctx->operation, ilen, ctx->iv, input, output); + ret = mbedtls_cipher_get_base(ctx->cipher_info)->xts_func(ctx->cipher_ctx, + ctx->operation, + ilen, + ctx->iv, + input, + output); if (ret != 0) { return ret; } @@ -826,9 +898,10 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in #endif /* MBEDTLS_CIPHER_MODE_XTS */ #if defined(MBEDTLS_CIPHER_MODE_STREAM) - if (ctx->cipher_info->mode == MBEDTLS_MODE_STREAM) { - if (0 != (ret = ctx->cipher_info->base->stream_func(ctx->cipher_ctx, - ilen, input, output))) { + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_STREAM) { + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->stream_func(ctx->cipher_ctx, + ilen, input, + output))) { return ret; } @@ -861,7 +934,7 @@ static int get_pkcs_padding(unsigned char *input, size_t input_len, size_t *data_len) { size_t i, pad_idx; - unsigned char padding_len, bad = 0; + unsigned char padding_len; if (NULL == input || NULL == data_len) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; @@ -870,18 +943,19 @@ static int get_pkcs_padding(unsigned char *input, size_t input_len, padding_len = input[input_len - 1]; *data_len = input_len - padding_len; - /* Avoid logical || since it results in a branch */ - bad |= padding_len > input_len; - bad |= padding_len == 0; + mbedtls_ct_condition_t bad = mbedtls_ct_uint_gt(padding_len, input_len); + bad = mbedtls_ct_bool_or(bad, mbedtls_ct_uint_eq(padding_len, 0)); /* The number of bytes checked must be independent of padding_len, * so pick input_len, which is usually 8 or 16 (one block) */ pad_idx = input_len - padding_len; for (i = 0; i < input_len; i++) { - bad |= (input[i] ^ padding_len) * (i >= pad_idx); + mbedtls_ct_condition_t in_padding = mbedtls_ct_uint_ge(i, pad_idx); + mbedtls_ct_condition_t different = mbedtls_ct_uint_ne(input[i], padding_len); + bad = mbedtls_ct_bool_or(bad, mbedtls_ct_bool_and(in_padding, different)); } - return MBEDTLS_ERR_CIPHER_INVALID_PADDING * (bad != 0); + return mbedtls_ct_error_if_else_0(bad, MBEDTLS_ERR_CIPHER_INVALID_PADDING); } #endif /* MBEDTLS_CIPHER_PADDING_PKCS7 */ @@ -904,24 +978,28 @@ static void add_one_and_zeros_padding(unsigned char *output, static int get_one_and_zeros_padding(unsigned char *input, size_t input_len, size_t *data_len) { - size_t i; - unsigned char done = 0, prev_done, bad; - - if (NULL == input || NULL == data_len) { + if (NULL == input || NULL == data_len) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } - bad = 0x80; + mbedtls_ct_condition_t in_padding = MBEDTLS_CT_TRUE; + mbedtls_ct_condition_t bad = MBEDTLS_CT_TRUE; + *data_len = 0; - for (i = input_len; i > 0; i--) { - prev_done = done; - done |= (input[i - 1] != 0); - *data_len |= (i - 1) * (done != prev_done); - bad ^= input[i - 1] * (done != prev_done); - } + + for (ptrdiff_t i = (ptrdiff_t) (input_len) - 1; i >= 0; i--) { + mbedtls_ct_condition_t is_nonzero = mbedtls_ct_bool(input[i]); + + mbedtls_ct_condition_t hit_first_nonzero = mbedtls_ct_bool_and(is_nonzero, in_padding); - return MBEDTLS_ERR_CIPHER_INVALID_PADDING * (bad != 0); + *data_len = mbedtls_ct_size_if(hit_first_nonzero, i, *data_len); + bad = mbedtls_ct_bool_if(hit_first_nonzero, mbedtls_ct_uint_ne(input[i], 0x80), bad); + + in_padding = mbedtls_ct_bool_and(in_padding, mbedtls_ct_bool_not(is_nonzero)); + } + + return mbedtls_ct_error_if_else_0(bad, MBEDTLS_ERR_CIPHER_INVALID_PADDING); } #endif /* MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS */ @@ -945,7 +1023,8 @@ static int get_zeros_and_len_padding(unsigned char *input, size_t input_len, size_t *data_len) { size_t i, pad_idx; - unsigned char padding_len, bad = 0; + unsigned char padding_len; + mbedtls_ct_condition_t bad; if (NULL == input || NULL == data_len) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; @@ -955,16 +1034,19 @@ static int get_zeros_and_len_padding(unsigned char *input, size_t input_len, *data_len = input_len - padding_len; /* Avoid logical || since it results in a branch */ - bad |= padding_len > input_len; - bad |= padding_len == 0; + bad = mbedtls_ct_uint_gt(padding_len, input_len); + bad = mbedtls_ct_bool_or(bad, mbedtls_ct_uint_eq(padding_len, 0)); /* The number of bytes checked must be independent of padding_len */ pad_idx = input_len - padding_len; for (i = 0; i < input_len - 1; i++) { - bad |= input[i] * (i >= pad_idx); + mbedtls_ct_condition_t is_padding = mbedtls_ct_uint_ge(i, pad_idx); +mbedtls_ct_condition_t nonzero_pad_byte; + nonzero_pad_byte = mbedtls_ct_bool_if_else_0(is_padding, mbedtls_ct_bool(input[i])); + bad = mbedtls_ct_bool_or(bad, nonzero_pad_byte); } - return MBEDTLS_ERR_CIPHER_INVALID_PADDING * (bad != 0); + return mbedtls_ct_error_if_else_0(bad, MBEDTLS_ERR_CIPHER_INVALID_PADDING); } #endif /* MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN */ @@ -975,18 +1057,14 @@ static int get_zeros_and_len_padding(unsigned char *input, size_t input_len, static void add_zeros_padding(unsigned char *output, size_t output_len, size_t data_len) { - size_t i; - - for (i = data_len; i < output_len; i++) { - output[i] = 0x00; - } + memset(output + data_len, 0, output_len - data_len); } static int get_zeros_padding(unsigned char *input, size_t input_len, size_t *data_len) { size_t i; - unsigned char done = 0, prev_done; + mbedtls_ct_condition_t done = MBEDTLS_CT_FALSE, prev_done; if (NULL == input || NULL == data_len) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; @@ -995,8 +1073,8 @@ static int get_zeros_padding(unsigned char *input, size_t input_len, *data_len = 0; for (i = input_len; i > 0; i--) { prev_done = done; - done |= (input[i-1] != 0); - *data_len |= i * (done != prev_done); + done = mbedtls_ct_bool_or(done, mbedtls_ct_uint_ne(input[i-1], 0)); + *data_len = mbedtls_ct_size_if(mbedtls_ct_bool_ne(done, prev_done), i, *data_len); } return 0; @@ -1029,32 +1107,42 @@ int mbedtls_cipher_finish(mbedtls_cipher_context_t *ctx, return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) if (ctx->psa_enabled == 1) { /* While PSA Crypto has an API for multipart * operations, we currently don't make it * accessible through the cipher layer. */ return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; } -#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ *olen = 0; - if (MBEDTLS_MODE_CFB == ctx->cipher_info->mode || - MBEDTLS_MODE_OFB == ctx->cipher_info->mode || - MBEDTLS_MODE_GCM == ctx->cipher_info->mode || - MBEDTLS_MODE_CCM_STAR_NO_TAG == ctx->cipher_info->mode || - MBEDTLS_MODE_XTS == ctx->cipher_info->mode || - MBEDTLS_MODE_STREAM == ctx->cipher_info->mode) { +#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING) + /* CBC mode requires padding so we make sure a call to + * mbedtls_cipher_set_padding_mode has been done successfully. */ + if (MBEDTLS_MODE_CBC == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + if (ctx->get_padding == NULL) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + } +#endif + + if (MBEDTLS_MODE_CFB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_OFB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_CCM_STAR_NO_TAG == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_XTS == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_STREAM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { return 0; } - if ((MBEDTLS_CIPHER_CHACHA20 == ctx->cipher_info->type) || - (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ctx->cipher_info->type)) { + if ((MBEDTLS_CIPHER_CHACHA20 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) || + (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type))) { return 0; } - if (MBEDTLS_MODE_ECB == ctx->cipher_info->mode) { + if (MBEDTLS_MODE_ECB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { if (ctx->unprocessed_len != 0) { return MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED; } @@ -1063,7 +1151,7 @@ int mbedtls_cipher_finish(mbedtls_cipher_context_t *ctx, } #if defined(MBEDTLS_CIPHER_MODE_CBC) - if (MBEDTLS_MODE_CBC == ctx->cipher_info->mode) { + if (MBEDTLS_MODE_CBC == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { int ret = 0; if (MBEDTLS_ENCRYPT == ctx->operation) { @@ -1099,11 +1187,13 @@ int mbedtls_cipher_finish(mbedtls_cipher_context_t *ctx, } /* cipher block */ - if (0 != (ret = ctx->cipher_info->base->cbc_func(ctx->cipher_ctx, + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->cbc_func(ctx->cipher_ctx, ctx->operation, - mbedtls_cipher_get_block_size(ctx), + mbedtls_cipher_get_block_size( + ctx), ctx->iv, - ctx->unprocessed_data, output))) { + ctx->unprocessed_data, + output))) { return ret; } @@ -1144,7 +1234,7 @@ int mbedtls_cipher_finish(mbedtls_cipher_context_t *ctx, (block_size - ctx->unprocessed_len) ); /* cipher block */ - if( 0 != ( ret = ctx->cipher_info->base->ctr_func( ctx->cipher_ctx, block_size, + if( 0 != ( ret = mbedtls_cipher_get_base(ctx->cipher_info)->ctr_func( ctx->cipher_ctx, block_size, NULL, ctx->iv, NULL, ctx->unprocessed_data, tmp ) ) ) { @@ -1172,11 +1262,12 @@ int mbedtls_cipher_finish(mbedtls_cipher_context_t *ctx, int mbedtls_cipher_set_padding_mode(mbedtls_cipher_context_t *ctx, mbedtls_cipher_padding_t mode) { - if (NULL == ctx->cipher_info || MBEDTLS_MODE_CBC != ctx->cipher_info->mode) { + if (NULL == ctx->cipher_info || + MBEDTLS_MODE_CBC != ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) if (ctx->psa_enabled == 1) { /* While PSA Crypto knows about CBC padding * schemes, we currently don't make them @@ -1187,7 +1278,7 @@ int mbedtls_cipher_set_padding_mode(mbedtls_cipher_context_t *ctx, return 0; } -#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ switch (mode) { #if defined(MBEDTLS_CIPHER_PADDING_PKCS7) @@ -1239,17 +1330,17 @@ int mbedtls_cipher_write_tag(mbedtls_cipher_context_t *ctx, return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) if (ctx->psa_enabled == 1) { /* While PSA Crypto has an API for multipart * operations, we currently don't make it * accessible through the cipher layer. */ return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; } -#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ #if defined(MBEDTLS_GCM_C) - if (MBEDTLS_MODE_GCM == ctx->cipher_info->mode) { + if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { size_t output_length; /* The code here doesn't yet support alternative implementations * that can delay up to a block of output. */ @@ -1260,7 +1351,7 @@ int mbedtls_cipher_write_tag(mbedtls_cipher_context_t *ctx, #endif #if defined(MBEDTLS_CHACHAPOLY_C) - if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ctx->cipher_info->type) { + if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) { /* Don't allow truncated MAC for Poly1305 */ if (tag_len != 16U) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; @@ -1288,20 +1379,20 @@ int mbedtls_cipher_check_tag(mbedtls_cipher_context_t *ctx, return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) if (ctx->psa_enabled == 1) { /* While PSA Crypto has an API for multipart * operations, we currently don't make it * accessible through the cipher layer. */ return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; } -#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ /* Status to return on a non-authenticated algorithm. */ ret = MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; #if defined(MBEDTLS_GCM_C) - if (MBEDTLS_MODE_GCM == ctx->cipher_info->mode) { + if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { size_t output_length; /* The code here doesn't yet support alternative implementations * that can delay up to a block of output. */ @@ -1326,7 +1417,7 @@ int mbedtls_cipher_check_tag(mbedtls_cipher_context_t *ctx, #endif /* MBEDTLS_GCM_C */ #if defined(MBEDTLS_CHACHAPOLY_C) - if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ctx->cipher_info->type) { + if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) { /* Don't allow truncated MAC for Poly1305 */ if (tag_len != sizeof(check_tag)) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; @@ -1363,7 +1454,7 @@ int mbedtls_cipher_crypt(mbedtls_cipher_context_t *ctx, int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t finish_olen; -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) if (ctx->psa_enabled == 1) { /* As in the non-PSA case, we don't check that * a key has been set. If not, the key slot will @@ -1397,7 +1488,7 @@ int mbedtls_cipher_crypt(mbedtls_cipher_context_t *ctx, return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; } - if (ctx->cipher_info->mode != MBEDTLS_MODE_ECB) { + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) != MBEDTLS_MODE_ECB) { status = psa_cipher_set_iv(&cipher_op, iv, iv_len); if (status != PSA_SUCCESS) { return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; @@ -1421,7 +1512,7 @@ int mbedtls_cipher_crypt(mbedtls_cipher_context_t *ctx, *olen += part_len; return 0; } -#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ if ((ret = mbedtls_cipher_set_iv(ctx, iv, iv_len)) != 0) { return ret; @@ -1458,7 +1549,7 @@ static int mbedtls_cipher_aead_encrypt(mbedtls_cipher_context_t *ctx, unsigned char *output, size_t *olen, unsigned char *tag, size_t tag_len) { -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) if (ctx->psa_enabled == 1) { /* As in the non-PSA case, we don't check that * a key has been set. If not, the key slot will @@ -1489,10 +1580,10 @@ static int mbedtls_cipher_aead_encrypt(mbedtls_cipher_context_t *ctx, *olen -= tag_len; return 0; } -#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ #if defined(MBEDTLS_GCM_C) - if (MBEDTLS_MODE_GCM == ctx->cipher_info->mode) { + if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { *olen = ilen; return mbedtls_gcm_crypt_and_tag(ctx->cipher_ctx, MBEDTLS_GCM_ENCRYPT, ilen, iv, iv_len, ad, ad_len, @@ -1500,7 +1591,7 @@ static int mbedtls_cipher_aead_encrypt(mbedtls_cipher_context_t *ctx, } #endif /* MBEDTLS_GCM_C */ #if defined(MBEDTLS_CCM_C) - if (MBEDTLS_MODE_CCM == ctx->cipher_info->mode) { + if (MBEDTLS_MODE_CCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { *olen = ilen; return mbedtls_ccm_encrypt_and_tag(ctx->cipher_ctx, ilen, iv, iv_len, ad, ad_len, input, output, @@ -1508,9 +1599,9 @@ static int mbedtls_cipher_aead_encrypt(mbedtls_cipher_context_t *ctx, } #endif /* MBEDTLS_CCM_C */ #if defined(MBEDTLS_CHACHAPOLY_C) - if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ctx->cipher_info->type) { + if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) { /* ChachaPoly has fixed length nonce and MAC (tag) */ - if ((iv_len != ctx->cipher_info->iv_size) || + if ((iv_len != mbedtls_cipher_info_get_iv_size(ctx->cipher_info)) || (tag_len != 16U)) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } @@ -1535,7 +1626,7 @@ static int mbedtls_cipher_aead_decrypt(mbedtls_cipher_context_t *ctx, unsigned char *output, size_t *olen, const unsigned char *tag, size_t tag_len) { -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) if (ctx->psa_enabled == 1) { /* As in the non-PSA case, we don't check that * a key has been set. If not, the key slot will @@ -1567,10 +1658,10 @@ static int mbedtls_cipher_aead_decrypt(mbedtls_cipher_context_t *ctx, return 0; } -#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ #if defined(MBEDTLS_GCM_C) - if (MBEDTLS_MODE_GCM == ctx->cipher_info->mode) { + if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; *olen = ilen; @@ -1586,7 +1677,7 @@ static int mbedtls_cipher_aead_decrypt(mbedtls_cipher_context_t *ctx, } #endif /* MBEDTLS_GCM_C */ #if defined(MBEDTLS_CCM_C) - if (MBEDTLS_MODE_CCM == ctx->cipher_info->mode) { + if (MBEDTLS_MODE_CCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; *olen = ilen; @@ -1602,11 +1693,11 @@ static int mbedtls_cipher_aead_decrypt(mbedtls_cipher_context_t *ctx, } #endif /* MBEDTLS_CCM_C */ #if defined(MBEDTLS_CHACHAPOLY_C) - if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ctx->cipher_info->type) { + if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* ChachaPoly has fixed length nonce and MAC (tag) */ - if ((iv_len != ctx->cipher_info->iv_size) || + if ((iv_len != mbedtls_cipher_info_get_iv_size(ctx->cipher_info)) || (tag_len != 16U)) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } @@ -1640,12 +1731,13 @@ int mbedtls_cipher_auth_encrypt_ext(mbedtls_cipher_context_t *ctx, { #if defined(MBEDTLS_NIST_KW_C) if ( -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) ctx->psa_enabled == 0 && #endif - (MBEDTLS_MODE_KW == ctx->cipher_info->mode || - MBEDTLS_MODE_KWP == ctx->cipher_info->mode)) { - mbedtls_nist_kw_mode_t mode = (MBEDTLS_MODE_KW == ctx->cipher_info->mode) ? + (MBEDTLS_MODE_KW == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_KWP == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode))) { + mbedtls_nist_kw_mode_t mode = + (MBEDTLS_MODE_KW == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) ? MBEDTLS_KW_MODE_KW : MBEDTLS_KW_MODE_KWP; /* There is no iv, tag or ad associated with KW and KWP, @@ -1690,12 +1782,13 @@ int mbedtls_cipher_auth_decrypt_ext(mbedtls_cipher_context_t *ctx, { #if defined(MBEDTLS_NIST_KW_C) if ( -#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) ctx->psa_enabled == 0 && #endif - (MBEDTLS_MODE_KW == ctx->cipher_info->mode || - MBEDTLS_MODE_KWP == ctx->cipher_info->mode)) { - mbedtls_nist_kw_mode_t mode = (MBEDTLS_MODE_KW == ctx->cipher_info->mode) ? + (MBEDTLS_MODE_KW == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_KWP == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode))) { + mbedtls_nist_kw_mode_t mode = + (MBEDTLS_MODE_KW == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) ? MBEDTLS_KW_MODE_KW : MBEDTLS_KW_MODE_KWP; /* There is no iv, tag or ad associated with KW and KWP, diff --git a/ra/fsp/src/rm_psa_crypto/cmac_alt.c b/ra/fsp/src/rm_psa_crypto/cmac_alt.c index 51da582a3..5d9a35ded 100644 --- a/ra/fsp/src/rm_psa_crypto/cmac_alt.c +++ b/ra/fsp/src/rm_psa_crypto/cmac_alt.c @@ -115,12 +115,12 @@ static int cmac_generate_subkeys(mbedtls_cipher_context_t *ctx, unsigned char *K1, unsigned char *K2) { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - unsigned char L[MBEDTLS_CIPHER_BLKSIZE_MAX]; + unsigned char L[MBEDTLS_CMAC_MAX_BLOCK_SIZE]; size_t olen, block_size; mbedtls_platform_zeroize(L, sizeof(L)); - block_size = ctx->cipher_info->block_size; + block_size = mbedtls_cipher_info_get_block_size(ctx->cipher_info); /* Calculate Ek(0) */ if ((ret = mbedtls_cipher_update(ctx, L, block_size, L, &olen)) != 0) { @@ -153,7 +153,7 @@ static int cmac_generate_subkeys(mbedtls_cipher_context_t *ctx, * We can't use the padding option from the cipher layer, as it only works for * CBC and we use ECB mode, and anyway we need to XOR K1 or K2 in addition. */ -static void cmac_pad(unsigned char padded_block[MBEDTLS_CIPHER_BLKSIZE_MAX], +static void cmac_pad(unsigned char padded_block[MBEDTLS_CMAC_MAX_BLOCK_SIZE], size_t padded_block_len, const unsigned char *last_block, size_t last_block_len) @@ -230,7 +230,7 @@ int mbedtls_cipher_cmac_starts(mbedtls_cipher_context_t *ctx, return retval; } - type = ctx->cipher_info->type; + type = mbedtls_cipher_info_get_type(ctx->cipher_info); switch (type) { case MBEDTLS_CIPHER_AES_128_ECB: @@ -268,7 +268,7 @@ int mbedtls_cipher_cmac_update(mbedtls_cipher_context_t *ctx, int ret = 0; size_t block_size; uint32_t length_rest = 0; - mbedtls_cipher_type_t type = ctx->cipher_info->type; + mbedtls_cipher_type_t type = mbedtls_cipher_info_get_type(ctx->cipher_info); if (ctx == NULL || ctx->cipher_info == NULL || input == NULL || ctx->cmac_ctx == NULL) { @@ -276,7 +276,7 @@ int mbedtls_cipher_cmac_update(mbedtls_cipher_context_t *ctx, } cmac_ctx = ctx->cmac_ctx; - block_size = ctx->cipher_info->block_size; + block_size = mbedtls_cipher_info_get_block_size(ctx->cipher_info); if (SCE_MBEDTLS_CMAC_OPERATION_STATE_INIT == cmac_ctx->vendor_state) { @@ -318,7 +318,7 @@ int mbedtls_cipher_cmac_finish(mbedtls_cipher_context_t *ctx, mbedtls_cmac_context_t *cmac_ctx; int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t block_size; - mbedtls_cipher_type_t type = ctx->cipher_info->type; + mbedtls_cipher_type_t type = mbedtls_cipher_info_get_type(ctx->cipher_info); if (ctx == NULL || ctx->cipher_info == NULL || ctx->cmac_ctx == NULL || output == NULL) { @@ -326,7 +326,7 @@ int mbedtls_cipher_cmac_finish(mbedtls_cipher_context_t *ctx, } cmac_ctx = ctx->cmac_ctx; - block_size = ctx->cipher_info->block_size; + block_size = mbedtls_cipher_info_get_block_size(ctx->cipher_info); if (SCE_MBEDTLS_CMAC_OPERATION_STATE_INIT == cmac_ctx->vendor_state) { @@ -570,6 +570,7 @@ static const unsigned char aes_128_expected_result[NB_CMAC_TESTS_PER_KEY][MBEDTL }; /* CMAC-AES192 Test Data */ +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) static const unsigned char aes_192_key[24] = { 0x8e, 0x73, 0xb0, 0xf7, 0xda, 0x0e, 0x64, 0x52, 0xc8, 0x10, 0xf3, 0x2b, 0x80, 0x90, 0x79, 0xe5, @@ -610,8 +611,10 @@ static const unsigned char aes_192_expected_result[NB_CMAC_TESTS_PER_KEY][MBEDTL 0x4d, 0x77, 0x58, 0x96, 0x59, 0xf3, 0x9a, 0x11 } }; +#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ /* CMAC-AES256 Test Data */ +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) static const unsigned char aes_256_key[32] = { 0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe, 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81, @@ -653,6 +656,7 @@ static const unsigned char aes_256_expected_result[NB_CMAC_TESTS_PER_KEY][MBEDTL 0x69, 0x6a, 0x2c, 0x05, 0x6c, 0x31, 0x54, 0x10 } }; +#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ #endif /* MBEDTLS_AES_C */ #if defined(MBEDTLS_DES_C) @@ -795,8 +799,8 @@ static int cmac_test_subkeys(int verbose, int i, ret = 0; mbedtls_cipher_context_t ctx; const mbedtls_cipher_info_t *cipher_info; - unsigned char K1[MBEDTLS_CIPHER_BLKSIZE_MAX]; - unsigned char K2[MBEDTLS_CIPHER_BLKSIZE_MAX]; + unsigned char K1[MBEDTLS_CMAC_MAX_BLOCK_SIZE]; + unsigned char K2[MBEDTLS_CMAC_MAX_BLOCK_SIZE]; cipher_info = mbedtls_cipher_info_from_type(cipher_type); if (cipher_info == NULL) { @@ -890,7 +894,7 @@ static int cmac_test_wth_cipher(int verbose, { const mbedtls_cipher_info_t *cipher_info; int i, ret = 0; - unsigned char output[MBEDTLS_CIPHER_BLKSIZE_MAX]; + unsigned char output[MBEDTLS_CMAC_MAX_BLOCK_SIZE]; cipher_info = mbedtls_cipher_info_from_type(cipher_type); if (cipher_info == NULL) { @@ -1000,6 +1004,7 @@ int mbedtls_cmac_self_test(int verbose) } /* AES-192 */ +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) if ((ret = cmac_test_subkeys(verbose, "AES 192", aes_192_key, @@ -1023,8 +1028,10 @@ int mbedtls_cmac_self_test(int verbose) NB_CMAC_TESTS_PER_KEY)) != 0) { return ret; } +#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ /* AES-256 */ +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) if ((ret = cmac_test_subkeys(verbose, "AES 256", aes_256_key, @@ -1048,6 +1055,7 @@ int mbedtls_cmac_self_test(int verbose) NB_CMAC_TESTS_PER_KEY)) != 0) { return ret; } +#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ #endif /* MBEDTLS_AES_C */ #if defined(MBEDTLS_DES_C) diff --git a/ra/fsp/src/rm_psa_crypto/ctr_drbg_alt.c b/ra/fsp/src/rm_psa_crypto/ctr_drbg_alt.c index d739e7de9..977adf610 100644 --- a/ra/fsp/src/rm_psa_crypto/ctr_drbg_alt.c +++ b/ra/fsp/src/rm_psa_crypto/ctr_drbg_alt.c @@ -21,7 +21,7 @@ /* * The NIST SP 800-90 DRBGs are described in the following publication. * - * http://csrc.nist.gov/publications/nistpubs/800-90/SP800-90revised_March2007.pdf + * https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-90r.pdf */ #include "common.h" @@ -78,6 +78,10 @@ void mbedtls_ctr_drbg_init(mbedtls_ctr_drbg_context *ctx) #endif } +/* + * This function resets CTR_DRBG context to the state immediately + * after initial call of mbedtls_ctr_drbg_init(). + */ void mbedtls_ctr_drbg_free(mbedtls_ctr_drbg_context *ctx) { if (ctx == NULL) { diff --git a/ra/fsp/src/rm_psa_crypto/ecdh_alt.c b/ra/fsp/src/rm_psa_crypto/ecdh_alt.c index b3bfec69a..9e962590b 100644 --- a/ra/fsp/src/rm_psa_crypto/ecdh_alt.c +++ b/ra/fsp/src/rm_psa_crypto/ecdh_alt.c @@ -22,7 +22,7 @@ /* * References: * - * SEC1 http://www.secg.org/index.php?action=secg,docs_secg + * SEC1 https://www.secg.org/sec1-v2.pdf * RFC 4492 */ diff --git a/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c b/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c index ed1096863..0c10eeee4 100644 --- a/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c +++ b/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c @@ -79,6 +79,24 @@ static const hw_sce_ecc_generatesign_t g_ecdsa_generate_sign_lookup[][2] = #endif }; +static const hw_sce_ecc_generatesign_t g_ed_ecdsa_generate_sign_lookup[][2] = +{ + #if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_25519_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = + HW_SCE_ECC_255GenerateSign, + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX((ECC_25519_PRIVATE_KEY_LENGTH_BITS - 1))][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = + HW_SCE_ECC_255GenerateSign, + #endif + #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_25519_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_WRAPPED] = + HW_SCE_ECC_255HrkGenerateSign, + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX((ECC_25519_PRIVATE_KEY_LENGTH_BITS - 1))][RM_PSA_CRYPTO_ECC_KEY_WRAPPED] = + HW_SCE_ECC_255HrkGenerateSign, + #endif + #endif +}; + static const hw_sce_ecc_verifysign_t g_ecdsa_verify_sign_lookup[] = { #if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) || \ @@ -350,6 +368,12 @@ int ecp_can_do_sce (mbedtls_ecp_group_id gid) return 1; } #endif + #ifdef MBEDTLS_ECP_DP_CURVE25519_ENABLED + case MBEDTLS_ECP_DP_CURVE25519: + { + return 1; + } + #endif #endif default: @@ -394,6 +418,15 @@ int ecp_load_curve_attributes_sce (const mbedtls_ecp_group * grp, *pp_domain_param = (uint32_t *) &DomainParam_NIST_P521[0]; break; } + + case MBEDTLS_ECP_DP_CURVE25519: + { + *p_curve_type = SCE_ECC_CURVE_TYPE_NIST; + *p_cmd = 0x0; + priv_key_command = SCE_OEM_CMD_ED25519_PRIVATE; + *pp_domain_param = (uint32_t *) &DomainParam_NIST_Ed25519[0]; + break; + } #endif case MBEDTLS_ECP_DP_SECP256K1: @@ -474,8 +507,17 @@ int mbedtls_ecdsa_sign (mbedtls_ecp_group * grp, return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; } + if (MBEDTLS_ECP_DP_CURVE25519 == grp->id) + { + p_hw_sce_ecc_generatesign = + g_ed_ecdsa_generate_sign_lookup[RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(grp->pbits)][(bool) grp->vendor_ctx]; + } + else + { p_hw_sce_ecc_generatesign = g_ecdsa_generate_sign_lookup[RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(grp->pbits)][(bool) grp->vendor_ctx]; + } + if (NULL == p_hw_sce_ecc_generatesign) { return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; diff --git a/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c b/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c index bb0c3fba7..eabe40090 100644 --- a/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c @@ -393,6 +393,92 @@ fsp_err_t HW_SCE_ECC_384VerifySign (const uint32_t * InData_CurveType, } #if BSP_FEATURE_CRYPTO_HAS_RSIP7 +fsp_err_t HW_SCE_ECC_255GenerateSign (const uint32_t * InData_CurveType, + const uint32_t * InData_G, + const uint32_t * InData_PrivKey, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S) +{ + uint32_t signature[HW_SCE_ECDSA_DATA_BYTE_SIZE / 4U] = {0}; + uint32_t wrapped_private_key[13U]; + sce_oem_cmd_t key_command; + const uint32_t * p_domain_param; + + /* NIST curve */ + if (SCE_ECC_CURVE_TYPE_NIST == *InData_CurveType) + { + key_command = SCE_OEM_CMD_ECC_P256_PRIVATE; + p_domain_param = DomainParam_NIST_Ed25519; + } + else + { + key_command = SCE_OEM_CMD_ECC_SECP256K1_PRIVATE; + p_domain_param = DomainParam_Koblitz_secp256k1; + } + + /* Install the plaintext private key to get the wrapped key */ + fsp_err_t err = HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, + key_command, + NULL, + NULL, + (const uint8_t *) InData_PrivKey, + wrapped_private_key); + if (FSP_SUCCESS == err) + { + err = HW_SCE_EcdsaSignatureGenerateSubAdaptor(InData_CurveType, + InData_G, + wrapped_private_key, + InData_MsgDgst, + p_domain_param, + signature); + } + + if (FSP_SUCCESS == err) + { + memcpy(OutData_R, signature, (HW_SCE_ECDSA_DATA_BYTE_SIZE / 2U)); + memcpy(OutData_S, &signature[(HW_SCE_ECDSA_DATA_BYTE_SIZE / 4U) / 2U], (HW_SCE_ECDSA_DATA_BYTE_SIZE / 2U)); + } + + return err; +} + +fsp_err_t HW_SCE_ECC_255HrkGenerateSign (const uint32_t * InData_CurveType, + const uint32_t * InData_G, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S) +{ + const uint32_t * p_domain_param; + + /* NIST curve */ + if (SCE_ECC_CURVE_TYPE_NIST == *InData_CurveType) + { + p_domain_param = DomainParam_NIST_Ed25519; + } + /* Koblitz curve */ + else + { + p_domain_param = DomainParam_Koblitz_secp256k1; + } + + uint32_t signature[(HW_SCE_ECDSA_DATA_BYTE_SIZE / 4U)] = {0}; + fsp_err_t err = HW_SCE_EcdsaSignatureGenerateSubAdaptor(InData_CurveType, + InData_G, + InData_KeyIndex, + InData_MsgDgst, + p_domain_param, + signature); + if (FSP_SUCCESS == err) + { + memcpy(OutData_R, signature, (HW_SCE_ECDSA_DATA_BYTE_SIZE / 2U)); + memcpy(OutData_S, &signature[(HW_SCE_ECDSA_DATA_BYTE_SIZE / 4U) / 2U], (HW_SCE_ECDSA_DATA_BYTE_SIZE / 2U)); + } + + return err; +} + fsp_err_t HW_SCE_ECC_521VerifySign (const uint32_t * InData_CurveType, const uint32_t * InData_G, const uint32_t * InData_PubKey, diff --git a/ra/fsp/src/rm_psa_crypto/ecp_alt.c b/ra/fsp/src/rm_psa_crypto/ecp_alt.c index 399665136..0999e61b5 100644 --- a/ra/fsp/src/rm_psa_crypto/ecp_alt.c +++ b/ra/fsp/src/rm_psa_crypto/ecp_alt.c @@ -20,13 +20,15 @@ /* * References: * - * SEC1 http://www.secg.org/index.php?action=secg,docs_secg + * SEC1 https://www.secg.org/sec1-v2.pdf * GECC = Guide to Elliptic Curve Cryptography - Hankerson, Menezes, Vanstone * FIPS 186-3 http://csrc.nist.gov/publications/fips/fips186-3/fips_186-3.pdf * RFC 4492 for the related TLS structures and constants +* - https://www.rfc-editor.org/rfc/rfc4492 * RFC 7748 for the Curve448 and Curve25519 curve definitions +* - https://www.rfc-editor.org/rfc/rfc7748 * - * [Curve25519] http://cr.yp.to/ecdh/curve25519-20060209.pdf + * [Curve25519] https://cr.yp.to/ecdh/curve25519-20060209.pdf * * [2] CORON, Jean-S'ebastien. Resistance against differential power analysis * for elliptic curve cryptosystems. In : Cryptographic Hardware and @@ -70,7 +72,7 @@ #if defined(MBEDTLS_ECP_INTERNAL_ALT) #endif -#if defined(MBEDTLS_ECP_C) +#if defined(MBEDTLS_ECP_LIGHT) #include "mbedtls/ecp.h" #include "mbedtls/threading.h" @@ -93,7 +95,10 @@ * Counts of point addition and doubling, and field multiplications. * Used to test resistance of point multiplication to simple timing attacks. */ -static unsigned long add_count, dbl_count, mul_count; +#if defined(MBEDTLS_ECP_C) +static unsigned long add_count, dbl_count; +#endif /* MBEDTLS_ECP_C */ +static unsigned long mul_count; #endif #if defined(MBEDTLS_ECP_RESTARTABLE) @@ -320,6 +325,7 @@ int mbedtls_ecp_check_budget(const mbedtls_ecp_group *grp, #endif /* MBEDTLS_ECP_RESTARTABLE */ +#if defined(MBEDTLS_ECP_C) static void mpi_init_many(mbedtls_mpi *arr, size_t size) { while (size--) { @@ -333,6 +339,7 @@ static void mpi_free_many(mbedtls_mpi *arr, size_t size) mbedtls_mpi_free(arr++); } } +#endif /* MBEDTLS_ECP_C */ /* * List of supported curves: @@ -585,8 +592,21 @@ void mbedtls_ecp_group_free(mbedtls_ecp_group *grp) mbedtls_mpi_free(&grp->A); mbedtls_mpi_free(&grp->B); mbedtls_ecp_point_free(&grp->G); + +#if !defined(MBEDTLS_ECP_WITH_MPI_UINT) + mbedtls_mpi_free(&grp->N); + mbedtls_mpi_free(&grp->P); +#endif } +#if BSP_FEATURE_CRYPTO_HAS_RSIP7 + if (grp->id == MBEDTLS_ECP_DP_CURVE25519) + { + mbedtls_mpi_free(&grp->P); + mbedtls_mpi_free(&grp->N); + } +#endif + if (!ecp_group_is_static_comb_table(grp) && grp->T != NULL) { for (i = 0; i < grp->T_size; i++) { mbedtls_ecp_point_free(&grp->T[i]); @@ -946,9 +966,8 @@ int mbedtls_ecp_tls_read_group_id(mbedtls_ecp_group_id *grp, /* * Next two bytes are the namedcurve value */ - tls_id = *(*buf)++; - tls_id <<= 8; - tls_id |= *(*buf)++; + tls_id = MBEDTLS_GET_UINT16_BE(*buf, 0); + *buf += 2; if ((curve_info = mbedtls_ecp_curve_info_from_tls_id(tls_id)) == NULL) { return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; @@ -1243,7 +1262,7 @@ static int ecp_sw_rhs(const mbedtls_ecp_group *grp, MPI_ECP_SQR(rhs, X); /* Special case for A = -3 */ - if (grp->A.p == NULL) { + if (mbedtls_ecp_group_a_is_minus_3(grp)) { MPI_ECP_SUB_INT(rhs, rhs, 3); } else { MPI_ECP_ADD(rhs, rhs, &grp->A); @@ -1306,7 +1325,10 @@ static int mbedtls_ecp_sw_derive_y(const mbedtls_ecp_group *grp, mbedtls_mpi_free(&exp); return ret; } +#endif /* MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED */ +#if defined(MBEDTLS_ECP_C) +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) /* * For curves in short Weierstrass form, we do all the internal operations in * Jacobian coordinates. @@ -1511,7 +1533,7 @@ static int ecp_double_jac(const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* Special case for A = -3 */ - if (grp->A.p == NULL) { + if (mbedtls_ecp_group_a_is_minus_3(grp)) { /* tmp[0] <- M = 3(X + Z^2)(X - Z^2) */ MPI_ECP_SQR(&tmp[1], &P->Z); MPI_ECP_ADD(&tmp[2], &P->X, &tmp[1]); @@ -2725,6 +2747,7 @@ int mbedtls_ecp_mul(mbedtls_ecp_group *grp, mbedtls_ecp_point *R, { return mbedtls_ecp_mul_restartable(grp, R, m, P, f_rng, p_rng, NULL); } +#endif /* MBEDTLS_ECP_C */ #if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) /* @@ -2765,6 +2788,7 @@ static int ecp_check_pubkey_sw(const mbedtls_ecp_group *grp, const mbedtls_ecp_p } #endif /* MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED */ +#if defined(MBEDTLS_ECP_C) #if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) /* * R = m * P with shortcuts for m == 0, m == 1 and m == -1 @@ -2916,12 +2940,13 @@ int mbedtls_ecp_muladd(mbedtls_ecp_group *grp, mbedtls_ecp_point *R, return mbedtls_ecp_muladd_restartable(grp, R, m, P, n, Q, NULL); } #endif /* MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED */ +#endif /* MBEDTLS_ECP_C */ #if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) #if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) -#define ECP_MPI_INIT(s, n, p) { s, (n), (mbedtls_mpi_uint *) (p) } +#define ECP_MPI_INIT(_p, _n) { .p = (mbedtls_mpi_uint *) (_p), .s = 1, .n = (_n) } #define ECP_MPI_INIT_ARRAY(x) \ - ECP_MPI_INIT(1, sizeof(x) / sizeof(mbedtls_mpi_uint), x) + ECP_MPI_INIT(x, sizeof(x) / sizeof(mbedtls_mpi_uint)) /* * Constants for the two points other than 0, 1, -1 (mod p) in * https://cr.yp.to/ecdh.html#validate @@ -3165,9 +3190,9 @@ int mbedtls_ecp_gen_privkey(const mbedtls_ecp_group *grp, return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; } - #endif /* #ifdef FSP_NOT_DEFINED */ +#if defined(MBEDTLS_ECP_C) /* * Generate a keypair with configurable base point */ @@ -3209,6 +3234,7 @@ int mbedtls_ecp_gen_key(mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, return mbedtls_ecp_gen_keypair(&key->grp, &key->d, &key->Q, f_rng, p_rng); } +#endif /* MBEDTLS_ECP_C */ #define ECP_CURVE25519_KEY_SIZE 32 #define ECP_CURVE448_KEY_SIZE 56 @@ -3272,18 +3298,16 @@ int mbedtls_ecp_read_key(mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, ); } } - #endif #if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) if (mbedtls_ecp_get_type(&key->grp) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS) { MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(&key->d, buf, buflen)); - - MBEDTLS_MPI_CHK(mbedtls_ecp_check_privkey(&key->grp, &key->d)); - } - +} #endif + MBEDTLS_MPI_CHK(mbedtls_ecp_check_privkey(&key->grp, &key->d)); #endif - MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &key->d, buf, buflen ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &key->d, buf, buflen ) ); + cleanup: if (ret != 0) { @@ -3327,7 +3351,7 @@ int mbedtls_ecp_write_key(mbedtls_ecp_keypair *key, return ret; } - +#if defined(MBEDTLS_ECP_C) /* * Check a public-private key pair */ @@ -3368,6 +3392,7 @@ int mbedtls_ecp_check_pub_priv( return ret; } +#endif /* MBEDTLS_ECP_C */ /* * Export generic key-pair parameters. @@ -3394,6 +3419,7 @@ int mbedtls_ecp_export(const mbedtls_ecp_keypair *key, mbedtls_ecp_group *grp, #if defined(MBEDTLS_SELF_TEST) +#if defined(MBEDTLS_ECP_C) /* * PRNG for test - !!!INSECURE NEVER USE IN PRODUCTION!!! * @@ -3501,12 +3527,14 @@ static int self_test_point(int verbose, } return ret; } +#endif /* MBEDTLS_ECP_C */ /* * Checkup routine */ int mbedtls_ecp_self_test(int verbose) { +#if defined(MBEDTLS_ECP_C) int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_group grp; mbedtls_ecp_point R, P; @@ -3620,10 +3648,14 @@ int mbedtls_ecp_self_test(int verbose) } return ret; +#else /* MBEDTLS_ECP_C */ + (void) verbose; + return 0; +#endif /* MBEDTLS_ECP_C */ } #endif /* MBEDTLS_SELF_TEST */ #endif /* !MBEDTLS_ECP_ALT */ -#endif /* MBEDTLS_ECP_C */ +#endif /* MBEDTLS_ECP_LIGHT */ diff --git a/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c b/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c index c5a1b0f7a..51743ff8e 100644 --- a/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c @@ -112,8 +112,24 @@ fsp_err_t HW_SCE_ECC_521WrappedScalarMultiplication (const uint32_t * InData_Cur Domain_Param, OutData_R); } + #endif +fsp_err_t HW_SCE_ECC_ED25519WrappedScalarMultiplication (const uint32_t * InData_CurveType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_P, + const uint32_t * Domain_Param, + uint32_t * OutData_R) +{ + return HW_SCE_EccEd25519ScalarMultiplicationSubAdaptor(InData_CurveType, + InData_Cmd, + InData_KeyIndex, + InData_P, + Domain_Param, + OutData_R); +} + static const hw_sce_ecc_scalarmultiplication_t g_ecp_scalar_multiplication_lookup[][2] = { #if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) || \ @@ -149,6 +165,22 @@ static const hw_sce_ecc_scalarmultiplication_t g_ecp_scalar_multiplication_looku #endif }; +static const hw_sce_ecc_scalarmultiplication_t g_ecp_edscalar_multiplication_lookup[][2] = +{ + #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_25519_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = + HW_SCE_ECC_ED25519WrappedScalarMultiplication, + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX((ECC_25519_PRIVATE_KEY_LENGTH_BITS - 1U))][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = + HW_SCE_ECC_ED25519WrappedScalarMultiplication, + #endif + #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_25519_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_WRAPPED] = + HW_SCE_ECC_ED25519WrappedScalarMultiplication, + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX((ECC_25519_PRIVATE_KEY_LENGTH_BITS - 1U))][RM_PSA_CRYPTO_ECC_KEY_WRAPPED] = + HW_SCE_ECC_ED25519WrappedScalarMultiplication, + #endif +}; + /* * Generate a private key */ @@ -161,6 +193,7 @@ extern int ecp_load_curve_attributes_sce(const mbedtls_ecp_group * grp, uint32_t ** pp_domain_param); uint32_t ecp_load_key_size(bool wrapped_mode_ctx, const mbedtls_ecp_group * grp); +uint32_t ed_ecp_load_key_size(bool wrapped_mode_ctx, const mbedtls_ecp_group * grp); uint32_t ecp_load_key_size (bool wrapped_mode_ctx, const mbedtls_ecp_group * grp) { @@ -219,6 +252,24 @@ uint32_t ecp_load_key_size (bool wrapped_mode_ctx, const mbedtls_ecp_group * grp } } else +#endif +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + if ((ECC_25519_PRIVATE_KEY_LENGTH_BITS == grp->pbits) || ((ECC_25519_PRIVATE_KEY_LENGTH_BITS - 1) == grp->pbits)) + { + if (wrapped_mode_ctx == true) + { + /* Store size of wrapped private key */ + key_size_words = + R_SCE_BYTES_TO_WORDS(HW_SCE_ECC_WRAPPED_KEY_ADJUST(R_SCE_WORDS_TO_BYTES( + ECC_25519_PRIVATE_KEY_LENGTH_WORDS))); + ; + } + else + { + key_size_words = curve_bytes / 4; + } + } + else #endif { key_size_words = 0; @@ -227,6 +278,31 @@ uint32_t ecp_load_key_size (bool wrapped_mode_ctx, const mbedtls_ecp_group * grp return key_size_words; // NOLINT(readability-misleading-indentation) } +uint32_t ed_ecp_load_key_size (bool wrapped_mode_ctx, const mbedtls_ecp_group * grp) +{ + uint32_t key_size_words = 0; +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + size_t curve_bytes = PSA_BITS_TO_BYTES(grp->pbits); + if (wrapped_mode_ctx == true) + { + /* Store size of wrapped private key */ + key_size_words = + R_SCE_BYTES_TO_WORDS(HW_SCE_ECC_WRAPPED_KEY_ADJUST(R_SCE_WORDS_TO_BYTES( + ECC_25519_PRIVATE_KEY_LENGTH_WORDS))); + ; + } + else + { + key_size_words = curve_bytes / 4; + } +#else + (void) wrapped_mode_ctx; + (void) grp; +#endif + + return key_size_words; // NOLINT(readability-misleading-indentation) +} + int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, mbedtls_mpi * d, int (* f_rng)(void *, unsigned char *, size_t), @@ -263,7 +339,8 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, #if defined(MBEDTLS_CHECK_PARAMS) #if BSP_FEATURE_CRYPTO_HAS_RSIP7 - if ((ECC_256_PRIVATE_KEY_LENGTH_BITS != grp->pbits) && (ECC_384_PRIVATE_KEY_LENGTH_BITS != grp->pbits) && (ECC_521_PRIVATE_KEY_LENGTH_BITS != grp->pbits)) + if ((ECC_256_PRIVATE_KEY_LENGTH_BITS != grp->pbits) && (ECC_384_PRIVATE_KEY_LENGTH_BITS != grp->pbits) && + (ECC_521_PRIVATE_KEY_LENGTH_BITS != grp->pbits) && (ECC_25519_PRIVATE_KEY_LENGTH_BITS != grp->pbits)) #else if ((ECC_256_PRIVATE_KEY_LENGTH_BITS != grp->pbits) && (ECC_384_PRIVATE_KEY_LENGTH_BITS != grp->pbits)) #endif @@ -272,7 +349,14 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, } #endif - private_key_size_words = ecp_load_key_size((bool) grp->vendor_ctx, grp); + if(MBEDTLS_ECP_DP_CURVE25519 == grp->id) + { + private_key_size_words = ed_ecp_load_key_size((bool) grp->vendor_ctx, grp); + } + else + { + private_key_size_words = ecp_load_key_size((bool) grp->vendor_ctx, grp); + } if (0 == private_key_size_words) { return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; @@ -303,7 +387,7 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, ret = ecp_load_curve_attributes_sce(grp, &curve_type, &cmd, NULL, &p_domain_param); if (ret == 0) { - if (ECC_256_PRIVATE_KEY_LENGTH_BITS == grp->pbits) + if ((ECC_256_PRIVATE_KEY_LENGTH_BITS == grp->pbits) && (MBEDTLS_ECP_DP_CURVE25519 != grp->id)) { uint32_t dummy[sizeof(sce_ecc_public_key_index_t)] = {0}; if (FSP_SUCCESS != @@ -357,6 +441,24 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, } } #endif + #if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +// else if (ECC_25519_PRIVATE_KEY_LENGTH_BITS == grp->pbits) + else if (MBEDTLS_ECP_DP_CURVE25519 == grp->id) + { + sce_ecc25519_public_key_index_t public_key = {0}; + if (FSP_SUCCESS != + HW_SCE_GenerateEccEd25519RandomKeyIndexSub(&indata_key_type, p_domain_param, + (uint32_t *) &public_key.value, (uint32_t *) wrapped_key, + NULL)) + { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + else + { + memcpy(p_private_key_buff_32, wrapped_key, private_key_size_words * 4U); + } + } + #endif #endif else @@ -423,8 +525,16 @@ int mbedtls_ecp_mul_restartable (mbedtls_ecp_group * grp, return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; } + if(MBEDTLS_ECP_DP_CURVE25519 == grp->id) + { + p_hw_sce_ecc_scalarmultiplication = + g_ecp_edscalar_multiplication_lookup[RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(grp->pbits)][(bool) grp->vendor_ctx]; + } + else + { p_hw_sce_ecc_scalarmultiplication = g_ecp_scalar_multiplication_lookup[RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(grp->pbits)][(bool) grp->vendor_ctx]; + } if (NULL == p_hw_sce_ecc_scalarmultiplication) { return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; diff --git a/ra/fsp/src/rm_psa_crypto/ecp_curves_alt.c b/ra/fsp/src/rm_psa_crypto/ecp_curves_alt.c index 42c26e047..ea9324a87 100644 --- a/ra/fsp/src/rm_psa_crypto/ecp_curves_alt.c +++ b/ra/fsp/src/rm_psa_crypto/ecp_curves_alt.c @@ -22,7 +22,9 @@ #include "common.h" -#if defined(MBEDTLS_ECP_C) +#if !defined(MBEDTLS_ECP_WITH_MPI_UINT) + +#if defined(MBEDTLS_ECP_LIGHT) #include "mbedtls/ecp.h" #include "mbedtls/platform_util.h" @@ -559,7 +561,7 @@ static const mbedtls_mpi_uint brainpoolP512r1_n[] = { static inline void ecp_mpi_load(mbedtls_mpi *X, const mbedtls_mpi_uint *p, size_t len) { X->s = 1; - X->n = len / sizeof(mbedtls_mpi_uint); + X->n = (unsigned short) (len / sizeof(mbedtls_mpi_uint)); X->p = (mbedtls_mpi_uint *) p; } @@ -608,26 +610,18 @@ static int ecp_group_load( mbedtls_ecp_group *grp, /* Forward declarations */ #if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) static int ecp_mod_p192(mbedtls_mpi *); -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p192_raw(mbedtls_mpi_uint *Np, size_t Nn); #endif #if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) static int ecp_mod_p224(mbedtls_mpi *); -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p224_raw(mbedtls_mpi_uint *X, size_t X_limbs); #endif #if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) static int ecp_mod_p256(mbedtls_mpi *); -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p256_raw(mbedtls_mpi_uint *X, size_t X_limbs); #endif #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) static int ecp_mod_p384(mbedtls_mpi *); #endif #if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) static int ecp_mod_p521(mbedtls_mpi *); -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p521_raw(mbedtls_mpi_uint *N_p, size_t N_n); #endif #define NIST_MODP(P) grp->modp = ecp_mod_ ## P; @@ -714,8 +708,11 @@ static int ecp_use_curve25519(mbedtls_ecp_group *grp) */ static int ecp_use_curve448(mbedtls_ecp_group *grp) { + mbedtls_mpi Ns; int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi_init(&Ns); + /* Actually ( A + 2 ) / 4 */ MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &grp->A, 16, "98AA" ) ); @@ -743,6 +740,7 @@ static int ecp_use_curve448(mbedtls_ecp_group *grp) grp->nbits = 447; cleanup: + mbedtls_mpi_free(&Ns); if (ret != 0) { mbedtls_ecp_group_free(grp); } @@ -892,12 +890,10 @@ static inline void carry64(mbedtls_mpi_uint *dst, mbedtls_mpi_uint *carry) } #define WIDTH 8 / sizeof(mbedtls_mpi_uint) -#define A(i) Np + (i) * WIDTH -#define ADD(i) add64(p, A(i), &c) +#define A(i) N->p + (i) * WIDTH +#define ADD(i) add64(p, A(i), &c) #define NEXT p += WIDTH; carry64(p, &c) #define LAST p += WIDTH; *p = c; while (++p < end) *p = 0 -#define RESET last_carry[0] = c; c = 0; p = Np -#define ADD_LAST add64(p, last_carry, &c) /* * Fast quasi-reduction modulo p192 (FIPS 186-3 D.2.1) @@ -905,42 +901,21 @@ static inline void carry64(mbedtls_mpi_uint *dst, mbedtls_mpi_uint *carry) static int ecp_mod_p192(mbedtls_mpi *N) { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - size_t expected_width = 2 * ((192 + biL - 1) / biL); - MBEDTLS_MPI_CHK(mbedtls_mpi_grow(N, expected_width)); - ret = mbedtls_ecp_mod_p192_raw(N->p, expected_width); - -cleanup: - return ret; -} - -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p192_raw(mbedtls_mpi_uint *Np, size_t Nn) -{ - mbedtls_mpi_uint c = 0, last_carry[WIDTH] = { 0 }; + mbedtls_mpi_uint c = 0; mbedtls_mpi_uint *p, *end; - if (Nn != 2*((192 + biL - 1)/biL)) { - return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; - } - - p = Np; - end = p + Nn; - - ADD(3); ADD(5); NEXT; // A0 += A3 + A5 - ADD(3); ADD(4); ADD(5); NEXT; // A1 += A3 + A4 + A5 - ADD(4); ADD(5); // A2 += A4 + A5 + /* Make sure we have enough blocks so that A(5) is legal */ + MBEDTLS_MPI_CHK(mbedtls_mpi_grow(N, 6 * WIDTH)); - RESET; + p = N->p; + end = p + N->n; - /* Use the reduction for the carry as well: - * 2^192 * last_carry = 2^64 * last_carry + last_carry mod P192 - */ - ADD_LAST; NEXT; // A0 += last_carry - ADD_LAST; NEXT; // A1 += last_carry + ADD(3); ADD(5); NEXT; // A0 += A3 + A5 + ADD(3); ADD(4); ADD(5); NEXT; // A1 += A3 + A4 + A5 + ADD(4); ADD(5); LAST; // A2 += A4 + A5 - LAST; // A2 += carry - - return 0; +cleanup: + return ret; } #undef WIDTH @@ -948,260 +923,11 @@ int mbedtls_ecp_mod_p192_raw(mbedtls_mpi_uint *Np, size_t Nn) #undef ADD #undef NEXT #undef LAST -#undef RESET -#undef ADD_LAST #endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ #if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || \ defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || \ defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) - -/* - * The reader is advised to first understand ecp_mod_p192() since the same - * general structure is used here, but with additional complications: - * (1) chunks of 32 bits, and (2) subtractions. - */ - -/* - * For these primes, we need to handle data in chunks of 32 bits. - * This makes it more complicated if we use 64 bits limbs in MPI, - * which prevents us from using a uniform access method as for p192. - * - * So, we define a mini abstraction layer to access 32 bit chunks, - * load them in 'cur' for work, and store them back from 'cur' when done. - * - * While at it, also define the size of N in terms of 32-bit chunks. - */ -#define LOAD32 cur = A(i); - -#if defined(MBEDTLS_HAVE_INT32) /* 32 bit */ - -#define MAX32 X_limbs -#define A(j) X[j] -#define STORE32 X[i] = (mbedtls_mpi_uint) cur; -#define STORE0 X[i] = 0; - -#else /* 64 bit */ - -#define MAX32 X_limbs * 2 -#define A(j) \ - (j) % 2 ? \ - (uint32_t) (X[(j) / 2] >> 32) : \ - (uint32_t) (X[(j) / 2]) -#define STORE32 \ - if (i % 2) { \ - X[i/2] &= 0x00000000FFFFFFFF; \ - X[i/2] |= (uint64_t) (cur) << 32; \ - } else { \ - X[i/2] &= 0xFFFFFFFF00000000; \ - X[i/2] |= (uint32_t) cur; \ - } - -#define STORE0 \ - if (i % 2) { \ - X[i/2] &= 0x00000000FFFFFFFF; \ - } else { \ - X[i/2] &= 0xFFFFFFFF00000000; \ - } - -#endif - -static inline int8_t extract_carry(int64_t cur) -{ - return (int8_t) (cur >> 32); -} - -#define ADD(j) cur += A(j) -#define SUB(j) cur -= A(j) - -#define ADD_CARRY(cc) cur += (cc) -#define SUB_CARRY(cc) cur -= (cc) - -#define ADD_LAST ADD_CARRY(last_c) -#define SUB_LAST SUB_CARRY(last_c) - -/* - * Helpers for the main 'loop' - */ -#define INIT(b) \ - int8_t c = 0, last_c; \ - int64_t cur; \ - size_t i = 0; \ - LOAD32; - -#define NEXT \ - c = extract_carry(cur); \ - STORE32; i++; LOAD32; \ - ADD_CARRY(c); - -#define RESET \ - c = extract_carry(cur); \ - last_c = c; \ - STORE32; i = 0; LOAD32; \ - c = 0; \ - -#define LAST \ - c = extract_carry(cur); \ - STORE32; i++; \ - if (c != 0) \ - return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; \ - while (i < MAX32) { STORE0; i++; } - -#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) - -/* - * Fast quasi-reduction modulo p224 (FIPS 186-3 D.2.2) - */ -static int ecp_mod_p224(mbedtls_mpi *N) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - size_t expected_width = 2 * 224 / biL; - MBEDTLS_MPI_CHK(mbedtls_mpi_grow(N, expected_width)); - ret = mbedtls_ecp_mod_p224_raw(N->p, expected_width); -cleanup: - return ret; -} - -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p224_raw(mbedtls_mpi_uint *X, size_t X_limbs) -{ - if (X_limbs != 2 * 224 / biL) { - return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; - } - - INIT(224); - - SUB(7); SUB(11); NEXT; // A0 += -A7 - A11 - SUB(8); SUB(12); NEXT; // A1 += -A8 - A12 - SUB(9); SUB(13); NEXT; // A2 += -A9 - A13 - SUB(10); ADD(7); ADD(11); NEXT; // A3 += -A10 + A7 + A11 - SUB(11); ADD(8); ADD(12); NEXT; // A4 += -A11 + A8 + A12 - SUB(12); ADD(9); ADD(13); NEXT; // A5 += -A12 + A9 + A13 - SUB(13); ADD(10); // A6 += -A13 + A10 - - RESET; - - /* Use 2^224 = P + 2^96 - 1 to modulo reduce the final carry */ - SUB_LAST; NEXT; // A0 -= last_c - ; NEXT; // A1 - ; NEXT; // A2 - ADD_LAST; NEXT; // A3 += last_c - ; NEXT; // A4 - ; NEXT; // A5 - // A6 - - /* The carry reduction cannot generate a carry - * (see commit 73e8553 for details)*/ - - LAST; - - return 0; -} - -#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) - -/* - * Fast quasi-reduction modulo p256 (FIPS 186-3 D.2.3) - */ -static int ecp_mod_p256(mbedtls_mpi *N) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - size_t expected_width = 2 * 256 / biL; - MBEDTLS_MPI_CHK(mbedtls_mpi_grow(N, expected_width)); - ret = mbedtls_ecp_mod_p256_raw(N->p, expected_width); -cleanup: - return ret; -} - -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p256_raw(mbedtls_mpi_uint *X, size_t X_limbs) -{ - if (X_limbs != 2 * 256 / biL) { - return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; - } - - INIT(256); - - ADD(8); ADD(9); - SUB(11); SUB(12); SUB(13); SUB(14); NEXT; // A0 - - ADD(9); ADD(10); - SUB(12); SUB(13); SUB(14); SUB(15); NEXT; // A1 - - ADD(10); ADD(11); - SUB(13); SUB(14); SUB(15); NEXT; // A2 - - ADD(11); ADD(11); ADD(12); ADD(12); ADD(13); - SUB(15); SUB(8); SUB(9); NEXT; // A3 - - ADD(12); ADD(12); ADD(13); ADD(13); ADD(14); - SUB(9); SUB(10); NEXT; // A4 - - ADD(13); ADD(13); ADD(14); ADD(14); ADD(15); - SUB(10); SUB(11); NEXT; // A5 - - ADD(14); ADD(14); ADD(15); ADD(15); ADD(14); ADD(13); - SUB(8); SUB(9); NEXT; // A6 - - ADD(15); ADD(15); ADD(15); ADD(8); - SUB(10); SUB(11); SUB(12); SUB(13); // A7 - - RESET; - - /* Use 2^224 * (2^32 - 1) + 2^192 + 2^96 - 1 - * to modulo reduce the final carry. */ - ADD_LAST; NEXT; // A0 - ; NEXT; // A1 - ; NEXT; // A2 - SUB_LAST; NEXT; // A3 - ; NEXT; // A4 - ; NEXT; // A5 - SUB_LAST; NEXT; // A6 - ADD_LAST; // A7 - - RESET; - - /* Use 2^224 * (2^32 - 1) + 2^192 + 2^96 - 1 - * to modulo reduce the carry generated by the previous reduction. */ - ADD_LAST; NEXT; // A0 - ; NEXT; // A1 - ; NEXT; // A2 - SUB_LAST; NEXT; // A3 - ; NEXT; // A4 - ; NEXT; // A5 - SUB_LAST; NEXT; // A6 - ADD_LAST; // A7 - - LAST; - - return 0; -} - -#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ - -#undef LOAD32 -#undef MAX32 -#undef A -#undef STORE32 -#undef STORE0 -#undef ADD -#undef SUB -#undef ADD_CARRY -#undef SUB_CARRY -#undef ADD_LAST -#undef SUB_LAST -#undef INIT -#undef NEXT -#undef RESET -#undef LAST - -#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED || - MBEDTLS_ECP_DP_SECP256R1_ENABLED || - MBEDTLS_ECP_DP_SECP384R1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) /* * The reader is advised to first understand ecp_mod_p192() since the same * general structure is used here, but with additional complications: @@ -1264,7 +990,7 @@ static inline void sub32(uint32_t *dst, uint32_t src, signed char *carry) * Helpers for the main 'loop' * (see fix_negative for the motivation of C) */ -#define INIT(b) \ +#define INIT(b) \ int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; \ signed char c = 0, cc; \ uint32_t cur; \ @@ -1322,6 +1048,64 @@ static inline int fix_negative( mbedtls_mpi *N, signed char c, mbedtls_mpi *C, s return( ret ); } +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +/* + * Fast quasi-reduction modulo p224 (FIPS 186-3 D.2.2) + */ +static int ecp_mod_p224(mbedtls_mpi *N) +{ + INIT(224); + + SUB(7); SUB(11); NEXT; // A0 += -A7 - A11 + SUB(8); SUB(12); NEXT; // A1 += -A8 - A12 + SUB(9); SUB(13); NEXT; // A2 += -A9 - A13 + SUB(10); ADD(7); ADD(11); NEXT; // A3 += -A10 + A7 + A11 + SUB(11); ADD(8); ADD(12); NEXT; // A4 += -A11 + A8 + A12 + SUB(12); ADD(9); ADD(13); NEXT; // A5 += -A12 + A9 + A13 + SUB(13); ADD(10); LAST; // A6 += -A13 + A10 + +cleanup: + return ret; +} +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +/* + * Fast quasi-reduction modulo p256 (FIPS 186-3 D.2.3) + */ +static int ecp_mod_p256(mbedtls_mpi *N) +{ + INIT(256); + + ADD(8); ADD(9); + SUB(11); SUB(12); SUB(13); SUB(14); NEXT; // A0 + + ADD(9); ADD(10); + SUB(12); SUB(13); SUB(14); SUB(15); NEXT; // A1 + + ADD(10); ADD(11); + SUB(13); SUB(14); SUB(15); NEXT; // A2 + + ADD(11); ADD(11); ADD(12); ADD(12); ADD(13); + SUB(15); SUB(8); SUB(9); NEXT; // A3 + + ADD(12); ADD(12); ADD(13); ADD(13); ADD(14); + SUB(9); SUB(10); NEXT; // A4 + + ADD(13); ADD(13); ADD(14); ADD(14); ADD(15); + SUB(10); SUB(11); NEXT; // A5 + + ADD(14); ADD(14); ADD(15); ADD(15); ADD(14); ADD(13); + SUB(8); SUB(9); NEXT; // A6 + + ADD(15); ADD(15); ADD(15); ADD(8); + SUB(10); SUB(11); SUB(12); SUB(13); LAST; // A7 + +cleanup: + return ret; +} +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) /* * Fast quasi-reduction modulo p384 (FIPS 186-3 D.2.4) @@ -1379,10 +1163,16 @@ static int ecp_mod_p384(mbedtls_mpi *N) #undef NEXT #undef LAST -#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED || +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED || + MBEDTLS_ECP_DP_SECP256R1_ENABLED || MBEDTLS_ECP_DP_SECP384R1_ENABLED */ #if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +/* + * Here we have an actual Mersenne prime, so things are more straightforward. + * However, chunks are aligned on a 'weird' boundary (521 bits). + */ + /* Size of p521 in terms of mbedtls_mpi_uint */ #define P521_WIDTH (521 / 8 / sizeof(mbedtls_mpi_uint) + 1) @@ -1390,81 +1180,48 @@ static int ecp_mod_p384(mbedtls_mpi *N) #define P521_MASK 0x01FF /* - * Fast quasi-reduction modulo p521 = 2^521 - 1 (FIPS 186-3 D.2.5) + * Fast quasi-reduction modulo p521 (FIPS 186-3 D.2.5) + * Write N as A1 + 2^521 A0, return A0 + A1 */ static int ecp_mod_p521(mbedtls_mpi *N) { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - size_t expected_width = 2 * P521_WIDTH; - MBEDTLS_MPI_CHK(mbedtls_mpi_grow(N, expected_width)); - ret = mbedtls_ecp_mod_p521_raw(N->p, expected_width); -cleanup: - return ret; -} + size_t i; + mbedtls_mpi M; + mbedtls_mpi_uint Mp[P521_WIDTH + 1]; + /* Worst case for the size of M is when mbedtls_mpi_uint is 16 bits: + * we need to hold bits 513 to 1056, which is 34 limbs, that is + * P521_WIDTH + 1. Otherwise P521_WIDTH is enough. */ -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p521_raw(mbedtls_mpi_uint *X, size_t X_limbs) -{ - mbedtls_mpi_uint carry = 0; + if (N->n < P521_WIDTH) { + return 0; + } - if (X_limbs != 2 * P521_WIDTH || X[2 * P521_WIDTH - 1] != 0) { - return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + /* M = A1 */ + M.s = 1; + M.n = N->n - (P521_WIDTH - 1); + if (M.n > P521_WIDTH + 1) { + M.n = P521_WIDTH + 1; + } + M.p = Mp; + memcpy(Mp, N->p + P521_WIDTH - 1, M.n * sizeof(mbedtls_mpi_uint)); + MBEDTLS_MPI_CHK(mbedtls_mpi_shift_r(&M, 521 % (8 * sizeof(mbedtls_mpi_uint)))); + + /* N = A0 */ + N->p[P521_WIDTH - 1] &= P521_MASK; + for (i = P521_WIDTH; i < N->n; i++) { + N->p[i] = 0; } - /* Step 1: Reduction to P521_WIDTH limbs */ - /* Helper references for bottom part of X */ - mbedtls_mpi_uint *X0 = X; - size_t X0_limbs = P521_WIDTH; - /* Helper references for top part of X */ - mbedtls_mpi_uint *X1 = X + X0_limbs; - size_t X1_limbs = X_limbs - X0_limbs; - /* Split X as X0 + 2^P521_WIDTH X1 and compute X0 + 2^(biL - 9) X1. - * (We are using that 2^P521_WIDTH = 2^(512 + biL) and that - * 2^(512 + biL) X1 = 2^(biL - 9) X1 mod P521.) - * The high order limb of the result will be held in carry and the rest - * in X0 (that is the result will be represented as - * 2^P521_WIDTH carry + X0). - * - * Also, note that the resulting carry is either 0 or 1: - * X0 < 2^P521_WIDTH = 2^(512 + biL) and X1 < 2^(P521_WIDTH-biL) = 2^512 - * therefore - * X0 + 2^(biL - 9) X1 < 2^(512 + biL) + 2^(512 + biL - 9) - * which in turn is less than 2 * 2^(512 + biL). - */ - mbedtls_mpi_uint shift = ((mbedtls_mpi_uint) 1u) << (biL - 9); - carry = mbedtls_mpi_core_mla(X0, X0_limbs, X1, X1_limbs, shift); - /* Set X to X0 (by clearing the top part). */ - memset(X1, 0, X1_limbs * sizeof(mbedtls_mpi_uint)); - - /* Step 2: Reduction modulo P521 - * - * At this point X is reduced to P521_WIDTH limbs. What remains is to add - * the carry (that is 2^P521_WIDTH carry) and to reduce mod P521. */ - - /* 2^P521_WIDTH carry = 2^(512 + biL) carry = 2^(biL - 9) carry mod P521. - * Also, recall that carry is either 0 or 1. */ - mbedtls_mpi_uint addend = carry << (biL - 9); - /* Keep the top 9 bits and reduce the rest, using 2^521 = 1 mod P521. */ - addend += (X[P521_WIDTH - 1] >> 9); - X[P521_WIDTH - 1] &= P521_MASK; - - /* Reuse the top part of X (already zeroed) as a helper array for - * carrying out the addition. */ - mbedtls_mpi_uint *addend_arr = X + P521_WIDTH; - addend_arr[0] = addend; - (void) mbedtls_mpi_core_add(X, X, addend_arr, P521_WIDTH); - /* Both addends were less than P521 therefore X < 2 * P521. (This also means - * that the result fit in P521_WIDTH limbs and there won't be any carry.) */ - - /* Clear the reused part of X. */ - addend_arr[0] = 0; + /* N = A0 + A1 */ + MBEDTLS_MPI_CHK(mbedtls_mpi_add_abs(N, N, &M)); - return 0; +cleanup: + return ret; } #undef P521_WIDTH #undef P521_MASK - #endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ #endif /* MBEDTLS_ECP_NIST_OPTIM */ @@ -1512,8 +1269,9 @@ static int ecp_mod_p255(mbedtls_mpi *N) /* Number of limbs fully occupied by 2^224 (max), and limbs used by it (min) */ #define DIV_ROUND_UP(X, Y) (((X) + (Y) -1) / (Y)) -#define P224_WIDTH_MIN (28 / sizeof(mbedtls_mpi_uint)) -#define P224_WIDTH_MAX DIV_ROUND_UP(28, sizeof(mbedtls_mpi_uint)) +#define P224_SIZE (224 / 8) +#define P224_WIDTH_MIN (P224_SIZE / sizeof(mbedtls_mpi_uint)) +#define P224_WIDTH_MAX DIV_ROUND_UP(P224_SIZE, sizeof(mbedtls_mpi_uint)) #define P224_UNUSED_BITS ((P224_WIDTH_MAX * sizeof(mbedtls_mpi_uint) * 8) - 224) /* @@ -1615,9 +1373,9 @@ static inline int ecp_mod_koblitz(mbedtls_mpi *N, mbedtls_mpi_uint *Rp, size_t p M.p = Mp; /* M = A1 */ - M.n = N->n - (p_limbs - adjust); + M.n = (unsigned short) (N->n - (p_limbs - adjust)); if (M.n > p_limbs + adjust) { - M.n = p_limbs + adjust; + M.n = (unsigned short) (p_limbs + adjust); } memset(Mp, 0, sizeof(Mp)); memcpy(Mp, N->p + p_limbs - adjust, M.n * sizeof(mbedtls_mpi_uint)); @@ -1641,9 +1399,9 @@ static inline int ecp_mod_koblitz(mbedtls_mpi *N, mbedtls_mpi_uint *Rp, size_t p /* Second pass */ /* M = A1 */ - M.n = N->n - (p_limbs - adjust); + M.n = (unsigned short) (N->n - (p_limbs - adjust)); if (M.n > p_limbs + adjust) { - M.n = p_limbs + adjust; + M.n = (unsigned short) (p_limbs + adjust); } memset(Mp, 0, sizeof(Mp)); memcpy(Mp, N->p + p_limbs - adjust, M.n * sizeof(mbedtls_mpi_uint)); @@ -1724,187 +1482,16 @@ static int ecp_mod_p256k1(mbedtls_mpi *N) #endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ #if defined(MBEDTLS_TEST_HOOKS) + MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_modulus_setup(mbedtls_mpi_mod_modulus *N, - const mbedtls_ecp_group_id id, - const mbedtls_ecp_curve_type ctype) +mbedtls_ecp_variant mbedtls_ecp_get_variant(void) { - mbedtls_mpi_uint *p = NULL; - size_t p_limbs; - - if (!(ctype == (mbedtls_ecp_curve_type) MBEDTLS_ECP_MOD_COORDINATE || \ - ctype == (mbedtls_ecp_curve_type) MBEDTLS_ECP_MOD_SCALAR)) { - return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; - } - - switch (id) { -#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) - case MBEDTLS_ECP_DP_SECP192R1: - if (ctype == (mbedtls_ecp_curve_type) MBEDTLS_ECP_MOD_COORDINATE) { - p = (mbedtls_mpi_uint *) secp192r1_p; - p_limbs = CHARS_TO_LIMBS(sizeof(secp192r1_p)); - } else { - p = (mbedtls_mpi_uint *) secp192r1_n; - p_limbs = CHARS_TO_LIMBS(sizeof(secp192r1_n)); - } - break; -#endif - -#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) - case MBEDTLS_ECP_DP_SECP224R1: - if (ctype == (mbedtls_ecp_curve_type) MBEDTLS_ECP_MOD_COORDINATE) { - p = (mbedtls_mpi_uint *) secp224r1_p; - p_limbs = CHARS_TO_LIMBS(sizeof(secp224r1_p)); - } else { - p = (mbedtls_mpi_uint *) secp224r1_n; - p_limbs = CHARS_TO_LIMBS(sizeof(secp224r1_n)); - } - break; -#endif - -#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) - case MBEDTLS_ECP_DP_SECP256R1: - if (ctype == (mbedtls_ecp_curve_type) MBEDTLS_ECP_MOD_COORDINATE) { - p = (mbedtls_mpi_uint *) secp256r1_p; - p_limbs = CHARS_TO_LIMBS(sizeof(secp256r1_p)); - } else { - p = (mbedtls_mpi_uint *) secp256r1_n; - p_limbs = CHARS_TO_LIMBS(sizeof(secp256r1_n)); - } - break; -#endif - -#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) - case MBEDTLS_ECP_DP_SECP384R1: - if (ctype == (mbedtls_ecp_curve_type) MBEDTLS_ECP_MOD_COORDINATE) { - p = (mbedtls_mpi_uint *) secp384r1_p; - p_limbs = CHARS_TO_LIMBS(sizeof(secp384r1_p)); - } else { - p = (mbedtls_mpi_uint *) secp384r1_n; - p_limbs = CHARS_TO_LIMBS(sizeof(secp384r1_n)); - } - break; -#endif - -#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) - case MBEDTLS_ECP_DP_SECP521R1: - if (ctype == (mbedtls_ecp_curve_type) MBEDTLS_ECP_MOD_COORDINATE) { - p = (mbedtls_mpi_uint *) secp521r1_p; - p_limbs = CHARS_TO_LIMBS(sizeof(secp521r1_p)); - } else { - p = (mbedtls_mpi_uint *) secp521r1_n; - p_limbs = CHARS_TO_LIMBS(sizeof(secp521r1_n)); - } - break; -#endif - -#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) - case MBEDTLS_ECP_DP_BP256R1: - if (ctype == (mbedtls_ecp_curve_type) MBEDTLS_ECP_MOD_COORDINATE) { - p = (mbedtls_mpi_uint *) brainpoolP256r1_p; - p_limbs = CHARS_TO_LIMBS(sizeof(brainpoolP256r1_p)); - } else { - p = (mbedtls_mpi_uint *) brainpoolP256r1_n; - p_limbs = CHARS_TO_LIMBS(sizeof(brainpoolP256r1_n)); - } - break; -#endif - -#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) - case MBEDTLS_ECP_DP_BP384R1: - if (ctype == (mbedtls_ecp_curve_type) MBEDTLS_ECP_MOD_COORDINATE) { - p = (mbedtls_mpi_uint *) brainpoolP384r1_p; - p_limbs = CHARS_TO_LIMBS(sizeof(brainpoolP384r1_p)); - } else { - p = (mbedtls_mpi_uint *) brainpoolP384r1_n; - p_limbs = CHARS_TO_LIMBS(sizeof(brainpoolP384r1_n)); - } - break; -#endif - -#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) - case MBEDTLS_ECP_DP_BP512R1: - if (ctype == (mbedtls_ecp_curve_type) MBEDTLS_ECP_MOD_COORDINATE) { - p = (mbedtls_mpi_uint *) brainpoolP512r1_p; - p_limbs = CHARS_TO_LIMBS(sizeof(brainpoolP512r1_p)); - } else { - p = (mbedtls_mpi_uint *) brainpoolP512r1_n; - p_limbs = CHARS_TO_LIMBS(sizeof(brainpoolP512r1_n)); - } - break; -#endif - -#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) - case MBEDTLS_ECP_DP_CURVE25519: - if (ctype == (mbedtls_ecp_curve_type) MBEDTLS_ECP_MOD_COORDINATE) { - p = (mbedtls_mpi_uint *) curve25519_p; - p_limbs = CHARS_TO_LIMBS(sizeof(curve25519_p)); - } else { - p = (mbedtls_mpi_uint *) curve25519_n; - p_limbs = CHARS_TO_LIMBS(sizeof(curve25519_n)); - } - break; -#endif - -#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) - case MBEDTLS_ECP_DP_SECP192K1: - if (ctype == (mbedtls_ecp_curve_type) MBEDTLS_ECP_MOD_COORDINATE) { - p = (mbedtls_mpi_uint *) secp192k1_p; - p_limbs = CHARS_TO_LIMBS(sizeof(secp192k1_p)); - } else { - p = (mbedtls_mpi_uint *) secp192k1_n; - p_limbs = CHARS_TO_LIMBS(sizeof(secp192k1_n)); - } - break; -#endif - -#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) - case MBEDTLS_ECP_DP_SECP224K1: - if (ctype == (mbedtls_ecp_curve_type) MBEDTLS_ECP_MOD_COORDINATE) { - p = (mbedtls_mpi_uint *) secp224k1_p; - p_limbs = CHARS_TO_LIMBS(sizeof(secp224k1_p)); - } else { - p = (mbedtls_mpi_uint *) secp224k1_n; - p_limbs = CHARS_TO_LIMBS(sizeof(secp224k1_n)); - } - break; -#endif - -#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) - case MBEDTLS_ECP_DP_SECP256K1: - if (ctype == (mbedtls_ecp_curve_type) MBEDTLS_ECP_MOD_COORDINATE) { - p = (mbedtls_mpi_uint *) secp256k1_p; - p_limbs = CHARS_TO_LIMBS(sizeof(secp256k1_p)); - } else { - p = (mbedtls_mpi_uint *) secp256k1_n; - p_limbs = CHARS_TO_LIMBS(sizeof(secp256k1_n)); - } - break; -#endif - -#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) - case MBEDTLS_ECP_DP_CURVE448: - if (ctype == (mbedtls_ecp_curve_type) MBEDTLS_ECP_MOD_COORDINATE) { - p = (mbedtls_mpi_uint *) curve448_p; - p_limbs = CHARS_TO_LIMBS(sizeof(curve448_p)); - } else { - p = (mbedtls_mpi_uint *) curve448_n; - p_limbs = CHARS_TO_LIMBS(sizeof(curve448_n)); - } - break; -#endif - - default: - case MBEDTLS_ECP_DP_NONE: - return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; - } - - if (mbedtls_mpi_mod_modulus_setup(N, p, p_limbs, - MBEDTLS_MPI_MOD_REP_MONTGOMERY)) { - return MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - } - return 0; + return MBEDTLS_ECP_VARIANT_WITH_MPI_STRUCT; } + #endif /* MBEDTLS_TEST_HOOKS */ + #endif /* !MBEDTLS_ECP_ALT */ -#endif /* MBEDTLS_ECP_C */ + +#endif /* MBEDTLS_ECP_LIGHT */ +#endif /* MBEDTLS_ECP_WITH_MPI_UINT */ diff --git a/ra/fsp/src/rm_psa_crypto/gcm_alt.c b/ra/fsp/src/rm_psa_crypto/gcm_alt.c index f465ef115..632a92361 100644 --- a/ra/fsp/src/rm_psa_crypto/gcm_alt.c +++ b/ra/fsp/src/rm_psa_crypto/gcm_alt.c @@ -35,6 +35,7 @@ #include "mbedtls/platform.h" #include "mbedtls/platform_util.h" #include "mbedtls/error.h" +#include "mbedtls/constant_time.h" #include @@ -98,8 +99,8 @@ static int gcm_gen_table(mbedtls_gcm_context *ctx) } #endif -#if defined(MBEDTLS_AESCE_C) && defined(MBEDTLS_HAVE_ARM64) - if (mbedtls_aesce_has_support()) { +#if defined(MBEDTLS_AESCE_HAVE_CODE) + if (MBEDTLS_AESCE_HAS_SUPPORT()) { return 0; } #endif @@ -148,7 +149,7 @@ int mbedtls_gcm_setkey(mbedtls_gcm_context *ctx, return MBEDTLS_ERR_GCM_BAD_INPUT; } - if (cipher_info->block_size != 16) { + if (mbedtls_cipher_info_get_block_size(cipher_info) != 16) { return MBEDTLS_ERR_GCM_BAD_INPUT; } @@ -181,7 +182,7 @@ int mbedtls_gcm_setkey(mbedtls_gcm_context *ctx, * last4[x] = x times P^128 * where x and last4[x] are seen as elements of GF(2^128) as in [MGV] */ -static const uint64_t last4[16] = +static const uint16_t last4[16] = { 0x0000, 0x1c20, 0x3840, 0x2460, 0x7080, 0x6ca0, 0x48c0, 0x54e0, @@ -215,8 +216,8 @@ static void gcm_mult(mbedtls_gcm_context *ctx, const unsigned char x[16], } #endif /* MBEDTLS_AESNI_HAVE_CODE */ -#if defined(MBEDTLS_AESCE_C) && defined(MBEDTLS_HAVE_ARM64) - if (mbedtls_aesce_has_support()) { +#if defined(MBEDTLS_AESCE_HAVE_CODE) + if (MBEDTLS_AESCE_HAS_SUPPORT()) { unsigned char h[16]; /* mbedtls_aesce_gcm_mult needs big-endian input */ @@ -622,7 +623,7 @@ void mbedtls_gcm_free(mbedtls_gcm_context *ctx) static const int key_index_test_data[MAX_TESTS] = { 0, 0, 1, 1, 1, 1 }; -static const unsigned char key_test_data[MAX_TESTS][32] = +static const unsigned char key_test_data[][32] = { { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -640,7 +641,7 @@ static const size_t iv_len_test_data[MAX_TESTS] = static const int iv_index_test_data[MAX_TESTS] = { 0, 0, 1, 1, 1, 2 }; -static const unsigned char iv_test_data[MAX_TESTS][64] = +static const unsigned char iv_test_data[][64] = { { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, @@ -662,7 +663,7 @@ static const size_t add_len_test_data[MAX_TESTS] = static const int add_index_test_data[MAX_TESTS] = { 0, 0, 0, 1, 1, 1 }; -static const unsigned char additional_test_data[MAX_TESTS][64] = +static const unsigned char additional_test_data[][64] = { { 0x00 }, { 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef, @@ -676,7 +677,7 @@ static const size_t pt_len_test_data[MAX_TESTS] = static const int pt_index_test_data[MAX_TESTS] = { 0, 0, 1, 1, 1, 1 }; -static const unsigned char pt_test_data[MAX_TESTS][64] = +static const unsigned char pt_test_data[][64] = { { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, @@ -690,7 +691,7 @@ static const unsigned char pt_test_data[MAX_TESTS][64] = 0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55 }, }; -static const unsigned char ct_test_data[MAX_TESTS * 3][64] = +static const unsigned char ct_test_data[][64] = { { 0x00 }, { 0x03, 0x88, 0xda, 0xce, 0x60, 0xb6, 0xa3, 0x92, @@ -727,6 +728,7 @@ static const unsigned char ct_test_data[MAX_TESTS * 3][64] = 0xcc, 0xdc, 0xb2, 0x81, 0xd4, 0x8c, 0x7c, 0x6f, 0xd6, 0x28, 0x75, 0xd2, 0xac, 0xa4, 0x17, 0x03, 0x4c, 0x34, 0xae, 0xe5 }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) { 0x00 }, { 0x98, 0xe7, 0x24, 0x7c, 0x07, 0xf0, 0xfe, 0x41, 0x1c, 0x26, 0x7e, 0x43, 0x84, 0xb0, 0xf6, 0x00 }, @@ -797,9 +799,10 @@ static const unsigned char ct_test_data[MAX_TESTS * 3][64] = 0x2d, 0xa3, 0xeb, 0xf1, 0xc5, 0xd8, 0x2c, 0xde, 0xa2, 0x41, 0x89, 0x97, 0x20, 0x0e, 0xf8, 0x2e, 0x44, 0xae, 0x7e, 0x3f }, +#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ }; -static const unsigned char tag_test_data[MAX_TESTS * 3][16] = +static const unsigned char tag_test_data[][16] = { { 0x58, 0xe2, 0xfc, 0xce, 0xfa, 0x7e, 0x30, 0x61, 0x36, 0x7f, 0x1d, 0x57, 0xa4, 0xe7, 0x45, 0x5a }, @@ -813,6 +816,7 @@ static const unsigned char tag_test_data[MAX_TESTS * 3][16] = 0x56, 0x1b, 0xe1, 0x4a, 0xac, 0xa2, 0xfc, 0xcb }, { 0x61, 0x9c, 0xc5, 0xae, 0xff, 0xfe, 0x0b, 0xfa, 0x46, 0x2a, 0xf4, 0x3c, 0x16, 0x99, 0xd0, 0x50 }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) { 0xcd, 0x33, 0xb2, 0x8a, 0xc7, 0x73, 0xf7, 0x4b, 0xa0, 0x0e, 0xd1, 0xf3, 0x12, 0x57, 0x24, 0x35 }, { 0x2f, 0xf5, 0x8d, 0x80, 0x03, 0x39, 0x27, 0xab, @@ -837,6 +841,7 @@ static const unsigned char tag_test_data[MAX_TESTS * 3][16] = 0x5e, 0x45, 0x49, 0x13, 0xfe, 0x2e, 0xa8, 0xf2 }, { 0xa4, 0x4a, 0x82, 0x66, 0xee, 0x1c, 0x8e, 0xb0, 0xc8, 0xb5, 0xd4, 0xcf, 0x5a, 0xe9, 0xf1, 0x9a }, +#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ }; int mbedtls_gcm_self_test(int verbose) @@ -857,21 +862,31 @@ int mbedtls_gcm_self_test(int verbose) mbedtls_printf(" GCM note: using AESNI.\n"); } else #endif + +#if defined(MBEDTLS_AESCE_HAVE_CODE) + if (MBEDTLS_AESCE_HAS_SUPPORT()) { + mbedtls_printf(" GCM note: using AESCE.\n"); + } else +#endif + mbedtls_printf(" GCM note: built-in implementation.\n"); #endif /* MBEDTLS_GCM_ALT */ } - for (j = 0; j < 3; j++) { + static const int loop_limit = + (sizeof(ct_test_data) / sizeof(*ct_test_data)) / MAX_TESTS; + + for (j = 0; j < loop_limit; j++) { int key_len = 128 + 64 * j; for (i = 0; i < MAX_TESTS; i++) { - mbedtls_gcm_init(&ctx); - - if (verbose != 0) { + if (verbose != 0) { mbedtls_printf(" AES-GCM-%3d #%d (%s): ", key_len, i, "enc"); } + mbedtls_gcm_init(&ctx); + ret = mbedtls_gcm_setkey(&ctx, cipher, key_test_data[key_index_test_data[i]], key_len); diff --git a/ra/fsp/src/rm_psa_crypto/inc/cmac_alt.h b/ra/fsp/src/rm_psa_crypto/inc/cmac_alt.h index e012cdada..b920ba7cc 100644 --- a/ra/fsp/src/rm_psa_crypto/inc/cmac_alt.h +++ b/ra/fsp/src/rm_psa_crypto/inc/cmac_alt.h @@ -56,11 +56,11 @@ typedef enum e_sce_mbedtls_cmac_operation_state struct mbedtls_cmac_context_t { /** The internal state of the CMAC algorithm. */ - unsigned char MBEDTLS_PRIVATE(state)[MBEDTLS_CIPHER_BLKSIZE_MAX]; + unsigned char MBEDTLS_PRIVATE(state)[MBEDTLS_CMAC_MAX_BLOCK_SIZE]; /** Unprocessed data - either data that was not block aligned and is still * pending processing, or the final block. */ - unsigned char MBEDTLS_PRIVATE(unprocessed_block)[MBEDTLS_CIPHER_BLKSIZE_MAX]; + unsigned char MBEDTLS_PRIVATE(unprocessed_block)[MBEDTLS_CMAC_MAX_BLOCK_SIZE]; /** The length of data pending processing. */ size_t MBEDTLS_PRIVATE(unprocessed_len); diff --git a/ra/fsp/src/rm_psa_crypto/inc/ecp_alt.h b/ra/fsp/src/rm_psa_crypto/inc/ecp_alt.h index 25ef2b757..cf85893f2 100644 --- a/ra/fsp/src/rm_psa_crypto/inc/ecp_alt.h +++ b/ra/fsp/src/rm_psa_crypto/inc/ecp_alt.h @@ -39,10 +39,10 @@ extern "C" { // Alternate implementation // - #define RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(bits) ((((bits >> 7) & 1) | (bits & 8) >> 2) ) - #define RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT (0U) - #define RM_PSA_CRYPTO_ECC_KEY_WRAPPED (1U) - #define RM_PSA_CRYPTO_LARGEST_WRAPPED_ECC_PRIVATE_KEY_WORDS (25U) /* Corresponding to ECC P-521 curves on RSIP */ + #define RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(bits) ((((bits >> 7) & 1) | (bits & 8) >> 2)) + #define RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT (0U) + #define RM_PSA_CRYPTO_ECC_KEY_WRAPPED (1U) + #define RM_PSA_CRYPTO_LARGEST_WRAPPED_ECC_PRIVATE_KEY_WORDS (25U) /* Corresponding to ECC P-521 curves on RSIP */ #define PSA_ECC_BYTES_VENDOR_RAW(bit_length) \ ((bit_length) == \ @@ -53,22 +53,24 @@ extern "C" { PSA_BITS_TO_BYTES(ECC_521_PRIVATE_KEY_HRK_LENGTH_BITS) ? PSA_BITS_TO_BYTES(ECC_521_PRIVATE_KEY_LENGTH_BITS) : \ 0) - #define PSA_ECC_BITS_VENDOR_RAW(byte_length) \ - ((byte_length) == \ + #define PSA_ECC_BITS_VENDOR_RAW(byte_length) \ + ((byte_length) == \ PSA_BITS_TO_BYTES(ECC_256_PRIVATE_KEY_LENGTH_BITS) ? ECC_256_PRIVATE_KEY_LENGTH_BITS : \ - (byte_length) == \ + (byte_length) == \ PSA_BITS_TO_BYTES(ECC_384_PRIVATE_KEY_LENGTH_BITS) ? ECC_384_PRIVATE_KEY_LENGTH_BITS : \ - (byte_length) == \ + (byte_length) == \ PSA_BITS_TO_BYTES(ECC_521_PRIVATE_KEY_LENGTH_BITS) ? ECC_521_PRIVATE_KEY_LENGTH_BITS : \ 0) - - #define RM_PSA_CRYPTO_ECC_KEY_WRAPPED_SIZE_BYTES(bit_length) \ - ((bit_length) == \ - ECC_256_PRIVATE_KEY_LENGTH_BITS ? PSA_BITS_TO_BYTES(ECC_256_PRIVATE_KEY_HRK_LENGTH_BITS) : \ - (bit_length) == \ - ECC_384_PRIVATE_KEY_LENGTH_BITS ? PSA_BITS_TO_BYTES(ECC_384_PRIVATE_KEY_HRK_LENGTH_BITS) : \ - (bit_length) == \ - ECC_521_PRIVATE_KEY_LENGTH_BITS ? PSA_BITS_TO_BYTES(ECC_521_PRIVATE_KEY_HRK_LENGTH_BITS) : \ + + #define RM_PSA_CRYPTO_ECC_KEY_WRAPPED_SIZE_BYTES(bit_length) \ + ((bit_length) == \ + ECC_256_PRIVATE_KEY_LENGTH_BITS ? PSA_BITS_TO_BYTES(ECC_256_PRIVATE_KEY_HRK_LENGTH_BITS) : \ + (bit_length) == \ + ECC_384_PRIVATE_KEY_LENGTH_BITS ? PSA_BITS_TO_BYTES(ECC_384_PRIVATE_KEY_HRK_LENGTH_BITS) : \ + (bit_length) == \ + ECC_521_PRIVATE_KEY_LENGTH_BITS ? PSA_BITS_TO_BYTES(ECC_521_PRIVATE_KEY_HRK_LENGTH_BITS) : \ + (bit_length) == \ + ECC_25519_PRIVATE_KEY_LENGTH_BITS ? PSA_BITS_TO_BYTES(ECC_256_PRIVATE_KEY_HRK_LENGTH_BITS) : \ 0) /* @@ -136,7 +138,7 @@ typedef struct mbedtls_ecp_group void * vendor_ctx; /*!< Vendor defined context. */ } mbedtls_ecp_group; -///** +/// ** // * \name SECTION: Module settings // * // * The configuration options you can set for this module are in this section. @@ -144,8 +146,8 @@ typedef struct mbedtls_ecp_group // * \{ // */ // -// #define MBEDTLS_ECP_MAX_BYTES ((MBEDTLS_ECP_MAX_BITS + 7) / 8) -// #define MBEDTLS_ECP_MAX_PT_LEN (2 * MBEDTLS_ECP_MAX_BYTES + 1) +// #define MBEDTLS_ECP_MAX_BYTES ((MBEDTLS_ECP_MAX_BITS + 7) / 8) +// #define MBEDTLS_ECP_MAX_PT_LEN (2 * MBEDTLS_ECP_MAX_BYTES + 1) #if !defined(MBEDTLS_ECP_WINDOW_SIZE) diff --git a/ra/fsp/src/rm_psa_crypto/inc/rsa_alt.h b/ra/fsp/src/rm_psa_crypto/inc/rsa_alt.h index 0744d61ed..214d64631 100644 --- a/ra/fsp/src/rm_psa_crypto/inc/rsa_alt.h +++ b/ra/fsp/src/rm_psa_crypto/inc/rsa_alt.h @@ -115,15 +115,8 @@ typedef struct mbedtls_rsa_context #if defined(MBEDTLS_THREADING_C) mbedtls_threading_mutex_t mutex; /*!< Thread-safety mutex. */ #endif -} mbedtls_rsa_context; - -/* This declaration is here as well as in constant_time_internal.h but is excluded - * if MBEDTLS_RSA_ALT is defined. */ -int mbedtls_ct_rsaes_pkcs1_v15_unpadding(unsigned char * input, - size_t ilen, - unsigned char * output, - size_t output_max_len, - size_t * olen); +} +mbedtls_rsa_context; #endif /* MBEDTLS_RSA_ALT */ diff --git a/ra/fsp/src/rm_psa_crypto/rsa_alt.c b/ra/fsp/src/rm_psa_crypto/rsa_alt.c index e5c029e63..6a0c4da29 100644 --- a/ra/fsp/src/rm_psa_crypto/rsa_alt.c +++ b/ra/fsp/src/rm_psa_crypto/rsa_alt.c @@ -49,7 +49,7 @@ #include "mbedtls/error.h" #include "constant_time_internal.h" #include "mbedtls/constant_time.h" -#include "hash_info.h" +#include "md_psa.h" #include @@ -57,21 +57,165 @@ #include #endif -/* We use MD first if it's available (for compatibility reasons) - * and "fall back" to PSA otherwise (which needs psa_crypto_init()). */ -#if defined(MBEDTLS_PKCS1_V21) -#if !defined(MBEDTLS_MD_C) -#include "psa/crypto.h" -#include "mbedtls/psa_util.h" -#define PSA_TO_MBEDTLS_ERR(status) PSA_TO_MBEDTLS_ERR_LIST(status, \ - psa_to_md_errors, \ - psa_generic_status_to_mbedtls) -#endif /* !MBEDTLS_MD_C */ -#endif /* MBEDTLS_PKCS1_V21 */ - #include "mbedtls/platform.h" - #if defined(MBEDTLS_RSA_ALT) + +#if defined(MBEDTLS_PKCS1_V15) && defined(MBEDTLS_RSA_C) + +/** This function performs the unpadding part of a PKCS#1 v1.5 decryption + * operation (EME-PKCS1-v1_5 decoding). + * + * \note The return value from this function is a sensitive value + * (this is unusual). #MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE shouldn't happen + * in a well-written application, but 0 vs #MBEDTLS_ERR_RSA_INVALID_PADDING + * is often a situation that an attacker can provoke and leaking which + * one is the result is precisely the information the attacker wants. + * + * \param input The input buffer which is the payload inside PKCS#1v1.5 + * encryption padding, called the "encoded message EM" + * by the terminology. + * \param ilen The length of the payload in the \p input buffer. + * \param output The buffer for the payload, called "message M" by the + * PKCS#1 terminology. This must be a writable buffer of + * length \p output_max_len bytes. + * \param olen The address at which to store the length of + * the payload. This must not be \c NULL. + * \param output_max_len The length in bytes of the output buffer \p output. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE + * The output buffer is too small for the unpadded payload. + * \return #MBEDTLS_ERR_RSA_INVALID_PADDING + * The input doesn't contain properly formatted padding. + */ +static int mbedtls_ct_rsaes_pkcs1_v15_unpadding(unsigned char *input, + size_t ilen, + unsigned char *output, + size_t output_max_len, + size_t *olen) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t i, plaintext_max_size; + + /* The following variables take sensitive values: their value must + * not leak into the observable behavior of the function other than + * the designated outputs (output, olen, return value). Otherwise + * this would open the execution of the function to + * side-channel-based variants of the Bleichenbacher padding oracle + * attack. Potential side channels include overall timing, memory + * access patterns (especially visible to an adversary who has access + * to a shared memory cache), and branches (especially visible to + * an adversary who has access to a shared code cache or to a shared + * branch predictor). */ + size_t pad_count = 0; + mbedtls_ct_condition_t bad; + mbedtls_ct_condition_t pad_done; + size_t plaintext_size = 0; + mbedtls_ct_condition_t output_too_large; + + plaintext_max_size = (output_max_len > ilen - 11) ? ilen - 11 + : output_max_len; + + /* Check and get padding length in constant time and constant + * memory trace. The first byte must be 0. */ + bad = mbedtls_ct_bool(input[0]); + + + /* Decode EME-PKCS1-v1_5 padding: 0x00 || 0x02 || PS || 0x00 + * where PS must be at least 8 nonzero bytes. */ + bad = mbedtls_ct_bool_or(bad, mbedtls_ct_uint_ne(input[1], MBEDTLS_RSA_CRYPT)); + + /* Read the whole buffer. Set pad_done to nonzero if we find + * the 0x00 byte and remember the padding length in pad_count. */ + pad_done = MBEDTLS_CT_FALSE; + for (i = 2; i < ilen; i++) { + mbedtls_ct_condition_t found = mbedtls_ct_uint_eq(input[i], 0); + pad_done = mbedtls_ct_bool_or(pad_done, found); + pad_count += mbedtls_ct_uint_if_else_0(mbedtls_ct_bool_not(pad_done), 1); + } + + /* If pad_done is still zero, there's no data, only unfinished padding. */ + bad = mbedtls_ct_bool_or(bad, mbedtls_ct_bool_not(pad_done)); + + /* There must be at least 8 bytes of padding. */ + bad = mbedtls_ct_bool_or(bad, mbedtls_ct_uint_gt(8, pad_count)); + + /* If the padding is valid, set plaintext_size to the number of + * remaining bytes after stripping the padding. If the padding + * is invalid, avoid leaking this fact through the size of the + * output: use the maximum message size that fits in the output + * buffer. Do it without branches to avoid leaking the padding + * validity through timing. RSA keys are small enough that all the + * size_t values involved fit in unsigned int. */ + plaintext_size = mbedtls_ct_uint_if( + bad, (unsigned) plaintext_max_size, + (unsigned) (ilen - pad_count - 3)); + + /* Set output_too_large to 0 if the plaintext fits in the output + * buffer and to 1 otherwise. */ + output_too_large = mbedtls_ct_uint_gt(plaintext_size, + plaintext_max_size); + + /* Set ret without branches to avoid timing attacks. Return: + * - INVALID_PADDING if the padding is bad (bad != 0). + * - OUTPUT_TOO_LARGE if the padding is good but the decrypted + * plaintext does not fit in the output buffer. + * - 0 if the padding is correct. */ + ret = mbedtls_ct_error_if( + bad, + MBEDTLS_ERR_RSA_INVALID_PADDING, + mbedtls_ct_error_if_else_0(output_too_large, MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE) + ); + + /* If the padding is bad or the plaintext is too large, zero the + * data that we're about to copy to the output buffer. + * We need to copy the same amount of data + * from the same buffer whether the padding is good or not to + * avoid leaking the padding validity through overall timing or + * through memory or cache access patterns. */ + mbedtls_ct_zeroize_if(mbedtls_ct_bool_or(bad, output_too_large), input + 11, ilen - 11); + + /* If the plaintext is too large, truncate it to the buffer size. + * Copy anyway to avoid revealing the length through timing, because + * revealing the length is as bad as revealing the padding validity + * for a Bleichenbacher attack. */ + plaintext_size = mbedtls_ct_uint_if(output_too_large, + (unsigned) plaintext_max_size, + (unsigned) plaintext_size); + + /* Move the plaintext to the leftmost position where it can start in + * the working buffer, i.e. make it start plaintext_max_size from + * the end of the buffer. Do this with a memory access trace that + * does not depend on the plaintext size. After this move, the + * starting location of the plaintext is no longer sensitive + * information. */ + mbedtls_ct_memmove_left(input + ilen - plaintext_max_size, + plaintext_max_size, + plaintext_max_size - plaintext_size); + + /* Finally copy the decrypted plaintext plus trailing zeros into the output + * buffer. If output_max_len is 0, then output may be an invalid pointer + * and the result of memcpy() would be undefined; prevent undefined + * behavior making sure to depend only on output_max_len (the size of the + * user-provided output buffer), which is independent from plaintext + * length, validity of padding, success of the decryption, and other + * secrets. */ + if (output_max_len != 0) { + memcpy(output, input + ilen - plaintext_max_size, plaintext_max_size); + } + + /* Report the amount of data we copied to the output buffer. In case + * of errors (bad padding or output too large), the value of *olen + * when this function returns is not specified. Making it equivalent + * to the good case limits the risks of leaking the padding validity. */ + *olen = plaintext_size; + + return ret; +} + +#endif /* MBEDTLS_PKCS1_V15 && MBEDTLS_RSA_C && ! MBEDTLS_RSA_ALT */ + +#if defined(MBEDTLS_RSA_ALT) int mbedtls_rsa_import(mbedtls_rsa_context *ctx, const mbedtls_mpi *N, @@ -509,7 +653,7 @@ int mbedtls_rsa_set_padding(mbedtls_rsa_context *ctx, int padding, if ((padding == MBEDTLS_RSA_PKCS_V21) && (hash_id != MBEDTLS_MD_NONE)) { /* Just make sure this hash is supported in this build. */ - if (mbedtls_hash_info_psa_from_md(hash_id) == PSA_ALG_NONE) { + if (mbedtls_md_info_from_type(hash_id) == NULL) { return MBEDTLS_ERR_RSA_INVALID_PADDING; } } @@ -576,7 +720,12 @@ int mbedtls_rsa_gen_key(mbedtls_rsa_context *ctx, mbedtls_mpi_init(&G); mbedtls_mpi_init(&L); - if (nbits < 128 || exponent < 3 || nbits % 2 != 0) { + if (exponent < 3 || nbits % 2 != 0) { + ret = MBEDTLS_ERR_RSA_BAD_INPUT_DATA; + goto cleanup; + } + + if (nbits < MBEDTLS_RSA_GEN_KEY_MIN_BITS) { ret = MBEDTLS_ERR_RSA_BAD_INPUT_DATA; goto cleanup; } @@ -1108,8 +1257,7 @@ static int mgf_mask(unsigned char *dst, size_t dlen, unsigned char *src, unsigned char *p; unsigned int hlen; size_t i, use_len; - unsigned char mask[MBEDTLS_HASH_MAX_SIZE]; -#if defined(MBEDTLS_MD_C) + unsigned char mask[MBEDTLS_MD_MAX_SIZE]; int ret = 0; const mbedtls_md_info_t *md_info; mbedtls_md_context_t md_ctx; @@ -1126,14 +1274,6 @@ static int mgf_mask(unsigned char *dst, size_t dlen, unsigned char *src, } hlen = mbedtls_md_get_size(md_info); -#else - psa_hash_operation_t op = PSA_HASH_OPERATION_INIT; - psa_algorithm_t alg = mbedtls_psa_translate_md(md_alg); - psa_status_t status = PSA_SUCCESS; - size_t out_len; - - hlen = PSA_HASH_LENGTH(alg); -#endif memset(mask, 0, sizeof(mask)); memset(counter, 0, 4); @@ -1147,7 +1287,6 @@ static int mgf_mask(unsigned char *dst, size_t dlen, unsigned char *src, use_len = dlen; } -#if defined(MBEDTLS_MD_C) if ((ret = mbedtls_md_starts(&md_ctx)) != 0) { goto exit; } @@ -1160,21 +1299,6 @@ static int mgf_mask(unsigned char *dst, size_t dlen, unsigned char *src, if ((ret = mbedtls_md_finish(&md_ctx, mask)) != 0) { goto exit; } -#else - if ((status = psa_hash_setup(&op, alg)) != PSA_SUCCESS) { - goto exit; - } - if ((status = psa_hash_update(&op, src, slen)) != PSA_SUCCESS) { - goto exit; - } - if ((status = psa_hash_update(&op, counter, 4)) != PSA_SUCCESS) { - goto exit; - } - status = psa_hash_finish(&op, mask, sizeof(mask), &out_len); - if (status != PSA_SUCCESS) { - goto exit; - } -#endif for (i = 0; i < use_len; ++i) { *p++ ^= mask[i]; @@ -1187,15 +1311,9 @@ static int mgf_mask(unsigned char *dst, size_t dlen, unsigned char *src, exit: mbedtls_platform_zeroize(mask, sizeof(mask)); -#if defined(MBEDTLS_MD_C) mbedtls_md_free(&md_ctx); return ret; -#else - psa_hash_abort(&op); - - return PSA_TO_MBEDTLS_ERR(status); -#endif } /** @@ -1214,7 +1332,6 @@ static int hash_mprime(const unsigned char *hash, size_t hlen, { const unsigned char zeros[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; -#if defined(MBEDTLS_MD_C) mbedtls_md_context_t md_ctx; int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; @@ -1247,35 +1364,6 @@ static int hash_mprime(const unsigned char *hash, size_t hlen, mbedtls_md_free(&md_ctx); return ret; -#else - psa_hash_operation_t op = PSA_HASH_OPERATION_INIT; - psa_algorithm_t alg = mbedtls_psa_translate_md(md_alg); - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - size_t out_size = PSA_HASH_LENGTH(alg); - size_t out_len; - - if ((status = psa_hash_setup(&op, alg)) != PSA_SUCCESS) { - goto exit; - } - if ((status = psa_hash_update(&op, zeros, sizeof(zeros))) != PSA_SUCCESS) { - goto exit; - } - if ((status = psa_hash_update(&op, hash, hlen)) != PSA_SUCCESS) { - goto exit; - } - if ((status = psa_hash_update(&op, salt, slen)) != PSA_SUCCESS) { - goto exit; - } - status = psa_hash_finish(&op, out, out_size, &out_len); - if (status != PSA_SUCCESS) { - goto exit; - } - -exit: - psa_hash_abort(&op); - - return PSA_TO_MBEDTLS_ERR(status); -#endif /* !MBEDTLS_MD_C */ } /** @@ -1290,7 +1378,6 @@ static int compute_hash(mbedtls_md_type_t md_alg, const unsigned char *input, size_t ilen, unsigned char *output) { -#if defined(MBEDTLS_MD_C) const mbedtls_md_info_t *md_info; md_info = mbedtls_md_info_from_type(md_alg); @@ -1299,16 +1386,6 @@ static int compute_hash(mbedtls_md_type_t md_alg, } return mbedtls_md(md_info, input, ilen, output); -#else - psa_algorithm_t alg = mbedtls_psa_translate_md(md_alg); - psa_status_t status; - size_t out_size = PSA_HASH_LENGTH(alg); - size_t out_len; - - status = psa_hash_compute(alg, input, ilen, output, out_size, &out_len); - - return PSA_TO_MBEDTLS_ERR(status); -#endif /* !MBEDTLS_MD_C */ } #endif /* MBEDTLS_PKCS1_V21 */ @@ -1333,7 +1410,7 @@ int mbedtls_rsa_rsaes_oaep_encrypt(mbedtls_rsa_context *ctx, return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } - hlen = mbedtls_hash_info_get_size((mbedtls_md_type_t) ctx->hash_id); + hlen = mbedtls_md_get_size_from_type((mbedtls_md_type_t) ctx->hash_id); if (hlen == 0) { return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } @@ -1376,7 +1453,7 @@ int mbedtls_rsa_rsaes_oaep_encrypt(mbedtls_rsa_context *ctx, /* maskedSeed: Apply seedMask to seed */ if ((ret = mgf_mask(output + 1, hlen, output + hlen + 1, olen - hlen - 1, - (mbedtls_md_type_t)ctx->hash_id)) != 0) { + (mbedtls_md_type_t) ctx->hash_id)) != 0) { return ret; } @@ -1482,9 +1559,10 @@ int mbedtls_rsa_rsaes_oaep_decrypt(mbedtls_rsa_context *ctx, { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t ilen, i, pad_len; - unsigned char *p, bad, pad_done; + unsigned char *p; + mbedtls_ct_condition_t bad, in_padding; unsigned char buf[MBEDTLS_MPI_MAX_SIZE]; - unsigned char lhash[MBEDTLS_HASH_MAX_SIZE]; + unsigned char lhash[MBEDTLS_MD_MAX_SIZE]; unsigned int hlen; /* @@ -1500,7 +1578,7 @@ int mbedtls_rsa_rsaes_oaep_decrypt(mbedtls_rsa_context *ctx, return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } - hlen = mbedtls_hash_info_get_size((mbedtls_md_type_t) ctx->hash_id); + hlen = mbedtls_md_get_size_from_type((mbedtls_md_type_t) ctx->hash_id); if (hlen == 0) { return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } @@ -1542,28 +1620,26 @@ int mbedtls_rsa_rsaes_oaep_decrypt(mbedtls_rsa_context *ctx, * Check contents, in "constant-time" */ p = buf; - bad = 0; - - bad |= *p++; /* First byte must be 0 */ + + bad = mbedtls_ct_bool(*p++); /* First byte must be 0 */ p += hlen; /* Skip seed */ /* Check lHash */ - for (i = 0; i < hlen; i++) { - bad |= lhash[i] ^ *p++; - } + bad = mbedtls_ct_bool_or(bad, mbedtls_ct_bool(mbedtls_ct_memcmp(lhash, p, hlen))); + p += hlen; /* Get zero-padding len, but always read till end of buffer * (minus one, for the 01 byte) */ pad_len = 0; - pad_done = 0; + in_padding = MBEDTLS_CT_TRUE; for (i = 0; i < ilen - 2 * hlen - 2; i++) { - pad_done |= p[i]; - pad_len += ((pad_done | (unsigned char) -pad_done) >> 7) ^ 1; + in_padding = mbedtls_ct_bool_and(in_padding, mbedtls_ct_uint_eq(p[i], 0)); + pad_len += mbedtls_ct_uint_if_else_0(in_padding, 1); } p += pad_len; - bad |= *p++ ^ 0x01; + bad = mbedtls_ct_bool_or(bad, mbedtls_ct_uint_ne(*p++, 0x01)); /* * The only information "leaked" is whether the padding was correct or not @@ -1571,7 +1647,7 @@ int mbedtls_rsa_rsaes_oaep_decrypt(mbedtls_rsa_context *ctx, * recommendations in PKCS#1 v2.2: an opponent cannot distinguish between * the different error conditions. */ - if (bad != 0) { + if (bad != MBEDTLS_CT_FALSE) { ret = MBEDTLS_ERR_RSA_INVALID_PADDING; goto cleanup; } @@ -1700,7 +1776,7 @@ static int rsa_rsassa_pss_sign(mbedtls_rsa_context *ctx, if (md_alg != MBEDTLS_MD_NONE) { /* Gather length of hash to sign */ - size_t exp_hashlen = mbedtls_hash_info_get_size(md_alg); + size_t exp_hashlen = mbedtls_md_get_size_from_type(md_alg); if (exp_hashlen == 0) { return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } @@ -1710,7 +1786,7 @@ static int rsa_rsassa_pss_sign(mbedtls_rsa_context *ctx, } } - hlen = mbedtls_hash_info_get_size((mbedtls_md_type_t) ctx->hash_id); + hlen = mbedtls_md_get_size_from_type((mbedtls_md_type_t) ctx->hash_id); if (hlen == 0) { return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } @@ -1848,7 +1924,7 @@ static int rsa_rsassa_pkcs1_v15_encode(mbedtls_md_type_t md_alg, /* Are we signing hashed or raw data? */ if (md_alg != MBEDTLS_MD_NONE) { - unsigned char md_size = mbedtls_hash_info_get_size(md_alg); + unsigned char md_size = mbedtls_md_get_size_from_type(md_alg); if (md_size == 0) { return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } @@ -2009,11 +2085,9 @@ int mbedtls_rsa_rsassa_pkcs1_v15_sign(mbedtls_rsa_context *ctx, memcpy(sig, sig_try, ctx->len); cleanup: - mbedtls_platform_zeroize(sig_try, ctx->len); - mbedtls_platform_zeroize(verif, ctx->len); - mbedtls_free(sig_try); - mbedtls_free(verif); - + mbedtls_zeroize_and_free(sig_try, ctx->len); + mbedtls_zeroize_and_free(verif, ctx->len); + if (ret != 0) { memset(sig, '!', ctx->len); } @@ -2070,7 +2144,7 @@ int mbedtls_rsa_rsassa_pss_verify_ext(mbedtls_rsa_context *ctx, size_t siglen; unsigned char *p; unsigned char *hash_start; - unsigned char result[MBEDTLS_HASH_MAX_SIZE]; + unsigned char result[MBEDTLS_MD_MAX_SIZE]; unsigned int hlen; size_t observed_salt_len, msb; unsigned char buf[MBEDTLS_MPI_MAX_SIZE] = { 0 }; @@ -2099,7 +2173,7 @@ int mbedtls_rsa_rsassa_pss_verify_ext(mbedtls_rsa_context *ctx, if (md_alg != MBEDTLS_MD_NONE) { /* Gather length of hash to sign */ - size_t exp_hashlen = mbedtls_hash_info_get_size(md_alg); + size_t exp_hashlen = mbedtls_md_get_size_from_type(md_alg); if (exp_hashlen == 0) { return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } @@ -2109,7 +2183,7 @@ int mbedtls_rsa_rsassa_pss_verify_ext(mbedtls_rsa_context *ctx, } } - hlen = mbedtls_hash_info_get_size(mgf1_hash_id); + hlen = mbedtls_md_get_size_from_type(mgf1_hash_id); if (hlen == 0) { return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } @@ -2256,14 +2330,12 @@ int mbedtls_rsa_rsassa_pkcs1_v15_verify(mbedtls_rsa_context *ctx, cleanup: if (encoded != NULL) { - mbedtls_platform_zeroize(encoded, sig_len); - mbedtls_free(encoded); - } + mbedtls_zeroize_and_free(encoded, sig_len); + } if (encoded_expected != NULL) { - mbedtls_platform_zeroize(encoded_expected, sig_len); - mbedtls_free(encoded_expected); - } + mbedtls_zeroize_and_free(encoded_expected, sig_len); + } return ret; } @@ -2455,7 +2527,7 @@ int mbedtls_rsa_self_test(int verbose) unsigned char rsa_plaintext[PT_LEN]; unsigned char rsa_decrypted[PT_LEN]; unsigned char rsa_ciphertext[KEY_LEN]; -#if defined(MBEDTLS_SHA1_C) +#if defined(MBEDTLS_MD_CAN_SHA1) unsigned char sha1sum[20]; #endif @@ -2536,7 +2608,7 @@ int mbedtls_rsa_self_test(int verbose) mbedtls_printf("passed\n"); } -#if defined(MBEDTLS_SHA1_C) +#if defined(MBEDTLS_MD_CAN_SHA1) if (verbose != 0) { mbedtls_printf(" PKCS#1 data sign : "); } @@ -2578,7 +2650,7 @@ int mbedtls_rsa_self_test(int verbose) if (verbose != 0) { mbedtls_printf("passed\n"); } -#endif /* MBEDTLS_SHA1_C */ +#endif /* MBEDTLS_MD_CAN_SHA1 */ if (verbose != 0) { mbedtls_printf("\n"); diff --git a/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c b/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c index bf4ff0a3f..7302b628b 100644 --- a/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c @@ -749,7 +749,7 @@ int mbedtls_rsa_public (mbedtls_rsa_context * ctx, const unsigned char * input, if (ctx->N.n != (ctx->len / (sizeof(mbedtls_mpi_uint)))) { /* There should be only 1 extra value (00) at the beginning; otherwise the key is in an unexpected format */ - if ((ctx->N.n - 1) != (ctx->len / (sizeof(mbedtls_mpi_uint)))) + if ((ctx->N.n - 1) != (int)(ctx->len / (sizeof(mbedtls_mpi_uint)))) { return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } @@ -815,7 +815,7 @@ int mbedtls_rsa_private (mbedtls_rsa_context * ctx, if (ctx->N.n != (ctx->len / (sizeof(mbedtls_mpi_uint)))) { /* There should be only 1 extra value (00) at the beginning; otherwise the key is in an unexpected format */ - if ((ctx->N.n - 1) != (ctx->len / (sizeof(mbedtls_mpi_uint)))) + if ((ctx->N.n - 1) != (int)(ctx->len / (sizeof(mbedtls_mpi_uint)))) { return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } diff --git a/ra/fsp/src/rm_psa_crypto/sha256_alt.c b/ra/fsp/src/rm_psa_crypto/sha256_alt.c index 4e54fa23d..05de3899d 100644 --- a/ra/fsp/src/rm_psa_crypto/sha256_alt.c +++ b/ra/fsp/src/rm_psa_crypto/sha256_alt.c @@ -21,7 +21,6 @@ * * This file is part of mbed TLS (https://tls.mbed.org) */ - /* * The SHA-256 Secure Hash Standard was published by NIST in 2002. * @@ -65,11 +64,26 @@ #include "mbedtls/platform.h" #if defined(__aarch64__) + # if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) || \ defined(MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY) + /* *INDENT-OFF* */ + +# ifdef __ARM_NEON +# include +# else +# error "Target does not support NEON instructions" +# endif + # if !defined(__ARM_FEATURE_CRYPTO) || defined(MBEDTLS_ENABLE_ARM_CRYPTO_EXTENSIONS_COMPILER_FLAG) -# if defined(__clang__) +# if defined(__ARMCOMPILER_VERSION) +# if __ARMCOMPILER_VERSION <= 6090000 +# error "Must use minimum -march=armv8-a+crypto for MBEDTLS_SHA256_USE_A64_CRYPTO_*" +# endif +# pragma clang attribute push (__attribute__((target("sha2"))), apply_to=function) +# define MBEDTLS_POP_TARGET_PRAGMA +# elif defined(__clang__) # if __clang_major__ < 4 # error "A more recent Clang is required for MBEDTLS_SHA256_USE_A64_CRYPTO_*" # endif @@ -91,7 +105,7 @@ # endif # endif /* *INDENT-ON* */ -# include + # endif # if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) # if defined(__unix__) @@ -457,6 +471,8 @@ int mbedtls_internal_sha256_process_a64_crypto(mbedtls_sha256_context *ctx, SHA256_BLOCK_SIZE) ? 0 : -1; } +#endif /* MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT || MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY */ + #if defined(MBEDTLS_POP_TARGET_PRAGMA) #if defined(__clang__) #pragma clang attribute pop @@ -466,8 +482,6 @@ int mbedtls_internal_sha256_process_a64_crypto(mbedtls_sha256_context *ctx, #undef MBEDTLS_POP_TARGET_PRAGMA #endif -#endif /* MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT || MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY */ - #if !defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) #define mbedtls_internal_sha256_process_many_c mbedtls_internal_sha256_process_many #define mbedtls_internal_sha256_process_c mbedtls_internal_sha256_process @@ -817,8 +831,9 @@ int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; uint32_t used; + int truncated = 0; - /* + /* * Add padding: 0x80 then 0x00 until 8 bytes remain for the length */ used = ctx->total[0] & 0x3F; @@ -840,7 +855,7 @@ int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, } if( ( ret = mbedtls_internal_sha256_process_ext(ctx, ctx->rsip_buffer, SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES ) ) != 0) { - return ret; + goto exit; } ctx->rsip_buffer_processed = 1U; ctx->use_rsip_buffer = 0U; @@ -851,7 +866,7 @@ int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, ctx->sce_operation_state = SCE_OEM_CMD_HASH_ONESHOT; if( ( ret = mbedtls_internal_sha256_process_ext(ctx, ctx->rsip_buffer, 0 ) ) != 0) { - return ret; + goto exit; } } } @@ -865,7 +880,7 @@ int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, } if( ( ret = mbedtls_internal_sha256_process_ext(ctx, ctx->rsip_buffer, SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES ) ) != 0) { - return ret; + goto exit; } ctx->rsip_buffer_processed = 1U; ctx->use_rsip_buffer = 0U; @@ -880,7 +895,7 @@ int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, } if((ret = mbedtls_internal_sha256_process_ext(ctx, ctx->buffer, used)) != 0) { - return ret; + goto exit; } } @@ -897,7 +912,7 @@ int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, memset(ctx->buffer + used, 0, SHA256_BLOCK_SIZE - used); if((ret = mbedtls_internal_sha256_process_ext(ctx, ctx->buffer, SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES)) != 0) { - return ret; + goto exit; } memset(ctx->buffer, 0, 56); @@ -917,7 +932,7 @@ int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, ctx->sce_operation_state = SCE_OEM_CMD_HASH_RESUME_TO_FINAL; if( ( ret = mbedtls_internal_sha256_process_ext( ctx, ctx->buffer, SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES ) ) != 0) { - return ret; + goto exit; } #endif @@ -933,7 +948,6 @@ int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, MBEDTLS_PUT_UINT32_LE(ctx->state[5], output, 20); MBEDTLS_PUT_UINT32_LE(ctx->state[6], output, 24); - int truncated = 0; #if defined(MBEDTLS_SHA224_C) truncated = ctx->is224; #endif @@ -941,7 +955,11 @@ int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, MBEDTLS_PUT_UINT32_LE(ctx->state[7], output, 28); } - return 0; + ret = 0; + +exit: + mbedtls_sha256_free(ctx); + return ret; } #endif /* !MBEDTLS_SHA256_ALT */ diff --git a/ra/fsp/src/rm_psa_crypto/sha512_alt.c b/ra/fsp/src/rm_psa_crypto/sha512_alt.c index f2e537343..ee032c98d 100644 --- a/ra/fsp/src/rm_psa_crypto/sha512_alt.c +++ b/ra/fsp/src/rm_psa_crypto/sha512_alt.c @@ -16,7 +16,6 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - /* * The SHA-512 Secure Hash Standard was published by NIST in 2002. * @@ -25,7 +24,6 @@ #if defined(__aarch64__) && !defined(__ARM_FEATURE_SHA512) && \ defined(__clang__) && __clang_major__ >= 7 - /* TODO: Re-consider above after https://reviews.llvm.org/D131064 merged. * * The intrinsic declaration are guarded by predefined ACLE macros in clang: @@ -61,9 +59,12 @@ #if defined(__aarch64__) #if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) || \ defined(MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY) - /* *INDENT-OFF* */ - +# ifdef __ARM_NEON +# include +# else +# error "Target does not support NEON instructions" +# endif /* * Best performance comes from most recent compilers, with intrinsics and -O3. * Must compile with -march=armv8.2-a+sha3, but we can't detect armv8.2-a, and @@ -81,79 +82,80 @@ #if !defined(__ARM_FEATURE_SHA512) || defined(MBEDTLS_ENABLE_ARM_SHA3_EXTENSIONS_COMPILER_FLAG) /* Test Clang first, as it defines __GNUC__ */ - #if defined(__clang__) - #if __clang_major__ < 7 - #error "A more recent Clang is required for MBEDTLS_SHA512_USE_A64_CRYPTO_*" - #else - #pragma clang attribute push (__attribute__((target("sha3"))), apply_to=function) - #define MBEDTLS_POP_TARGET_PRAGMA - #endif - #elif defined(__GNUC__) - #if __GNUC__ < 8 - #error "A more recent GCC is required for MBEDTLS_SHA512_USE_A64_CRYPTO_*" - #else - #pragma GCC push_options - #pragma GCC target ("arch=armv8.2-a+sha3") - #define MBEDTLS_POP_TARGET_PRAGMA - #endif - #else - #error "Only GCC and Clang supported for MBEDTLS_SHA512_USE_A64_CRYPTO_*" - #endif - #endif - + # if defined(__ARMCOMPILER_VERSION) +# if __ARMCOMPILER_VERSION < 6090000 +# error "A more recent armclang is required for MBEDTLS_SHA512_USE_A64_CRYPTO_*" +# elif __ARMCOMPILER_VERSION == 6090000 +# error "Must use minimum -march=armv8.2-a+sha3 for MBEDTLS_SHA512_USE_A64_CRYPTO_*" +# else +# pragma clang attribute push (__attribute__((target("sha3"))), apply_to=function) +# define MBEDTLS_POP_TARGET_PRAGMA +# endif +# elif defined(__clang__) +# if __clang_major__ < 7 + # error "A more recent Clang is required for MBEDTLS_SHA512_USE_A64_CRYPTO_*" + # else + # pragma clang attribute push (__attribute__((target("sha3"))), apply_to=function) + # define MBEDTLS_POP_TARGET_PRAGMA + # endif + # elif defined(__GNUC__) + # if __GNUC__ < 8 + # error "A more recent GCC is required for MBEDTLS_SHA512_USE_A64_CRYPTO_*" + # else + # pragma GCC push_options + # pragma GCC target ("arch=armv8.2-a+sha3") + # define MBEDTLS_POP_TARGET_PRAGMA + # endif + # else + # error "Only GCC and Clang supported for MBEDTLS_SHA512_USE_A64_CRYPTO_*" + # endif + # endif /* *INDENT-ON* */ - #include - #endif - #if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) - #if defined(__unix__) - #if defined(__linux__) - + # endif + # if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) + # if defined(__unix__) + # if defined(__linux__) /* Our preferred method of detection is getauxval() */ - #include - #endif - + # include + # endif /* Use SIGILL on Unix, and fall back to it on Linux */ - #include - #endif - #endif + # include + # endif + # endif #elif defined(_M_ARM64) - #if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) || \ + # if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) || \ defined(MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY) - #include - #endif + # include + # endif #else - #undef MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY - #undef MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT + # undef MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY + # undef MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT #endif #if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) - /* * Capability detection code comes early, so we can disable * MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT if no detection mechanism found */ #if defined(HWCAP_SHA512) -static int mbedtls_a64_crypto_sha512_determine_support (void) +static int mbedtls_a64_crypto_sha512_determine_support(void) { return (getauxval(AT_HWCAP) & HWCAP_SHA512) ? 1 : 0; } - #elif defined(__APPLE__) #include #include -static int mbedtls_a64_crypto_sha512_determine_support (void) +static int mbedtls_a64_crypto_sha512_determine_support(void) { - int value = 0; + int value = 0; size_t value_len = sizeof(value); - int ret = sysctlbyname("hw.optional.armv8_2_sha512", &value, &value_len, NULL, 0); - + int ret = sysctlbyname("hw.optional.armv8_2_sha512", &value, &value_len, + NULL, 0); return ret == 0 && value != 0; } - #elif defined(_M_ARM64) - /* * As of March 2022, there don't appear to be any PF_ARM_V8_* flags * available to pass to IsProcessorFeaturePresent() to check for @@ -165,7 +167,6 @@ static int mbedtls_a64_crypto_sha512_determine_support (void) #warning "No mechanism to detect A64_CRYPTO found, using C code only" #endif #elif defined(__unix__) && defined(SIG_SETMASK) - /* Detection with SIGILL, setjmp() and longjmp() */ #include #include @@ -175,33 +176,31 @@ static jmp_buf return_from_sigill; /* * A64 SHA512 support detection via SIGILL */ -static void sigill_handler (int signal) +static void sigill_handler(int signal) { (void) signal; longjmp(return_from_sigill, 1); } -static int mbedtls_a64_crypto_sha512_determine_support (void) +static int mbedtls_a64_crypto_sha512_determine_support(void) { struct sigaction old_action, new_action; sigset_t old_mask; - if (sigprocmask(0, NULL, &old_mask)) - { + if (sigprocmask(0, NULL, &old_mask)) { return 0; } sigemptyset(&new_action.sa_mask); - new_action.sa_flags = 0; + new_action.sa_flags = 0; new_action.sa_handler = sigill_handler; sigaction(SIGILL, &new_action, &old_action); static int ret = 0; - if (setjmp(return_from_sigill) == 0) /* First return only */ - { - /* If this traps, we will return a second time from setjmp() with 1 */ + if (setjmp(return_from_sigill) == 0) { /* First return only */ + /* If this traps, we will return a second time from setjmp() with 1 */ asm ("sha512h q0, q0, v0.2d" : : : "v0"); ret = 1; } @@ -211,44 +210,42 @@ static int mbedtls_a64_crypto_sha512_determine_support (void) return ret; } - #else #warning "No mechanism to detect A64_CRYPTO found, using C code only" #undef MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT - #endif /* HWCAP_SHA512, __APPLE__, __unix__ && SIG_SETMASK */ + #endif /* HWCAP_SHA512, __APPLE__, __unix__ && SIG_SETMASK */ - #endif /* MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT */ + #endif /* MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT */ #if defined(MBEDTLS_SHA512_ALT) - #define SHA512_BLOCK_SIZE 128 + #define SHA512_BLOCK_SIZE 128 #if defined(MBEDTLS_SHA512_SMALLER) -static void sha512_put_uint64_be (uint64_t n, unsigned char * b, uint8_t i) +static void sha512_put_uint64_be(uint64_t n, unsigned char *b, uint8_t i) { MBEDTLS_PUT_UINT64_BE(n, b, i); } - #else #define sha512_put_uint64_be MBEDTLS_PUT_UINT64_BE - #endif /* MBEDTLS_SHA512_SMALLER */ + #endif /* MBEDTLS_SHA512_SMALLER */ -void mbedtls_sha512_init (mbedtls_sha512_context * ctx) +void mbedtls_sha512_init(mbedtls_sha512_context *ctx) { memset(ctx, 0, sizeof(mbedtls_sha512_context)); } -void mbedtls_sha512_free (mbedtls_sha512_context * ctx) +void mbedtls_sha512_free(mbedtls_sha512_context *ctx) { - if (ctx == NULL) - { + if (ctx == NULL) { return; } mbedtls_platform_zeroize(ctx, sizeof(mbedtls_sha512_context)); } -void mbedtls_sha512_clone (mbedtls_sha512_context * dst, const mbedtls_sha512_context * src) +void mbedtls_sha512_clone(mbedtls_sha512_context *dst, + const mbedtls_sha512_context *src) { *dst = *src; } @@ -256,23 +253,18 @@ void mbedtls_sha512_clone (mbedtls_sha512_context * dst, const mbedtls_sha512_co /* * SHA-512 context setup */ -int mbedtls_sha512_starts (mbedtls_sha512_context * ctx, int is384) +int mbedtls_sha512_starts(mbedtls_sha512_context *ctx, int is384) { #if defined(MBEDTLS_SHA384_C) && defined(MBEDTLS_SHA512_C) - if ((is384 != 0) && (is384 != 1)) - { + if (is384 != 0 && is384 != 1) { return MBEDTLS_ERR_SHA512_BAD_INPUT_DATA; } - #elif defined(MBEDTLS_SHA512_C) - if (is384 != 0) - { + if (is384 != 0) { return MBEDTLS_ERR_SHA512_BAD_INPUT_DATA; } - - #else /* defined MBEDTLS_SHA384_C only */ - if (is384 == 0) - { +#else /* defined MBEDTLS_SHA384_C only */ + if (is384 == 0) { return MBEDTLS_ERR_SHA512_BAD_INPUT_DATA; } #endif @@ -280,8 +272,7 @@ int mbedtls_sha512_starts (mbedtls_sha512_context * ctx, int is384) ctx->total[0] = 0; ctx->total[1] = 0; - if (is384 == 0) - { + if (is384 == 0) { #if defined(MBEDTLS_SHA512_C) ctx->state[0] = UL64(0x6A09E667F3BCC908); ctx->state[1] = UL64(0xBB67AE8584CAA73B); @@ -291,10 +282,8 @@ int mbedtls_sha512_starts (mbedtls_sha512_context * ctx, int is384) ctx->state[5] = UL64(0x9B05688C2B3E6C1F); ctx->state[6] = UL64(0x1F83D9ABFB41BD6B); ctx->state[7] = UL64(0x5BE0CD19137E2179); - #endif /* MBEDTLS_SHA512_C */ - } - else - { + #endif /* MBEDTLS_SHA512_C */ + } else { #if defined(MBEDTLS_SHA384_C) ctx->state[0] = UL64(0xCBBB9D5DC1059ED8); ctx->state[1] = UL64(0x629A292A367CD507); @@ -304,7 +293,7 @@ int mbedtls_sha512_starts (mbedtls_sha512_context * ctx, int is384) ctx->state[5] = UL64(0x8EB44A8768581511); ctx->state[6] = UL64(0xDB0C2E0D64F98FA7); ctx->state[7] = UL64(0x47B5481DBEFA4FA4); - #endif /* MBEDTLS_SHA384_C */ + #endif /* MBEDTLS_SHA384_C */ } #if defined(MBEDTLS_SHA384_C) @@ -322,46 +311,46 @@ int mbedtls_sha512_starts (mbedtls_sha512_context * ctx, int is384) */ static const uint64_t K[80] = { - UL64(0x428A2F98D728AE22), UL64(0x7137449123EF65CD), - UL64(0xB5C0FBCFEC4D3B2F), UL64(0xE9B5DBA58189DBBC), - UL64(0x3956C25BF348B538), UL64(0x59F111F1B605D019), - UL64(0x923F82A4AF194F9B), UL64(0xAB1C5ED5DA6D8118), - UL64(0xD807AA98A3030242), UL64(0x12835B0145706FBE), - UL64(0x243185BE4EE4B28C), UL64(0x550C7DC3D5FFB4E2), - UL64(0x72BE5D74F27B896F), UL64(0x80DEB1FE3B1696B1), - UL64(0x9BDC06A725C71235), UL64(0xC19BF174CF692694), - UL64(0xE49B69C19EF14AD2), UL64(0xEFBE4786384F25E3), - UL64(0x0FC19DC68B8CD5B5), UL64(0x240CA1CC77AC9C65), - UL64(0x2DE92C6F592B0275), UL64(0x4A7484AA6EA6E483), - UL64(0x5CB0A9DCBD41FBD4), UL64(0x76F988DA831153B5), - UL64(0x983E5152EE66DFAB), UL64(0xA831C66D2DB43210), - UL64(0xB00327C898FB213F), UL64(0xBF597FC7BEEF0EE4), - UL64(0xC6E00BF33DA88FC2), UL64(0xD5A79147930AA725), - UL64(0x06CA6351E003826F), UL64(0x142929670A0E6E70), - UL64(0x27B70A8546D22FFC), UL64(0x2E1B21385C26C926), - UL64(0x4D2C6DFC5AC42AED), UL64(0x53380D139D95B3DF), - UL64(0x650A73548BAF63DE), UL64(0x766A0ABB3C77B2A8), - UL64(0x81C2C92E47EDAEE6), UL64(0x92722C851482353B), - UL64(0xA2BFE8A14CF10364), UL64(0xA81A664BBC423001), - UL64(0xC24B8B70D0F89791), UL64(0xC76C51A30654BE30), - UL64(0xD192E819D6EF5218), UL64(0xD69906245565A910), - UL64(0xF40E35855771202A), UL64(0x106AA07032BBD1B8), - UL64(0x19A4C116B8D2D0C8), UL64(0x1E376C085141AB53), - UL64(0x2748774CDF8EEB99), UL64(0x34B0BCB5E19B48A8), - UL64(0x391C0CB3C5C95A63), UL64(0x4ED8AA4AE3418ACB), - UL64(0x5B9CCA4F7763E373), UL64(0x682E6FF3D6B2B8A3), - UL64(0x748F82EE5DEFB2FC), UL64(0x78A5636F43172F60), - UL64(0x84C87814A1F0AB72), UL64(0x8CC702081A6439EC), - UL64(0x90BEFFFA23631E28), UL64(0xA4506CEBDE82BDE9), - UL64(0xBEF9A3F7B2C67915), UL64(0xC67178F2E372532B), - UL64(0xCA273ECEEA26619C), UL64(0xD186B8C721C0C207), - UL64(0xEADA7DD6CDE0EB1E), UL64(0xF57D4F7FEE6ED178), - UL64(0x06F067AA72176FBA), UL64(0x0A637DC5A2C898A6), - UL64(0x113F9804BEF90DAE), UL64(0x1B710B35131C471B), - UL64(0x28DB77F523047D84), UL64(0x32CAAB7B40C72493), - UL64(0x3C9EBE0A15C9BEBC), UL64(0x431D67C49C100D4C), - UL64(0x4CC5D4BECB3E42B6), UL64(0x597F299CFC657E2A), - UL64(0x5FCB6FAB3AD6FAEC), UL64(0x6C44198C4A475817) + UL64(0x428A2F98D728AE22), UL64(0x7137449123EF65CD), + UL64(0xB5C0FBCFEC4D3B2F), UL64(0xE9B5DBA58189DBBC), + UL64(0x3956C25BF348B538), UL64(0x59F111F1B605D019), + UL64(0x923F82A4AF194F9B), UL64(0xAB1C5ED5DA6D8118), + UL64(0xD807AA98A3030242), UL64(0x12835B0145706FBE), + UL64(0x243185BE4EE4B28C), UL64(0x550C7DC3D5FFB4E2), + UL64(0x72BE5D74F27B896F), UL64(0x80DEB1FE3B1696B1), + UL64(0x9BDC06A725C71235), UL64(0xC19BF174CF692694), + UL64(0xE49B69C19EF14AD2), UL64(0xEFBE4786384F25E3), + UL64(0x0FC19DC68B8CD5B5), UL64(0x240CA1CC77AC9C65), + UL64(0x2DE92C6F592B0275), UL64(0x4A7484AA6EA6E483), + UL64(0x5CB0A9DCBD41FBD4), UL64(0x76F988DA831153B5), + UL64(0x983E5152EE66DFAB), UL64(0xA831C66D2DB43210), + UL64(0xB00327C898FB213F), UL64(0xBF597FC7BEEF0EE4), + UL64(0xC6E00BF33DA88FC2), UL64(0xD5A79147930AA725), + UL64(0x06CA6351E003826F), UL64(0x142929670A0E6E70), + UL64(0x27B70A8546D22FFC), UL64(0x2E1B21385C26C926), + UL64(0x4D2C6DFC5AC42AED), UL64(0x53380D139D95B3DF), + UL64(0x650A73548BAF63DE), UL64(0x766A0ABB3C77B2A8), + UL64(0x81C2C92E47EDAEE6), UL64(0x92722C851482353B), + UL64(0xA2BFE8A14CF10364), UL64(0xA81A664BBC423001), + UL64(0xC24B8B70D0F89791), UL64(0xC76C51A30654BE30), + UL64(0xD192E819D6EF5218), UL64(0xD69906245565A910), + UL64(0xF40E35855771202A), UL64(0x106AA07032BBD1B8), + UL64(0x19A4C116B8D2D0C8), UL64(0x1E376C085141AB53), + UL64(0x2748774CDF8EEB99), UL64(0x34B0BCB5E19B48A8), + UL64(0x391C0CB3C5C95A63), UL64(0x4ED8AA4AE3418ACB), + UL64(0x5B9CCA4F7763E373), UL64(0x682E6FF3D6B2B8A3), + UL64(0x748F82EE5DEFB2FC), UL64(0x78A5636F43172F60), + UL64(0x84C87814A1F0AB72), UL64(0x8CC702081A6439EC), + UL64(0x90BEFFFA23631E28), UL64(0xA4506CEBDE82BDE9), + UL64(0xBEF9A3F7B2C67915), UL64(0xC67178F2E372532B), + UL64(0xCA273ECEEA26619C), UL64(0xD186B8C721C0C207), + UL64(0xEADA7DD6CDE0EB1E), UL64(0xF57D4F7FEE6ED178), + UL64(0x06F067AA72176FBA), UL64(0x0A637DC5A2C898A6), + UL64(0x113F9804BEF90DAE), UL64(0x1B710B35131C471B), + UL64(0x28DB77F523047D84), UL64(0x32CAAB7B40C72493), + UL64(0x3C9EBE0A15C9BEBC), UL64(0x431D67C49C100D4C), + UL64(0x4CC5D4BECB3E42B6), UL64(0x597F299CFC657E2A), + UL64(0x5FCB6FAB3AD6FAEC), UL64(0x6C44198C4A475817) }; #endif @@ -369,8 +358,8 @@ static const uint64_t K[80] = defined(MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY) #if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY) - #define mbedtls_internal_sha512_process_many_a64_crypto mbedtls_internal_sha512_process_many - #define mbedtls_internal_sha512_process_a64_crypto mbedtls_internal_sha512_process + # define mbedtls_internal_sha512_process_many_a64_crypto mbedtls_internal_sha512_process_many + # define mbedtls_internal_sha512_process_a64_crypto mbedtls_internal_sha512_process #endif /* Accelerated SHA-512 implementation originally written by Simon Tatham for PuTTY, @@ -380,35 +369,27 @@ static const uint64_t K[80] = #if defined(__clang__) && \ (__clang_major__ < 13 || \ (__clang_major__ == 13 && __clang_minor__ == 0 && __clang_patchlevel__ == 0)) -static inline uint64x2_t vsha512su0q_u64 (uint64x2_t x, uint64x2_t y) +static inline uint64x2_t vsha512su0q_u64(uint64x2_t x, uint64x2_t y) { asm ("sha512su0 %0.2D,%1.2D" : "+w" (x) : "w" (y)); - return x; } - -static inline uint64x2_t vsha512su1q_u64 (uint64x2_t x, uint64x2_t y, uint64x2_t z) +static inline uint64x2_t vsha512su1q_u64(uint64x2_t x, uint64x2_t y, uint64x2_t z) { asm ("sha512su1 %0.2D,%1.2D,%2.2D" : "+w" (x) : "w" (y), "w" (z)); - return x; } - -static inline uint64x2_t vsha512hq_u64 (uint64x2_t x, uint64x2_t y, uint64x2_t z) +static inline uint64x2_t vsha512hq_u64(uint64x2_t x, uint64x2_t y, uint64x2_t z) { asm ("sha512h %0,%1,%2.2D" : "+w" (x) : "w" (y), "w" (z)); - return x; } - -static inline uint64x2_t vsha512h2q_u64 (uint64x2_t x, uint64x2_t y, uint64x2_t z) +static inline uint64x2_t vsha512h2q_u64(uint64x2_t x, uint64x2_t y, uint64x2_t z) { asm ("sha512h2 %0,%1,%2.2D" : "+w" (x) : "w" (y), "w" (z)); - return x; } - - #endif /* __clang__ etc */ +#endif /* __clang__ etc */ static size_t mbedtls_internal_sha512_process_many_a64_crypto (mbedtls_sha512_context * ctx, const uint8_t * msg, @@ -421,12 +402,11 @@ static size_t mbedtls_internal_sha512_process_many_a64_crypto (mbedtls_sha512_co size_t processed = 0; - for ( ; + for (; len >= SHA512_BLOCK_SIZE; processed += SHA512_BLOCK_SIZE, msg += SHA512_BLOCK_SIZE, - len -= SHA512_BLOCK_SIZE) - { + len -= SHA512_BLOCK_SIZE) { uint64x2_t initial_sum, sum, intermed; uint64x2_t ab_orig = ab; @@ -443,7 +423,7 @@ static size_t mbedtls_internal_sha512_process_many_a64_crypto (mbedtls_sha512_co uint64x2_t s6 = (uint64x2_t) vld1q_u8(msg + 16 * 6); uint64x2_t s7 = (uint64x2_t) vld1q_u8(msg + 16 * 7); - #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ /* assume LE if these not defined; untested on BE */ + #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ /* assume LE if these not defined; untested on BE */ s0 = vreinterpretq_u64_u8(vrev64q_u8(vreinterpretq_u8_u64(s0))); s1 = vreinterpretq_u64_u8(vrev64q_u8(vreinterpretq_u8_u64(s1))); s2 = vreinterpretq_u64_u8(vrev64q_u8(vreinterpretq_u8_u64(s2))); @@ -456,125 +436,124 @@ static size_t mbedtls_internal_sha512_process_many_a64_crypto (mbedtls_sha512_co /* Rounds 0 and 1 */ initial_sum = vaddq_u64(s0, vld1q_u64(&K[0])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), gh); - intermed = vsha512hq_u64(sum, vextq_u64(ef, gh, 1), vextq_u64(cd, ef, 1)); - gh = vsha512h2q_u64(intermed, cd, ab); - cd = vaddq_u64(cd, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), gh); + intermed = vsha512hq_u64(sum, vextq_u64(ef, gh, 1), vextq_u64(cd, ef, 1)); + gh = vsha512h2q_u64(intermed, cd, ab); + cd = vaddq_u64(cd, intermed); /* Rounds 2 and 3 */ initial_sum = vaddq_u64(s1, vld1q_u64(&K[2])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ef); - intermed = vsha512hq_u64(sum, vextq_u64(cd, ef, 1), vextq_u64(ab, cd, 1)); - ef = vsha512h2q_u64(intermed, ab, gh); - ab = vaddq_u64(ab, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ef); + intermed = vsha512hq_u64(sum, vextq_u64(cd, ef, 1), vextq_u64(ab, cd, 1)); + ef = vsha512h2q_u64(intermed, ab, gh); + ab = vaddq_u64(ab, intermed); /* Rounds 4 and 5 */ initial_sum = vaddq_u64(s2, vld1q_u64(&K[4])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), cd); - intermed = vsha512hq_u64(sum, vextq_u64(ab, cd, 1), vextq_u64(gh, ab, 1)); - cd = vsha512h2q_u64(intermed, gh, ef); - gh = vaddq_u64(gh, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), cd); + intermed = vsha512hq_u64(sum, vextq_u64(ab, cd, 1), vextq_u64(gh, ab, 1)); + cd = vsha512h2q_u64(intermed, gh, ef); + gh = vaddq_u64(gh, intermed); /* Rounds 6 and 7 */ initial_sum = vaddq_u64(s3, vld1q_u64(&K[6])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ab); - intermed = vsha512hq_u64(sum, vextq_u64(gh, ab, 1), vextq_u64(ef, gh, 1)); - ab = vsha512h2q_u64(intermed, ef, cd); - ef = vaddq_u64(ef, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ab); + intermed = vsha512hq_u64(sum, vextq_u64(gh, ab, 1), vextq_u64(ef, gh, 1)); + ab = vsha512h2q_u64(intermed, ef, cd); + ef = vaddq_u64(ef, intermed); /* Rounds 8 and 9 */ initial_sum = vaddq_u64(s4, vld1q_u64(&K[8])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), gh); - intermed = vsha512hq_u64(sum, vextq_u64(ef, gh, 1), vextq_u64(cd, ef, 1)); - gh = vsha512h2q_u64(intermed, cd, ab); - cd = vaddq_u64(cd, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), gh); + intermed = vsha512hq_u64(sum, vextq_u64(ef, gh, 1), vextq_u64(cd, ef, 1)); + gh = vsha512h2q_u64(intermed, cd, ab); + cd = vaddq_u64(cd, intermed); /* Rounds 10 and 11 */ initial_sum = vaddq_u64(s5, vld1q_u64(&K[10])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ef); - intermed = vsha512hq_u64(sum, vextq_u64(cd, ef, 1), vextq_u64(ab, cd, 1)); - ef = vsha512h2q_u64(intermed, ab, gh); - ab = vaddq_u64(ab, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ef); + intermed = vsha512hq_u64(sum, vextq_u64(cd, ef, 1), vextq_u64(ab, cd, 1)); + ef = vsha512h2q_u64(intermed, ab, gh); + ab = vaddq_u64(ab, intermed); /* Rounds 12 and 13 */ initial_sum = vaddq_u64(s6, vld1q_u64(&K[12])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), cd); - intermed = vsha512hq_u64(sum, vextq_u64(ab, cd, 1), vextq_u64(gh, ab, 1)); - cd = vsha512h2q_u64(intermed, gh, ef); - gh = vaddq_u64(gh, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), cd); + intermed = vsha512hq_u64(sum, vextq_u64(ab, cd, 1), vextq_u64(gh, ab, 1)); + cd = vsha512h2q_u64(intermed, gh, ef); + gh = vaddq_u64(gh, intermed); /* Rounds 14 and 15 */ initial_sum = vaddq_u64(s7, vld1q_u64(&K[14])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ab); - intermed = vsha512hq_u64(sum, vextq_u64(gh, ab, 1), vextq_u64(ef, gh, 1)); - ab = vsha512h2q_u64(intermed, ef, cd); - ef = vaddq_u64(ef, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ab); + intermed = vsha512hq_u64(sum, vextq_u64(gh, ab, 1), vextq_u64(ef, gh, 1)); + ab = vsha512h2q_u64(intermed, ef, cd); + ef = vaddq_u64(ef, intermed); - for (unsigned int t = 16; t < 80; t += 16) - { + for (unsigned int t = 16; t < 80; t += 16) { /* Rounds t and t + 1 */ - s0 = vsha512su1q_u64(vsha512su0q_u64(s0, s1), s7, vextq_u64(s4, s5, 1)); + s0 = vsha512su1q_u64(vsha512su0q_u64(s0, s1), s7, vextq_u64(s4, s5, 1)); initial_sum = vaddq_u64(s0, vld1q_u64(&K[t])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), gh); - intermed = vsha512hq_u64(sum, vextq_u64(ef, gh, 1), vextq_u64(cd, ef, 1)); - gh = vsha512h2q_u64(intermed, cd, ab); - cd = vaddq_u64(cd, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), gh); + intermed = vsha512hq_u64(sum, vextq_u64(ef, gh, 1), vextq_u64(cd, ef, 1)); + gh = vsha512h2q_u64(intermed, cd, ab); + cd = vaddq_u64(cd, intermed); /* Rounds t + 2 and t + 3 */ - s1 = vsha512su1q_u64(vsha512su0q_u64(s1, s2), s0, vextq_u64(s5, s6, 1)); + s1 = vsha512su1q_u64(vsha512su0q_u64(s1, s2), s0, vextq_u64(s5, s6, 1)); initial_sum = vaddq_u64(s1, vld1q_u64(&K[t + 2])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ef); - intermed = vsha512hq_u64(sum, vextq_u64(cd, ef, 1), vextq_u64(ab, cd, 1)); - ef = vsha512h2q_u64(intermed, ab, gh); - ab = vaddq_u64(ab, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ef); + intermed = vsha512hq_u64(sum, vextq_u64(cd, ef, 1), vextq_u64(ab, cd, 1)); + ef = vsha512h2q_u64(intermed, ab, gh); + ab = vaddq_u64(ab, intermed); /* Rounds t + 4 and t + 5 */ - s2 = vsha512su1q_u64(vsha512su0q_u64(s2, s3), s1, vextq_u64(s6, s7, 1)); + s2 = vsha512su1q_u64(vsha512su0q_u64(s2, s3), s1, vextq_u64(s6, s7, 1)); initial_sum = vaddq_u64(s2, vld1q_u64(&K[t + 4])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), cd); - intermed = vsha512hq_u64(sum, vextq_u64(ab, cd, 1), vextq_u64(gh, ab, 1)); - cd = vsha512h2q_u64(intermed, gh, ef); - gh = vaddq_u64(gh, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), cd); + intermed = vsha512hq_u64(sum, vextq_u64(ab, cd, 1), vextq_u64(gh, ab, 1)); + cd = vsha512h2q_u64(intermed, gh, ef); + gh = vaddq_u64(gh, intermed); /* Rounds t + 6 and t + 7 */ - s3 = vsha512su1q_u64(vsha512su0q_u64(s3, s4), s2, vextq_u64(s7, s0, 1)); + s3 = vsha512su1q_u64(vsha512su0q_u64(s3, s4), s2, vextq_u64(s7, s0, 1)); initial_sum = vaddq_u64(s3, vld1q_u64(&K[t + 6])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ab); - intermed = vsha512hq_u64(sum, vextq_u64(gh, ab, 1), vextq_u64(ef, gh, 1)); - ab = vsha512h2q_u64(intermed, ef, cd); - ef = vaddq_u64(ef, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ab); + intermed = vsha512hq_u64(sum, vextq_u64(gh, ab, 1), vextq_u64(ef, gh, 1)); + ab = vsha512h2q_u64(intermed, ef, cd); + ef = vaddq_u64(ef, intermed); /* Rounds t + 8 and t + 9 */ - s4 = vsha512su1q_u64(vsha512su0q_u64(s4, s5), s3, vextq_u64(s0, s1, 1)); + s4 = vsha512su1q_u64(vsha512su0q_u64(s4, s5), s3, vextq_u64(s0, s1, 1)); initial_sum = vaddq_u64(s4, vld1q_u64(&K[t + 8])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), gh); - intermed = vsha512hq_u64(sum, vextq_u64(ef, gh, 1), vextq_u64(cd, ef, 1)); - gh = vsha512h2q_u64(intermed, cd, ab); - cd = vaddq_u64(cd, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), gh); + intermed = vsha512hq_u64(sum, vextq_u64(ef, gh, 1), vextq_u64(cd, ef, 1)); + gh = vsha512h2q_u64(intermed, cd, ab); + cd = vaddq_u64(cd, intermed); /* Rounds t + 10 and t + 11 */ - s5 = vsha512su1q_u64(vsha512su0q_u64(s5, s6), s4, vextq_u64(s1, s2, 1)); + s5 = vsha512su1q_u64(vsha512su0q_u64(s5, s6), s4, vextq_u64(s1, s2, 1)); initial_sum = vaddq_u64(s5, vld1q_u64(&K[t + 10])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ef); - intermed = vsha512hq_u64(sum, vextq_u64(cd, ef, 1), vextq_u64(ab, cd, 1)); - ef = vsha512h2q_u64(intermed, ab, gh); - ab = vaddq_u64(ab, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ef); + intermed = vsha512hq_u64(sum, vextq_u64(cd, ef, 1), vextq_u64(ab, cd, 1)); + ef = vsha512h2q_u64(intermed, ab, gh); + ab = vaddq_u64(ab, intermed); /* Rounds t + 12 and t + 13 */ - s6 = vsha512su1q_u64(vsha512su0q_u64(s6, s7), s5, vextq_u64(s2, s3, 1)); + s6 = vsha512su1q_u64(vsha512su0q_u64(s6, s7), s5, vextq_u64(s2, s3, 1)); initial_sum = vaddq_u64(s6, vld1q_u64(&K[t + 12])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), cd); - intermed = vsha512hq_u64(sum, vextq_u64(ab, cd, 1), vextq_u64(gh, ab, 1)); - cd = vsha512h2q_u64(intermed, gh, ef); - gh = vaddq_u64(gh, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), cd); + intermed = vsha512hq_u64(sum, vextq_u64(ab, cd, 1), vextq_u64(gh, ab, 1)); + cd = vsha512h2q_u64(intermed, gh, ef); + gh = vaddq_u64(gh, intermed); /* Rounds t + 14 and t + 15 */ - s7 = vsha512su1q_u64(vsha512su0q_u64(s7, s0), s6, vextq_u64(s3, s4, 1)); + s7 = vsha512su1q_u64(vsha512su0q_u64(s7, s0), s6, vextq_u64(s3, s4, 1)); initial_sum = vaddq_u64(s7, vld1q_u64(&K[t + 14])); - sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ab); - intermed = vsha512hq_u64(sum, vextq_u64(gh, ab, 1), vextq_u64(ef, gh, 1)); - ab = vsha512h2q_u64(intermed, ef, cd); - ef = vaddq_u64(ef, intermed); + sum = vaddq_u64(vextq_u64(initial_sum, initial_sum, 1), ab); + intermed = vsha512hq_u64(sum, vextq_u64(gh, ab, 1), vextq_u64(ef, gh, 1)); + ab = vsha512h2q_u64(intermed, ef, cd); + ef = vaddq_u64(ef, intermed); } ab = vaddq_u64(ab, ab_orig); @@ -592,20 +571,22 @@ static size_t mbedtls_internal_sha512_process_many_a64_crypto (mbedtls_sha512_co } #if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) - /* * This function is for internal use only if we are building both C and A64 * versions, otherwise it is renamed to be the public mbedtls_internal_sha512_process() */ static #endif -int mbedtls_internal_sha512_process_a64_crypto (mbedtls_sha512_context * ctx, - const unsigned char data[SHA512_BLOCK_SIZE]) +int mbedtls_internal_sha512_process_a64_crypto(mbedtls_sha512_context *ctx, + const unsigned char data[SHA512_BLOCK_SIZE]) { - return (mbedtls_internal_sha512_process_many_a64_crypto(ctx, data, SHA512_BLOCK_SIZE) == + return (mbedtls_internal_sha512_process_many_a64_crypto(ctx, data, + SHA512_BLOCK_SIZE) == SHA512_BLOCK_SIZE) ? 0 : -1; } +#endif /* MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT || MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY */ + #if defined(MBEDTLS_POP_TARGET_PRAGMA) #if defined(__clang__) #pragma clang attribute pop @@ -615,116 +596,105 @@ int mbedtls_internal_sha512_process_a64_crypto (mbedtls_sha512_context * ctx, #undef MBEDTLS_POP_TARGET_PRAGMA #endif - #endif /* MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT || MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY */ - + #if !defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) - #define mbedtls_internal_sha512_process_many_c mbedtls_internal_sha512_process_many - #define mbedtls_internal_sha512_process_c mbedtls_internal_sha512_process + #define mbedtls_internal_sha512_process_many_c mbedtls_internal_sha512_process_many + #define mbedtls_internal_sha512_process_c mbedtls_internal_sha512_process #endif + #if !defined(MBEDTLS_SHA512_PROCESS_ALT) && !defined(MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY) #if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) - /* * This function is for internal use only if we are building both C and A64 * versions, otherwise it is renamed to be the public mbedtls_internal_sha512_process() */ static #endif -int mbedtls_internal_sha512_process_c (mbedtls_sha512_context * ctx, const unsigned char data[SHA512_BLOCK_SIZE]) +int mbedtls_internal_sha512_process_c(mbedtls_sha512_context *ctx, + const unsigned char data[SHA512_BLOCK_SIZE]) { int i; - struct - { + struct { uint64_t temp1, temp2, W[80]; uint64_t A[8]; } local; - #define SHR(x, n) ((x) >> (n)) - #define ROTR(x, n) (SHR((x), (n)) | ((x) << (64 - (n)))) + #define SHR(x, n) ((x) >> (n)) + #define ROTR(x, n) (SHR((x), (n)) | ((x) << (64 - (n)))) - #define S0(x) (ROTR(x, 1) ^ ROTR(x, 8) ^ SHR(x, 7)) - #define S1(x) (ROTR(x, 19) ^ ROTR(x, 61) ^ SHR(x, 6)) +#define S0(x) (ROTR(x, 1) ^ ROTR(x, 8) ^ SHR(x, 7)) +#define S1(x) (ROTR(x, 19) ^ ROTR(x, 61) ^ SHR(x, 6)) - #define S2(x) (ROTR(x, 28) ^ ROTR(x, 34) ^ ROTR(x, 39)) - #define S3(x) (ROTR(x, 14) ^ ROTR(x, 18) ^ ROTR(x, 41)) +#define S2(x) (ROTR(x, 28) ^ ROTR(x, 34) ^ ROTR(x, 39)) +#define S3(x) (ROTR(x, 14) ^ ROTR(x, 18) ^ ROTR(x, 41)) - #define F0(x, y, z) (((x) & (y)) | ((z) & ((x) | (y)))) - #define F1(x, y, z) ((z) ^ ((x) & ((y) ^ (z)))) +#define F0(x, y, z) (((x) & (y)) | ((z) & ((x) | (y)))) +#define F1(x, y, z) ((z) ^ ((x) & ((y) ^ (z)))) - #define P(a, b, c, d, e, f, g, h, x, K) \ +#define P(a, b, c, d, e, f, g, h, x, K) \ do \ { \ - local.temp1 = (h) + S3(e) + F1((e), (f), (g)) + (K) + (x); \ - local.temp2 = S2(a) + F0((a), (b), (c)); \ - (d) += local.temp1; (h) = local.temp1 + local.temp2; \ + local.temp1 = (h) + S3(e) + F1((e), (f), (g)) + (K) + (x); \ + local.temp2 = S2(a) + F0((a), (b), (c)); \ + (d) += local.temp1; (h) = local.temp1 + local.temp2; \ } while (0) - for (i = 0; i < 8; i++) - { + for (i = 0; i < 8; i++) { local.A[i] = ctx->state[i]; } #if defined(MBEDTLS_SHA512_SMALLER) - for (i = 0; i < 80; i++) - { - if (i < 16) - { + for (i = 0; i < 80; i++) { + if (i < 16) { local.W[i] = MBEDTLS_GET_UINT64_BE(data, i << 3); - } - else - { - local.W[i] = S1(local.W[i - 2]) + local.W[i - 7] + + } else { + local.W[i] = S1(local.W[i - 2]) + local.W[i - 7] + S0(local.W[i - 15]) + local.W[i - 16]; } - P(local.A[0], local.A[1], local.A[2], local.A[3], local.A[4], local.A[5], local.A[6], local.A[7], local.W[i], - K[i]); + P(local.A[0], local.A[1], local.A[2], local.A[3], local.A[4], + local.A[5], local.A[6], local.A[7], local.W[i], K[i]); local.temp1 = local.A[7]; local.A[7] = local.A[6]; - local.A[6] = local.A[5]; local.A[5] = local.A[4]; - local.A[4] = local.A[3]; local.A[3] = local.A[2]; - local.A[2] = local.A[1]; local.A[1] = local.A[0]; - local.A[0] = local.temp1; + local.A[6] = local.A[5]; local.A[5] = local.A[4]; + local.A[4] = local.A[3]; local.A[3] = local.A[2]; + local.A[2] = local.A[1]; local.A[1] = local.A[0]; + local.A[0] = local.temp1; } - - #else /* MBEDTLS_SHA512_SMALLER */ - for (i = 0; i < 16; i++) - { +#else /* MBEDTLS_SHA512_SMALLER */ + for (i = 0; i < 16; i++) { local.W[i] = MBEDTLS_GET_UINT64_BE(data, i << 3); } - for ( ; i < 80; i++) - { - local.W[i] = S1(local.W[i - 2]) + local.W[i - 7] + + for (; i < 80; i++) { + local.W[i] = S1(local.W[i - 2]) + local.W[i - 7] + S0(local.W[i - 15]) + local.W[i - 16]; } i = 0; - do - { - P(local.A[0], local.A[1], local.A[2], local.A[3], local.A[4], local.A[5], local.A[6], local.A[7], local.W[i], - K[i]); i++; - P(local.A[7], local.A[0], local.A[1], local.A[2], local.A[3], local.A[4], local.A[5], local.A[6], local.W[i], - K[i]); i++; - P(local.A[6], local.A[7], local.A[0], local.A[1], local.A[2], local.A[3], local.A[4], local.A[5], local.W[i], - K[i]); i++; - P(local.A[5], local.A[6], local.A[7], local.A[0], local.A[1], local.A[2], local.A[3], local.A[4], local.W[i], - K[i]); i++; - P(local.A[4], local.A[5], local.A[6], local.A[7], local.A[0], local.A[1], local.A[2], local.A[3], local.W[i], - K[i]); i++; - P(local.A[3], local.A[4], local.A[5], local.A[6], local.A[7], local.A[0], local.A[1], local.A[2], local.W[i], - K[i]); i++; - P(local.A[2], local.A[3], local.A[4], local.A[5], local.A[6], local.A[7], local.A[0], local.A[1], local.W[i], - K[i]); i++; - P(local.A[1], local.A[2], local.A[3], local.A[4], local.A[5], local.A[6], local.A[7], local.A[0], local.W[i], - K[i]); i++; + do { + P(local.A[0], local.A[1], local.A[2], local.A[3], local.A[4], + local.A[5], local.A[6], local.A[7], local.W[i], K[i]); i++; + P(local.A[7], local.A[0], local.A[1], local.A[2], local.A[3], + local.A[4], local.A[5], local.A[6], local.W[i], K[i]); i++; + P(local.A[6], local.A[7], local.A[0], local.A[1], local.A[2], + local.A[3], local.A[4], local.A[5], local.W[i], K[i]); i++; + P(local.A[5], local.A[6], local.A[7], local.A[0], local.A[1], + local.A[2], local.A[3], local.A[4], local.W[i], K[i]); i++; + P(local.A[4], local.A[5], local.A[6], local.A[7], local.A[0], + local.A[1], local.A[2], local.A[3], local.W[i], K[i]); i++; + P(local.A[3], local.A[4], local.A[5], local.A[6], local.A[7], + local.A[0], local.A[1], local.A[2], local.W[i], K[i]); i++; + P(local.A[2], local.A[3], local.A[4], local.A[5], local.A[6], + local.A[7], local.A[0], local.A[1], local.W[i], K[i]); i++; + P(local.A[1], local.A[2], local.A[3], local.A[4], local.A[5], + local.A[6], local.A[7], local.A[0], local.W[i], K[i]); i++; } while (i < 80); - #endif /* MBEDTLS_SHA512_SMALLER */ +#endif /* MBEDTLS_SHA512_SMALLER */ - for (i = 0; i < 8; i++) - { + for (i = 0; i < 8; i++) { ctx->state[i] += local.A[i]; } @@ -734,18 +704,18 @@ int mbedtls_internal_sha512_process_c (mbedtls_sha512_context * ctx, const unsig return 0; } - #endif /* !MBEDTLS_SHA512_PROCESS_ALT && !MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY */ + #endif /* !MBEDTLS_SHA512_PROCESS_ALT && !MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY */ + #if !defined(MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY) -static size_t mbedtls_internal_sha512_process_many_c (mbedtls_sha512_context * ctx, const uint8_t * data, size_t len) +static size_t mbedtls_internal_sha512_process_many_c( + mbedtls_sha512_context *ctx, const uint8_t *data, size_t len) { size_t processed = 0; - while (len >= SHA512_BLOCK_SIZE) - { - if (mbedtls_internal_sha512_process_c(ctx, data) != 0) - { + while (len >= SHA512_BLOCK_SIZE) { + if (mbedtls_internal_sha512_process_c(ctx, data) != 0) { return 0; } @@ -758,63 +728,60 @@ static size_t mbedtls_internal_sha512_process_many_c (mbedtls_sha512_context * c return processed; } - #endif /* !MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY */ + #endif /* !MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY */ + #if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) -static int mbedtls_a64_crypto_sha512_has_support (void) +static int mbedtls_a64_crypto_sha512_has_support(void) { - static int done = 0; + static int done = 0; static int supported = 0; - if (!done) - { + if (!done) { supported = mbedtls_a64_crypto_sha512_determine_support(); - done = 1; + done = 1; } return supported; } -static size_t mbedtls_internal_sha512_process_many (mbedtls_sha512_context * ctx, const uint8_t * msg, size_t len) +static size_t mbedtls_internal_sha512_process_many(mbedtls_sha512_context *ctx, + const uint8_t *msg, size_t len) { - if (mbedtls_a64_crypto_sha512_has_support()) - { + if (mbedtls_a64_crypto_sha512_has_support()) { return mbedtls_internal_sha512_process_many_a64_crypto(ctx, msg, len); - } - else - { + } else { return mbedtls_internal_sha512_process_many_c(ctx, msg, len); } } -int mbedtls_internal_sha512_process (mbedtls_sha512_context * ctx, const unsigned char data[SHA512_BLOCK_SIZE]) +int mbedtls_internal_sha512_process(mbedtls_sha512_context *ctx, + const unsigned char data[SHA512_BLOCK_SIZE]) { - if (mbedtls_a64_crypto_sha512_has_support()) - { + if (mbedtls_a64_crypto_sha512_has_support()) { return mbedtls_internal_sha512_process_a64_crypto(ctx, data); - } - else - { + } else { return mbedtls_internal_sha512_process_c(ctx, data); } } - #endif /* MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT */ +#endif /* MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT */ /* * SHA-512 process buffer */ -int mbedtls_sha512_update (mbedtls_sha512_context * ctx, const unsigned char * input, size_t ilen) +int mbedtls_sha512_update(mbedtls_sha512_context *ctx, + const unsigned char *input, + size_t ilen) { - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - size_t fill; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t fill; unsigned int left; uint32_t sha512_block_aligned_size; uint32_t sha512_block_aligned_size_mod; - if (ilen == 0) - { + if (ilen == 0) { return 0; } @@ -823,13 +790,11 @@ int mbedtls_sha512_update (mbedtls_sha512_context * ctx, const unsigned char * i ctx->total[0] += (uint64_t) ilen; - if (ctx->total[0] < (uint64_t) ilen) - { + if (ctx->total[0] < (uint64_t) ilen) { ctx->total[1]++; } - if (left && (ilen >= fill)) - { + if (left && ilen >= fill) { memcpy((void *) (ctx->buffer + left), input, fill); input += fill; @@ -1040,4 +1005,4 @@ int mbedtls_sha512_finish (mbedtls_sha512_context * ctx, unsigned char * output) #endif /* !MBEDTLS_SHA512_ALT */ -#endif /* MBEDTLS_SHA512_C || MBEDTLS_SHA384_C */ +#endif /* MBEDTLS_SHA512_C || MBEDTLS_SHA384_C */ diff --git a/ra/fsp/src/rm_psa_crypto/vendor.c b/ra/fsp/src/rm_psa_crypto/vendor.c index c94ca526e..0cb16d005 100644 --- a/ra/fsp/src/rm_psa_crypto/vendor.c +++ b/ra/fsp/src/rm_psa_crypto/vendor.c @@ -123,7 +123,7 @@ psa_status_t psa_generate_key_vendor (psa_key_slot_t * slot, if (PSA_KEY_TYPE_IS_RSA_KEY_PAIR_WRAPPED(slot->attr.type)) { mbedtls_rsa_context * rsa; - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED;; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; int exponent; uint32_t export_der_size_bytes = 0; @@ -214,7 +214,7 @@ psa_status_t psa_generate_key_vendor (psa_key_slot_t * slot, psa_ecc_family_t curve = PSA_KEY_TYPE_ECC_GET_FAMILY(slot->attr.type); uint32_t ecc_bytes = 0; mbedtls_ecp_group_id grp_id = - mbedtls_ecc_group_of_psa(curve, bits, 0); + mbedtls_ecc_group_of_psa(curve, bits, 1); const mbedtls_ecp_curve_info * curve_info = mbedtls_ecp_curve_info_from_grp_id(grp_id); mbedtls_ecp_keypair * ecp; diff --git a/ra/fsp/src/rm_tfm_port/config_impl.h b/ra/fsp/src/rm_tfm_port/config_impl.h index b1916b734..1202f0ce1 100644 --- a/ra/fsp/src/rm_tfm_port/config_impl.h +++ b/ra/fsp/src/rm_tfm_port/config_impl.h @@ -11,16 +11,10 @@ #include "config_tfm.h" -/* Backends */ /* Backends */ #define CONFIG_TFM_SPM_BACKEND_IPC 1 #define CONFIG_TFM_SPM_BACKEND_SFN 0 -/* API calls */ -#define CONFIG_TFM_PSA_API_SFN_CALL 0 -#define CONFIG_TFM_PSA_API_CROSS_CALL 0 -#define CONFIG_TFM_PSA_API_SUPERVISOR_CALL 1 - #define CONFIG_TFM_CONNECTION_BASED_SERVICE_API 1 #define CONFIG_TFM_MMIO_REGION_ENABLE 0 #define CONFIG_TFM_FLIH_API 0 @@ -28,15 +22,15 @@ #if CONFIG_TFM_SPM_BACKEND_IPC == 1 /* Trustzone NS agent working stack size. */ -#if defined(TFM_FIH_PROFILE_ON) && TFM_LVL == 1 -#define CONFIG_TFM_NS_AGENT_TZ_STACK_SIZE 1256 +#if defined(TFM_FIH_PROFILE_ON) && TFM_ISOLATION_LEVEL == 1 +#define CONFIG_TFM_NS_AGENT_TZ_STACK_SIZE 1256 #else -#define CONFIG_TFM_NS_AGENT_TZ_STACK_SIZE 1024 +#define CONFIG_TFM_NS_AGENT_TZ_STACK_SIZE 1024 #endif /* SPM re-uses Trustzone NS agent stack. */ #define CONFIG_TFM_SPM_THREAD_STACK_SIZE \ - CONFIG_TFM_NS_AGENT_TZ_STACK_SIZE + CONFIG_TFM_NS_AGENT_TZ_STACK_SIZE #elif CONFIG_TFM_SPM_BACKEND_SFN == 1 @@ -47,4 +41,3 @@ #endif /* CONFIG_TFM_SPM_BACKEND_IPC == 1 */ #endif /* __CONFIG_IMPL_H__ */ - diff --git a/ra/fsp/src/rm_tfm_port/ra/boot_hal_bl2.c b/ra/fsp/src/rm_tfm_port/ra/boot_hal_bl2.c index df108ade8..23261bdf6 100644 --- a/ra/fsp/src/rm_tfm_port/ra/boot_hal_bl2.c +++ b/ra/fsp/src/rm_tfm_port/ra/boot_hal_bl2.c @@ -31,9 +31,9 @@ REGION_DECLARE(Image$$, ER_DATA, $$Base)[]; REGION_DECLARE(Image$$, ARM_LIB_HEAP, $$ZI$$Limit)[]; REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -__attribute__((naked)) void boot_clear_bl2_ram_area(void) +__attribute__((naked)) void boot_clear_bl2_ram_area (void) { - __ASM volatile( + __ASM volatile ( "mov r0, #0 \n" "subs %1, %1, %0 \n" "Loop: \n" @@ -44,9 +44,9 @@ __attribute__((naked)) void boot_clear_bl2_ram_area(void) "bx lr \n" : : "r" (REGION_NAME(Image$$, ER_DATA, $$Base)), - "r" (REGION_NAME(Image$$, ARM_LIB_HEAP, $$ZI$$Limit)) + "r" (REGION_NAME(Image$$, ARM_LIB_HEAP, $$ZI$$Limit)) : "r0", "memory" - ); + ); } /* @@ -90,7 +90,7 @@ static void flash_FAW_Set (uint32_t start_addr, uint32_t end_addr) /* bootloader platform-specific HW intialization */ int32_t boot_platform_init (void) { - int32_t result; + int32_t result; result = FLASH_DEV_NAME.Initialize(NULL); if (ARM_DRIVER_OK != result) @@ -120,18 +120,18 @@ int32_t boot_platform_init (void) return result; } -__WEAK int32_t boot_platform_post_init(void) +__WEAK int32_t boot_platform_post_init (void) { #ifdef CRYPTO_HW_ACCELERATOR int32_t result; result = crypto_hw_accelerator_init(); - if (result) { + if (result) + { return 1; } - - (void)fih_delay_init(); -#endif /* CRYPTO_HW_ACCELERATOR */ + (void) fih_delay_init(); +#endif /* CRYPTO_HW_ACCELERATOR */ return 0; } @@ -148,35 +148,50 @@ void boot_platform_quit (struct boot_arm_vector_table * vt) #ifdef CRYPTO_HW_ACCELERATOR result = crypto_hw_accelerator_finish(); - if (result) { - while (1){} + if (result) + { + while (1) + { + } } -#endif /* CRYPTO_HW_ACCELERATOR */ +#endif /* CRYPTO_HW_ACCELERATOR */ #ifdef FLASH_DEV_NAME result = FLASH_DEV_NAME.Uninitialize(); - if (result != ARM_DRIVER_OK) { - while(1) {} + if (result != ARM_DRIVER_OK) + { + while (1) + { + } } -#endif /* FLASH_DEV_NAME */ +#endif /* FLASH_DEV_NAME */ #ifdef FLASH_DEV_NAME_2 result = FLASH_DEV_NAME_2.Uninitialize(); - if (result != ARM_DRIVER_OK) { - while(1) {} + if (result != ARM_DRIVER_OK) + { + while (1) + { + } } -#endif /* FLASH_DEV_NAME_2 */ +#endif /* FLASH_DEV_NAME_2 */ #ifdef FLASH_DEV_NAME_3 result = FLASH_DEV_NAME_3.Uninitialize(); - if (result != ARM_DRIVER_OK) { - while(1) {} + if (result != ARM_DRIVER_OK) + { + while (1) + { + } } -#endif /* FLASH_DEV_NAME_3 */ +#endif /* FLASH_DEV_NAME_3 */ #ifdef FLASH_DEV_NAME_SCRATCH result = FLASH_DEV_NAME_SCRATCH.Uninitialize(); - if (result != ARM_DRIVER_OK) { - while(1) {} + if (result != ARM_DRIVER_OK) + { + while (1) + { + } } -#endif /* FLASH_DEV_NAME_SCRATCH */ +#endif /* FLASH_DEV_NAME_SCRATCH */ vt_cpy = vt; #if BSP_FEATURE_BSP_HAS_SP_MON @@ -184,7 +199,7 @@ void boot_platform_quit (struct boot_arm_vector_table * vt) /* Disable MSP monitoring */ R_MPU_SPMON->SP[0].CTL = 0; #endif -#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) +#if defined(RENESAS_CORTEX_M23) || defined(RENESAS_CORTEX_M33) || defined(RENESAS_CORTEX_M85) /* Restore the Main Stack Pointer Limit register's reset value * before passing execution to runtime firmware to make the @@ -199,12 +214,12 @@ void boot_platform_quit (struct boot_arm_vector_table * vt) boot_jump_to_next_image(vt_cpy->reset); } -__WEAK int boot_platform_pre_load(uint32_t image_id) +__WEAK int boot_platform_pre_load (uint32_t image_id) { return 0; } -__WEAK int boot_platform_post_load(uint32_t image_id) +__WEAK int boot_platform_post_load (uint32_t image_id) { return 0; } diff --git a/ra/fsp/src/rm_tfm_port/ra/services/include/tfm_ioctl_api.h b/ra/fsp/src/rm_tfm_port/ra/services/include/tfm_ioctl_api.h index c040eaaba..28fac09dc 100644 --- a/ra/fsp/src/rm_tfm_port/ra/services/include/tfm_ioctl_api.h +++ b/ra/fsp/src/rm_tfm_port/ra/services/include/tfm_ioctl_api.h @@ -11,7 +11,6 @@ #include #include #include -#include "tfm_api.h" #include "tfm_platform_api.h" #ifdef __cplusplus diff --git a/ra/fsp/src/rm_tfm_port/ra/tfm_hal_isolation.c b/ra/fsp/src/rm_tfm_port/ra/tfm_hal_isolation.c index 4dcdf13dc..5a2d6f3b5 100644 --- a/ra/fsp/src/rm_tfm_port/ra/tfm_hal_isolation.c +++ b/ra/fsp/src/rm_tfm_port/ra/tfm_hal_isolation.c @@ -30,7 +30,7 @@ REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$ZI$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$ZI$$Limit); #endif /* CONFIG_TFM_PARTITION_META */ -#if TFM_LVL == 3 +#if TFM_ISOLATION_LEVEL == 3 static uint32_t idx_boundary_handle = 0; REGION_DECLARE(Image$$, PT_RO_START, $$Base); REGION_DECLARE(Image$$, PT_RO_END, $$Base); @@ -72,7 +72,7 @@ const static struct mpu_armv8m_region_cfg_t isolation_regions[] = { } #endif }; -#else /* TFM_LVL == 3 */ +#else /* TFM_ISOLATION_LEVEL == 3 */ REGION_DECLARE(Image$$, ER_VENEER, $$Base); REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit); @@ -137,7 +137,7 @@ const struct mpu_armv8m_region_cfg_t region_cfg[] = { } #endif }; -#endif /* TFM_LVL == 3 */ +#endif /* TFM_ISOLATION_LEVEL == 3 */ #endif /* CONFIG_TFM_ENABLE_MEMORY_PROTECT */ enum tfm_hal_status_t tfm_hal_set_up_static_boundaries(uintptr_t *p_spm_boundary) @@ -214,7 +214,7 @@ enum tfm_hal_status_t tfm_hal_bind_boundary( bool ns_agent; uint32_t partition_attrs = 0; const struct asset_desc_t *p_asset; -#if TFM_LVL == 2 +#if TFM_ISOLATION_LEVEL == 2 struct platform_data_t *plat_data_ptr; struct mpu_armv8m_region_cfg_t localcfg; #endif @@ -223,7 +223,7 @@ enum tfm_hal_status_t tfm_hal_bind_boundary( return TFM_HAL_ERROR_GENERIC; } -#if TFM_LVL == 1 +#if TFM_ISOLATION_LEVEL == 1 privileged = true; #else privileged = IS_PSA_ROT(p_ldinf); @@ -252,7 +252,7 @@ enum tfm_hal_status_t tfm_hal_bind_boundary( /* The MMIO asset is not in the allowed list of platform. */ return TFM_HAL_ERROR_GENERIC; } -#if TFM_LVL == 2 +#if TFM_ISOLATION_LEVEL == 2 plat_data_ptr = REFERENCE_TO_PTR(p_asset[i].dev.dev_ref, struct platform_data_t *); /* @@ -273,7 +273,7 @@ enum tfm_hal_status_t tfm_hal_bind_boundary( return TFM_HAL_ERROR_GENERIC; } } -#elif TFM_LVL == 3 +#elif TFM_ISOLATION_LEVEL == 3 /* Encode MMIO attributes into the "partition_attrs". */ partition_attrs <<= HANDLE_PER_ATTR_BITS; partition_attrs |= ((j + 1) & HANDLE_ATTR_INDEX_MASK); @@ -283,7 +283,7 @@ enum tfm_hal_status_t tfm_hal_bind_boundary( #endif } -#if TFM_LVL == 3 +#if TFM_ISOLATION_LEVEL == 3 partition_attrs <<= HANDLE_PER_ATTR_BITS; /* * Highest 8 bits are reserved for index, if they are non-zero, MMIO numbers @@ -311,7 +311,7 @@ enum tfm_hal_status_t tfm_hal_activate_boundary( CONTROL_Type ctrl; uint32_t local_handle = (uint32_t)boundary; bool privileged = !!(local_handle & HANDLE_ATTR_PRIV_MASK); -#if TFM_LVL == 3 +#if TFM_ISOLATION_LEVEL == 3 struct mpu_armv8m_region_cfg_t localcfg; uint32_t i, mmio_index; struct platform_data_t *plat_data_ptr; @@ -323,7 +323,7 @@ enum tfm_hal_status_t tfm_hal_activate_boundary( ctrl.b.nPRIV = privileged ? 0 : 1; __set_CONTROL(ctrl.w); -#if TFM_LVL == 3 +#if TFM_ISOLATION_LEVEL == 3 if (!p_ldinf) { return TFM_HAL_ERROR_GENERIC; } diff --git a/ra/fsp/src/rm_threadx_port/tx_initialize_low_level.c b/ra/fsp/src/rm_threadx_port/tx_initialize_low_level.c index a185a95f6..4bc884e96 100644 --- a/ra/fsp/src/rm_threadx_port/tx_initialize_low_level.c +++ b/ra/fsp/src/rm_threadx_port/tx_initialize_low_level.c @@ -1,4 +1,5 @@ /**************************************************************************/ + /* */ /* Copyright (c) Microsoft Corporation. All rights reserved. */ /* */ @@ -9,7 +10,6 @@ /* */ /**************************************************************************/ - /**************************************************************************/ /**************************************************************************/ /** */ @@ -105,7 +105,7 @@ VOID _tx_initialize_low_level (VOID) /* Set system stack pointer from vector value. */ _tx_thread_system_stack_ptr = TX_VECTOR_TABLE[0]; -#if defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) +#if defined(RENESAS_CORTEX_M4) || defined(RENESAS_CORTEX_M33) || defined(RENESAS_CORTEX_M85) /* Enable the cycle count register. */ DWT->CTRL |= (uint32_t) DWT_CTRL_CYCCNTENA_Msk; diff --git a/ra/fsp/src/rm_threadx_port/tx_port.h b/ra/fsp/src/rm_threadx_port/tx_port.h index 0ad9b9529..9da2c2e9d 100644 --- a/ra/fsp/src/rm_threadx_port/tx_port.h +++ b/ra/fsp/src/rm_threadx_port/tx_port.h @@ -1,4 +1,5 @@ /**************************************************************************/ + /* */ /* Copyright (c) Microsoft Corporation. All rights reserved. */ /* */ @@ -9,7 +10,6 @@ /* */ /**************************************************************************/ - /**************************************************************************/ /**************************************************************************/ /** */ @@ -20,7 +20,6 @@ /**************************************************************************/ /**************************************************************************/ - /**************************************************************************/ /* */ /* PORT SPECIFIC C INFORMATION RELEASE */ @@ -41,587 +40,588 @@ /**************************************************************************/ #ifndef TX_PORT_H -#define TX_PORT_H + #define TX_PORT_H -#include "tx_port_vendor.h" + #include "tx_port_vendor.h" /* Determine if the optional ThreadX user define file should be used. */ -#ifdef TX_INCLUDE_USER_DEFINE_FILE + #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may - alternately be defined on the command line. */ +/* Yes, include the user defines in tx_user.h. The defines in this file may + * alternately be defined on the command line. */ -#include "tx_user.h" -#endif + #include "tx_user.h" + #endif /* Define compiler library include files. */ -#include -#include -#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#include -#endif + #include + #include + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + #include + #endif /* CMSIS Core access. */ -#include "tx_cmsis.h" + #include "tx_cmsis.h" /* Determine non-secure callable functions can be accessed in threads. */ -#if defined(__ARM_FEATURE_CMSE) && !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) -#define TX_PORT_TRUSTZONE_NSC_ENABLE -#endif + #if defined(__ARM_FEATURE_CMSE) && !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + #define TX_PORT_TRUSTZONE_NSC_ENABLE + #endif /* If non-secure callable functions can be accessed in threads, include the CMSIS TrustZone secure context header. */ -#ifdef TX_PORT_TRUSTZONE_NSC_ENABLE -#include "tz_context.h" -#endif + #ifdef TX_PORT_TRUSTZONE_NSC_ENABLE + #include "tz_context.h" + #endif -#ifdef __cplusplus + #ifdef __cplusplus extern "C" { -#endif + #endif /* Define ThreadX basic types for this port. */ -#define VOID void -typedef char CHAR; -typedef unsigned char UCHAR; -typedef int INT; -typedef unsigned int UINT; -typedef long LONG; -typedef unsigned long ULONG; -typedef unsigned long long ULONG64; -typedef short SHORT; -typedef unsigned short USHORT; + #define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; /* Define this so that the FileX port doesn't try to define ULONG64 as well. */ -#define ULONG64_DEFINED + #define ULONG64_DEFINED -#if defined(TX_PORT_TRUSTZONE_NSC_ENABLE) + #if defined(TX_PORT_TRUSTZONE_NSC_ENABLE) /* Function prototypes for this port. */ struct TX_THREAD_STRUCT; -UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size); -UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); -UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size); -UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); +UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT * thread_ptr, ULONG stack_size); +UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT * thread_ptr); +UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT * thread_ptr, ULONG stack_size); +UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT * thread_ptr); -/* Define the system API mappings based on the error checking - selected by the user. Note: this section is only applicable to - application source code, hence the conditional that turns off this - stuff when the include file is processed by the ThreadX source. */ +/* Define the system API mappings based on the error checking + * selected by the user. Note: this section is only applicable to + * application source code, hence the conditional that turns off this + * stuff when the include file is processed by the ThreadX source. */ -#ifndef TX_SOURCE_CODE + #ifndef TX_SOURCE_CODE +/* Determine if error checking is desired. If so, map API functions + * to the appropriate error checking front-ends. Otherwise, map API + * functions to the core functions that actually perform the work. + * Note: error checking is enabled by default. */ -/* Determine if error checking is desired. If so, map API functions - to the appropriate error checking front-ends. Otherwise, map API - functions to the core functions that actually perform the work. - Note: error checking is enabled by default. */ - -#ifdef TX_DISABLE_ERROR_CHECKING + #ifdef TX_DISABLE_ERROR_CHECKING /* Services without error checking. */ -#define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate -#define tx_thread_secure_stack_free _tx_thread_secure_stack_free + #define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate + #define tx_thread_secure_stack_free _tx_thread_secure_stack_free -#else + #else /* Services with error checking. */ -#define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate -#define tx_thread_secure_stack_free _txe_thread_secure_stack_free - -#endif -#endif + #define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate + #define tx_thread_secure_stack_free _txe_thread_secure_stack_free -#endif + #endif + #endif + #endif /* Define the priority levels for ThreadX. Legal values range - from 32 to 1024 and MUST be evenly divisible by 32. */ - -#ifndef TX_MAX_PRIORITIES -#define TX_MAX_PRIORITIES 32 -#endif + * from 32 to 1024 and MUST be evenly divisible by 32. */ + #ifndef TX_MAX_PRIORITIES + #define TX_MAX_PRIORITIES 32 + #endif /* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during - thread creation is less than this value, the thread create call will return an error. */ - -#ifndef TX_MINIMUM_STACK -#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ -#endif + * thread creation is less than this value, the thread create call will return an error. */ + #ifndef TX_MINIMUM_STACK + #define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ + #endif /* Define the system timer thread's default stack size and priority. These are only applicable - if TX_TIMER_PROCESS_IN_ISR is not defined. */ - -#ifndef TX_TIMER_THREAD_STACK_SIZE -#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ -#endif + * if TX_TIMER_PROCESS_IN_ISR is not defined. */ -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ -#endif + #ifndef TX_TIMER_THREAD_STACK_SIZE + #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ + #endif + #ifndef TX_TIMER_THREAD_PRIORITY + #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ + #endif /* Define various constants for the ThreadX Cortex-M port. */ -#define TX_INT_DISABLE 1 /* Disable interrupts */ -#define TX_INT_ENABLE 0 /* Enable interrupts */ - + #define TX_INT_DISABLE 1 /* Disable interrupts */ + #define TX_INT_ENABLE 0 /* Enable interrupts */ /* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock - source constants would be: - -#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) -#define TX_TRACE_TIME_MASK 0x0000FFFFUL + * For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + * source constants would be: + * + #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) + #define TX_TRACE_TIME_MASK 0x0000FFFFUL + * + */ + + #ifndef TX_MISRA_ENABLE + #ifndef TX_TRACE_TIME_SOURCE + #if defined(RENESAS_CORTEX_M4) || defined(RENESAS_CORTEX_M33) || defined(RENESAS_CORTEX_M85) + +/* CM4, CM33, and CM85 do have DWT. */ + #define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) + #else -*/ - -#ifndef TX_MISRA_ENABLE -#ifndef TX_TRACE_TIME_SOURCE -#if defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) -/* CM4 and CM33 do have DWT. */ -#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) -#else /* CM23 does not have DWT. */ -#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time -#endif -#endif -#else -ULONG _tx_misra_time_stamp_get(VOID); -#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() -#endif + #define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time + #endif + #endif + #else +ULONG _tx_misra_time_stamp_get(VOID); -#ifndef TX_TRACE_TIME_MASK -#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL -#endif + #define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() + #endif + #ifndef TX_TRACE_TIME_MASK + #define TX_TRACE_TIME_MASK 0xFFFFFFFFUL + #endif /* Define the port specific options for the _tx_build_options variable. This variable indicates - how the ThreadX library was built. */ - -#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + * how the ThreadX library was built. */ + #define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) /* Define the in-line initialization constant so that modules with in-line - initialization capabilities can prevent their initialization from being - a function call. */ - -#ifdef TX_MISRA_ENABLE -#define TX_DISABLE_INLINE -#else -#define TX_INLINE_INITIALIZATION -#endif - - -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is - disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack - checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING - define is negated, thereby forcing the stack fill which is necessary for the stack checking - logic. */ - -#ifndef TX_MISRA_ENABLE -#ifdef TX_ENABLE_STACK_CHECKING -#undef TX_DISABLE_STACK_FILLING -#endif -#endif - + * initialization capabilities can prevent their initialization from being + * a function call. */ + + #ifdef TX_MISRA_ENABLE + #define TX_DISABLE_INLINE + #else + #define TX_INLINE_INITIALIZATION + #endif + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + * disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + * checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + * define is negated, thereby forcing the stack fill which is necessary for the stack checking + * logic. */ + + #ifndef TX_MISRA_ENABLE + #ifdef TX_ENABLE_STACK_CHECKING + #undef TX_DISABLE_STACK_FILLING + #endif + #endif /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with - existing ThreadX kernel awareness modules. */ + * for the multiple macros is so that backward compatibility can be maintained with + * existing ThreadX kernel awareness modules. */ -#ifndef TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_0 -#endif + #ifndef TX_THREAD_EXTENSION_0 + #define TX_THREAD_EXTENSION_0 + #endif -#ifndef TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_1 -#endif + #ifndef TX_THREAD_EXTENSION_1 + #define TX_THREAD_EXTENSION_1 + #endif + + #ifndef TX_THREAD_EXTENSION_2 + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#ifndef TX_THREAD_EXTENSION_2 -#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT /* IAR library support */ -#ifdef TX_PORT_TRUSTZONE_NSC_ENABLE -/* ThreadX in non-secure zone with calls to secure zone. */ -#define TX_THREAD_EXTENSION_2 TZ_MemoryId_t tx_thread_secure_stack_context; \ - VOID *tx_thread_iar_tls_pointer; -#else -/* ThreadX in only one zone. */ -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; -#endif + #ifdef TX_PORT_TRUSTZONE_NSC_ENABLE -#else -/* No IAR library support */ -#ifdef TX_PORT_TRUSTZONE_NSC_ENABLE /* ThreadX in non-secure zone with calls to secure zone. */ -#define TX_THREAD_EXTENSION_2 TZ_MemoryId_t tx_thread_secure_stack_context; -#else -/* ThreadX in only one zone. */ -#define TX_THREAD_EXTENSION_2 -#endif -#endif -#endif + #define TX_THREAD_EXTENSION_2 TZ_MemoryId_t tx_thread_secure_stack_context; \ + VOID * tx_thread_iar_tls_pointer; + #else -#ifndef TX_THREAD_EXTENSION_3 -#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY -#define TX_THREAD_EXTENSION_3 -#else -#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; -#endif -#endif +/* ThreadX in only one zone. */ + #define TX_THREAD_EXTENSION_2 VOID * tx_thread_iar_tls_pointer; + #endif -/* Define the port extensions of the remaining ThreadX objects. */ + #else -#ifndef TX_BLOCK_POOL_EXTENSION -#define TX_BLOCK_POOL_EXTENSION -#endif -#ifndef TX_BYTE_POOL_EXTENSION -#define TX_BYTE_POOL_EXTENSION -#endif -#ifndef TX_EVENT_FLAGS_GROUP_EXTENSION -#define TX_EVENT_FLAGS_GROUP_EXTENSION -#endif -#ifndef TX_MUTEX_EXTENSION -#define TX_MUTEX_EXTENSION -#endif -#ifndef TX_QUEUE_EXTENSION -#define TX_QUEUE_EXTENSION -#endif -#ifndef TX_SEMAPHORE_EXTENSION -#define TX_SEMAPHORE_EXTENSION -#endif -#ifndef TX_TIMER_EXTENSION -#define TX_TIMER_EXTENSION -#endif +/* No IAR library support */ + #ifdef TX_PORT_TRUSTZONE_NSC_ENABLE +/* ThreadX in non-secure zone with calls to secure zone. */ + #define TX_THREAD_EXTENSION_2 TZ_MemoryId_t tx_thread_secure_stack_context; + #else -/* Define the user extension field of the thread control block. Nothing - additional is needed for this port so it is defined as white space. */ +/* ThreadX in only one zone. */ + #define TX_THREAD_EXTENSION_2 + #endif + #endif + #endif + + #ifndef TX_THREAD_EXTENSION_3 + #ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + #define TX_THREAD_EXTENSION_3 + #else + #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ + unsigned long long tx_thread_execution_time_last_start; + #endif + #endif -#ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION -#endif +/* Define the port extensions of the remaining ThreadX objects. */ + #ifndef TX_BLOCK_POOL_EXTENSION + #define TX_BLOCK_POOL_EXTENSION + #endif + #ifndef TX_BYTE_POOL_EXTENSION + #define TX_BYTE_POOL_EXTENSION + #endif + #ifndef TX_EVENT_FLAGS_GROUP_EXTENSION + #define TX_EVENT_FLAGS_GROUP_EXTENSION + #endif + #ifndef TX_MUTEX_EXTENSION + #define TX_MUTEX_EXTENSION + #endif + #ifndef TX_QUEUE_EXTENSION + #define TX_QUEUE_EXTENSION + #endif + #ifndef TX_SEMAPHORE_EXTENSION + #define TX_SEMAPHORE_EXTENSION + #endif + #ifndef TX_TIMER_EXTENSION + #define TX_TIMER_EXTENSION + #endif + +/* Define the user extension field of the thread control block. Nothing + * additional is needed for this port so it is defined as white space. */ + + #ifndef TX_THREAD_USER_EXTENSION + #define TX_THREAD_USER_EXTENSION + #endif /* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, - tx_thread_shell_entry, and tx_thread_terminate. */ -#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -void *_tx_iar_create_per_thread_tls_area(void); -void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); -void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); - -#ifdef TX_PORT_TRUSTZONE_NSC_ENABLE -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); \ - if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} -#else -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#endif -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); -#else + * tx_thread_shell_entry, and tx_thread_terminate. */ + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void * _tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void * tls_ptr); +void __iar_Initlocks(void); + + #define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr->tx_thread_iar_tls_pointer = \ + _tx_iar_create_per_thread_tls_area(); + + #ifdef TX_PORT_TRUSTZONE_NSC_ENABLE + #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area( \ + thread_ptr->tx_thread_iar_tls_pointer); \ + thread_ptr->tx_thread_iar_tls_pointer = TX_NULL;} while (0); \ + if (thread_ptr->tx_thread_secure_stack_context) {_tx_thread_secure_stack_free(thread_ptr);} + #else + #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area( \ + thread_ptr->tx_thread_iar_tls_pointer); \ + thread_ptr->tx_thread_iar_tls_pointer = TX_NULL;} while (0); + #endif + #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while (0); + #else + /* No IAR library support. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#ifdef TX_PORT_TRUSTZONE_NSC_ENABLE -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} -#else -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) -#endif -#endif + #define TX_THREAD_CREATE_EXTENSION(thread_ptr) + #ifdef TX_PORT_TRUSTZONE_NSC_ENABLE + #define TX_THREAD_DELETE_EXTENSION(thread_ptr) if (thread_ptr->tx_thread_secure_stack_context) { \ + _tx_thread_secure_stack_free(thread_ptr);} + #else + #define TX_THREAD_DELETE_EXTENSION(thread_ptr) + #endif + #endif + + #ifdef TX_PORT_TRUSTZONE_NSC_ENABLE -#ifdef TX_PORT_TRUSTZONE_NSC_ENABLE /* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */ -#define TX_TIMER_THREAD_SECURE_STACK_SIZE 256 -#define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE); -#endif + #define TX_TIMER_THREAD_SECURE_STACK_SIZE 256 + #define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, \ + TX_TIMER_THREAD_SECURE_STACK_SIZE); + #endif -#if __FPU_USED + #if __FPU_USED -#ifdef TX_MISRA_ENABLE + #ifdef TX_MISRA_ENABLE -ULONG _tx_misra_control_get(void); -void _tx_misra_control_set(ULONG value); -ULONG _tx_misra_fpccr_get(void); -void _tx_misra_vfp_touch(void); +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); -#endif + #endif /* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA - in order to ensure no lazy stacking will occur. */ - -#ifndef TX_MISRA_ENABLE - -#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ - ULONG _tx_vfp_state; \ - _tx_vfp_state = __get_CONTROL(); \ - _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ - __set_CONTROL(_tx_vfp_state); \ - } -#else - -#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ - ULONG _tx_vfp_state; \ - _tx_vfp_state = _tx_misra_control_get(); \ - _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ - _tx_misra_control_set(_tx_vfp_state); \ - } - -#endif + * in order to ensure no lazy stacking will occur. */ -/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. - If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush - the lazy FPU save, then restore the CONTROL.FPCA state. */ - -#ifndef TX_MISRA_ENABLE - -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ - ULONG _tx_system_state; \ - _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ - if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ - { \ - ULONG _tx_vfp_state; \ - _tx_vfp_state = __get_CONTROL(); \ - _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ - __set_CONTROL(_tx_vfp_state); \ - } \ - else \ - { \ - ULONG _tx_fpccr; \ - _tx_fpccr = *((ULONG *) 0xE000EF34); \ - _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ - if (_tx_fpccr == ((ULONG) 0x01)) \ - { \ - ULONG _tx_vfp_state; \ - _tx_vfp_state = __get_CONTROL(); \ - _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ - __asm volatile ("vmov.f32 s0, s0"); \ - if (_tx_vfp_state == ((ULONG) 0)) \ - { \ - _tx_vfp_state = __get_CONTROL(); \ - _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ - __set_CONTROL(_tx_vfp_state); \ - } \ - } \ - } \ - } -#else - -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ - ULONG _tx_system_state; \ - _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ - if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ - { \ - ULONG _tx_vfp_state; \ - _tx_vfp_state = _tx_misra_control_get(); \ - _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ - _tx_misra_control_set(_tx_vfp_state); \ - } \ - else \ - { \ - ULONG _tx_fpccr; \ - _tx_fpccr = _tx_misra_fpccr_get(); \ - _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ - if (_tx_fpccr == ((ULONG) 0x01)) \ - { \ - ULONG _tx_vfp_state; \ - _tx_vfp_state = _tx_misra_control_get(); \ - _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ - _tx_misra_vfp_touch(); \ - if (_tx_vfp_state == ((ULONG) 0)) \ - { \ - _tx_vfp_state = _tx_misra_control_get(); \ - _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ - _tx_misra_control_set(_tx_vfp_state); \ - } \ - } \ - } \ - } -#endif + #ifndef TX_MISRA_ENABLE -#else + #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ +} + #else -#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ +} -#endif + #endif +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + * If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + * this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + * the lazy FPU save, then restore the CONTROL.FPCA state. */ + + #ifndef TX_MISRA_ENABLE + + #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + __asm volatile ("vmov.f32 s0, s0"); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } \ + } \ + } \ +} + #else + + #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ +} + #endif -/* Define the ThreadX object creation extensions for the remaining objects. */ + #else -#ifndef TX_BLOCK_POOL_CREATE_EXTENSION -#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) -#endif -#ifndef TX_BYTE_POOL_CREATE_EXTENSION -#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) -#endif -#ifndef TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION -#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) -#endif -#ifndef TX_MUTEX_CREATE_EXTENSION -#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) -#endif -#ifndef TX_QUEUE_CREATE_EXTENSION -#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) -#endif -#ifndef TX_SEMAPHORE_CREATE_EXTENSION -#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) -#endif -#ifndef TX_TIMER_CREATE_EXTENSION -#define TX_TIMER_CREATE_EXTENSION(timer_ptr) -#endif + #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) + #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + #endif -/* Define the ThreadX object deletion extensions for the remaining objects. */ +/* Define the ThreadX object creation extensions for the remaining objects. */ -#ifndef TX_BLOCK_POOL_DELETE_EXTENSION -#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) -#endif -#ifndef TX_BYTE_POOL_DELETE_EXTENSION -#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) -#endif -#ifndef TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION -#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) -#endif -#ifndef TX_MUTEX_DELETE_EXTENSION -#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) -#endif -#ifndef TX_QUEUE_DELETE_EXTENSION -#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) -#endif -#ifndef TX_SEMAPHORE_DELETE_EXTENSION -#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) -#endif -#ifndef TX_TIMER_DELETE_EXTENSION -#define TX_TIMER_DELETE_EXTENSION(timer_ptr) -#endif + #ifndef TX_BLOCK_POOL_CREATE_EXTENSION + #define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) + #endif + #ifndef TX_BYTE_POOL_CREATE_EXTENSION + #define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) + #endif + #ifndef TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION + #define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) + #endif + #ifndef TX_MUTEX_CREATE_EXTENSION + #define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) + #endif + #ifndef TX_QUEUE_CREATE_EXTENSION + #define TX_QUEUE_CREATE_EXTENSION(queue_ptr) + #endif + #ifndef TX_SEMAPHORE_CREATE_EXTENSION + #define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) + #endif + #ifndef TX_TIMER_CREATE_EXTENSION + #define TX_TIMER_CREATE_EXTENSION(timer_ptr) + #endif +/* Define the ThreadX object deletion extensions for the remaining objects. */ + + #ifndef TX_BLOCK_POOL_DELETE_EXTENSION + #define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) + #endif + #ifndef TX_BYTE_POOL_DELETE_EXTENSION + #define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) + #endif + #ifndef TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION + #define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) + #endif + #ifndef TX_MUTEX_DELETE_EXTENSION + #define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) + #endif + #ifndef TX_QUEUE_DELETE_EXTENSION + #define TX_QUEUE_DELETE_EXTENSION(queue_ptr) + #endif + #ifndef TX_SEMAPHORE_DELETE_EXTENSION + #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) + #endif + #ifndef TX_TIMER_DELETE_EXTENSION + #define TX_TIMER_DELETE_EXTENSION(timer_ptr) + #endif /* Define the get system state macro. */ - -#ifndef TX_THREAD_GET_SYSTEM_STATE -#ifndef TX_MISRA_ENABLE -#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_IPSR()) -#else -ULONG _tx_misra_ipsr_get(VOID); -#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) -#endif -#endif + #ifndef TX_THREAD_GET_SYSTEM_STATE + #ifndef TX_MISRA_ENABLE + #define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_IPSR()) + #else +ULONG _tx_misra_ipsr_get(VOID); + + #define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) + #endif + #endif /* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value - indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h - for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always - zero after initialization for Cortex-M ports. */ + * indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + * for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + * zero after initialization for Cortex-M ports. */ -#ifndef TX_THREAD_SYSTEM_RETURN_CHECK -#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); -#endif + #ifndef TX_THREAD_SYSTEM_RETURN_CHECK + #define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); + #endif + + #ifdef TX_PORT_TRUSTZONE_NSC_ENABLE -#ifdef TX_PORT_TRUSTZONE_NSC_ENABLE /* Initialize secure stacks for threads calling secure functions. */ -extern void _tx_thread_secure_stack_initialize(void); -#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); -#endif +extern void _tx_thread_secure_stack_initialize(void); -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to - prevent early scheduling on Cortex-M parts. */ - -#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + #define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); + #endif +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + * prevent early scheduling on Cortex-M parts. */ -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the - lowest bit set. */ + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -#ifndef TX_DISABLE_INLINE +/* Determine if the ARM architecture has the CLZ instruction. This is available on + * architectures v5 and above. If available, redefine the macro for calculating the + * lowest bit set. */ -#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT)__CLZ(__RBIT((m))); + #ifndef TX_DISABLE_INLINE -#endif + #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __CLZ(__RBIT((m))); -#ifndef TX_PORT_MAX_IPL -#define TX_PORT_MAX_IPL (0) -#endif + #endif -/* Cortex-M4 and Cortex-M33 have BASEPRI, so BASEPRI can be used to allow high priority interrupts - * to preempt the scheduler. */ + #ifndef TX_PORT_MAX_IPL + #define TX_PORT_MAX_IPL (0) + #endif -#if (defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__)) && TX_PORT_MAX_IPL != 0 -#define TX_PORT_USE_BASEPRI -#endif +/* Cortex-M4, Cortex-M33, and Cortex-M85 have BASEPRI, so BASEPRI can be used to allow high priority interrupts + * to preempt the scheduler. */ + #if (defined(RENESAS_CORTEX_M4) || defined(RENESAS_CORTEX_M33) || defined(RENESAS_CORTEX_M85)) && TX_PORT_MAX_IPL != 0 + #define TX_PORT_USE_BASEPRI + #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value - present prior to the disable macro. In most cases, the save area macro - is used to define a local function save area for the disable and restore - macros. */ +/* Define ThreadX interrupt lockout and restore macros for protection on + * access of critical kernel information. The restore interrupt macro must + * restore the interrupt posture of the running thread prior to the value + * present prior to the disable macro. In most cases, the save area macro + * is used to define a local function save area for the disable and restore + * macros. */ /* The embedded assembler blocks are design so as to be inlinable by the - armlink linker inlining. This requires them to consist of either a - single 32-bit instruction, or either one or two 16-bit instructions - followed by a "BX lr". Note that to reduce the critical region size, the - 16-bit "CPSID i" instruction is preceeded by a 16-bit NOP */ + * armlink linker inlining. This requires them to consist of either a + * single 32-bit instruction, or either one or two 16-bit instructions + * followed by a "BX lr". Note that to reduce the critical region size, the + * 16-bit "CPSID i" instruction is preceeded by a 16-bit NOP */ + #ifdef TX_DISABLE_INLINE -#ifdef TX_DISABLE_INLINE +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT new_posture); -UINT _tx_thread_interrupt_disable(VOID); -VOID _tx_thread_interrupt_restore(UINT new_posture); + #define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); -#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); -#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + #else -#else + #define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + #ifdef TX_PORT_USE_BASEPRI -#ifdef TX_PORT_USE_BASEPRI - -#define TX_DISABLE interrupt_save = __get_BASEPRI(); \ - __set_BASEPRI(TX_PORT_MAX_IPL << (8U - __NVIC_PRIO_BITS)); -#define TX_RESTORE __set_BASEPRI(interrupt_save); + #define TX_DISABLE interrupt_save = __get_BASEPRI(); \ + __set_BASEPRI(TX_PORT_MAX_IPL << (8U - __NVIC_PRIO_BITS)); + #define TX_RESTORE __set_BASEPRI(interrupt_save); /* Do not use R0 and R1 because they are used for arguments. */ -#define TX_ENABLE_ASM "MRS R3, BASEPRI \n" \ - "MOV R2, #0 \n" \ - "MSR BASEPRI, R2 \n" -#define TX_RESTORE_ASM "MSR BASEPRI, R3 \n" + #define TX_ENABLE_ASM "MRS R3, BASEPRI \n" \ + "MOV R2, #0 \n" \ + "MSR BASEPRI, R2 \n" + #define TX_RESTORE_ASM "MSR BASEPRI, R3 \n" -#else + #else -/* Cortex-M23 does not have BASEPRI, so PRIMASK is used to save the interrupt state for +/* Cortex-M23 does not have BASEPRI, so PRIMASK is used to save the interrupt state for * critical sections. */ -#define TX_DISABLE interrupt_save = __get_PRIMASK(); \ - __disable_irq(); -#define TX_RESTORE __set_PRIMASK(interrupt_save); + #define TX_DISABLE interrupt_save = __get_PRIMASK(); \ + __disable_irq(); + #define TX_RESTORE __set_PRIMASK(interrupt_save); /* Do not use R0 and R1 because they are used for arguments. */ -#define TX_ENABLE_ASM "MRS R3, PRIMASK \n" \ - "CPSIE i \n" -#define TX_RESTORE_ASM "MSR PRIMASK, R3 \n" + #define TX_ENABLE_ASM "MRS R3, PRIMASK \n" \ + "CPSIE i \n" + #define TX_RESTORE_ASM "MSR PRIMASK, R3 \n" -#endif + #endif /* Redefine _tx_thread_system_return for improved performance. */ -#define _tx_thread_system_return _tx_thread_system_return_inline + #define _tx_thread_system_return _tx_thread_system_return_inline -static inline void _tx_thread_system_return_inline(void) +static inline void _tx_thread_system_return_inline (void) { /* Return to real scheduler via PendSV. Note that this routine is often * replaced with in-line assembly in tx_port.h to improved performance. */ @@ -633,54 +633,49 @@ static inline void _tx_thread_system_return_inline(void) if (__get_IPSR() == 0) { UINT interrupt_save; -#ifdef TX_PORT_USE_BASEPRI + #ifdef TX_PORT_USE_BASEPRI interrupt_save = __get_BASEPRI(); __set_BASEPRI(0U); __set_BASEPRI(interrupt_save); -#else + #else interrupt_save = __get_PRIMASK(); __enable_irq(); __set_PRIMASK(interrupt_save); -#endif + #endif } } -#endif - + #endif /* Define the interrupt lockout macros for each ThreadX object. */ -#define TX_BLOCK_POOL_DISABLE TX_DISABLE -#define TX_BYTE_POOL_DISABLE TX_DISABLE -#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE -#define TX_MUTEX_DISABLE TX_DISABLE -#define TX_QUEUE_DISABLE TX_DISABLE -#define TX_SEMAPHORE_DISABLE TX_DISABLE - + #define TX_BLOCK_POOL_DISABLE TX_DISABLE + #define TX_BYTE_POOL_DISABLE TX_DISABLE + #define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE + #define TX_MUTEX_DISABLE TX_DISABLE + #define TX_QUEUE_DISABLE TX_DISABLE + #define TX_SEMAPHORE_DISABLE TX_DISABLE /* Define prototypes specific to the ThreadX Cortex-M implementation. */ -VOID tx_isr_start(ULONG isr_id); -VOID tx_isr_end(ULONG isr_id); +VOID tx_isr_start(ULONG isr_id); +VOID tx_isr_end(ULONG isr_id); /* Define the version ID of ThreadX. This may be utilized by the application. */ -#ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M/CMSIS *"; -#else -#ifdef TX_MISRA_ENABLE -extern CHAR _tx_version_id[100]; -#else -extern CHAR _tx_version_id[]; -#endif -#endif - -#ifdef __cplusplus + #ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M/CMSIS *"; + #else + #ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; + #else +extern CHAR _tx_version_id[]; + #endif + #endif + + #ifdef __cplusplus } -#endif + #endif #endif - - - diff --git a/ra/fsp/src/rm_threadx_port/tx_port_vendor.h b/ra/fsp/src/rm_threadx_port/tx_port_vendor.h index 331bdcf47..7f9d2474a 100644 --- a/ra/fsp/src/rm_threadx_port/tx_port_vendor.h +++ b/ra/fsp/src/rm_threadx_port/tx_port_vendor.h @@ -45,7 +45,7 @@ extern "C" { #define TX_INCLUDE_USER_DEFINE_FILE #endif -#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) // CM33, CM85 +#if defined(RENESAS_CORTEX_M33) || defined(RENESAS_CORTEX_M85) #define TX_PORT_PSPLIM_PRESENT #elif (1 == __MPU_PRESENT) #define TX_PORT_VENDOR_STACK_MONITOR_ENABLE diff --git a/ra/fsp/src/rm_threadx_port/tx_thread_schedule.c b/ra/fsp/src/rm_threadx_port/tx_thread_schedule.c index cd8d73105..9d111b848 100644 --- a/ra/fsp/src/rm_threadx_port/tx_thread_schedule.c +++ b/ra/fsp/src/rm_threadx_port/tx_thread_schedule.c @@ -30,21 +30,21 @@ #include "tx_secure_interface.h" #endif -#ifdef __ARM_ARCH_7EM__ // CM4 +#if defined(RENESAS_CORTEX_M4) #define TX_PORT_ISA_CBZ_SUPPORTED #define TX_PORT_ISA_STMDB_LDMIA_SUPPORTED #define TX_PORT_ISA_THUMB2_SUB_ADD_SUPPORTED #define TX_PORT_ISA_IT_SUPPORTED #endif -#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) // CM33, CM85 +#if defined(RENESAS_CORTEX_M33) || defined(RENESAS_CORTEX_M85) #define TX_PORT_ISA_CBZ_SUPPORTED #define TX_PORT_ISA_STMDB_LDMIA_SUPPORTED #define TX_PORT_ISA_THUMB2_SUB_ADD_SUPPORTED #define TX_PORT_ISA_IT_SUPPORTED #endif -#ifdef __ARM_ARCH_8M_BASE__ // CM23 +#if defined(RENESAS_CORTEX_M23) #define TX_PORT_ISA_CBZ_SUPPORTED #endif diff --git a/ra/fsp/src/rm_wifi_da16xxx/rm_wifi_da16xxx.c b/ra/fsp/src/rm_wifi_da16xxx/rm_wifi_da16xxx.c index a0623cda4..7799dd577 100644 --- a/ra/fsp/src/rm_wifi_da16xxx/rm_wifi_da16xxx.c +++ b/ra/fsp/src/rm_wifi_da16xxx/rm_wifi_da16xxx.c @@ -25,6 +25,11 @@ #define WIFI_DA16XXX_RETURN_TEXT_OK "OK" #define WIFI_DA16XXX_RETURN_CONN_TEXT "+WFJAP:1" +#define WIFI_DA16XXX_MIN_SDK_VER_MAJOR (3) +#define WIFI_DA16XXX_MIN_SDK_VER_MINOR (2) +#define WIFI_DA16XXX_MIN_SDK_VER_REVISION (6) +#define WIFI_DA16XXX_MIN_SDK_VER_ENGI (0) + /* Predefined timeout values */ #define WIFI_DA16XXX_TIMEOUT_1MS (1) #define WIFI_DA16XXX_TIMEOUT_3MS (3) @@ -49,6 +54,8 @@ /* Minimum string size for getting local time string */ #define WIFI_DA16XXX_LOCAL_TIME_STR_SIZE (25) +#define WIFI_DA16XXX_IPV4_MAX_LENGTH (15) + #define HOURS_IN_SECONDS (3600) #if (BSP_CFG_RTOS == 2) /* FreeRTOS */ /* Socket Types supported */ @@ -128,6 +135,11 @@ static bool rm_wifi_da16xxx_handle_incoming_socket_data(da16xxx_socket_t * pSock #endif +#if (WIFI_DA16XXX_CFG_CHECK_SDK_VERSION) +static fsp_err_t rm_wifi_da16xxx_check_sdk_version(void); + +#endif + #if (1 == WIFI_DA16XXX_CFG_SNTP_ENABLE) static fsp_err_t rm_wifi_da16xxx_sntp_service_init(wifi_da16xxx_instance_ctrl_t * const p_instance_ctrl); @@ -177,6 +189,11 @@ fsp_err_t rm_wifi_da16xxx_open (wifi_da16xxx_cfg_t const * const p_cfg) err = p_transport_instance->p_api->open(p_transport_instance->p_ctrl, p_transport_instance->p_cfg); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#if (WIFI_DA16XXX_CFG_CHECK_SDK_VERSION) + err = rm_wifi_da16xxx_check_sdk_version(); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + /* Set AP mode */ atcmd.p_at_cmd_string = (uint8_t *) "AT+WFMODE=0\r"; atcmd.at_cmd_string_length = 0; @@ -1668,24 +1685,31 @@ static fsp_err_t rm_wifi_da16xxx_sntp_service_init (wifi_da16xxx_instance_ctrl_t { fsp_err_t err = FSP_ERR_INTERNAL; uint8_t ip_address_sntp_server[4] = {0, 0, 0, 0}; - int32_t err_scan; + int err_scan = 0; + char * token; + char sntp_ip[WIFI_DA16XXX_IPV4_MAX_LENGTH + 1]; + + /* Check if the input IP address length exceeds the expected length */ + FSP_ERROR_RETURN(strlen( + (char *) p_instance_ctrl->p_wifi_da16xxx_cfg->sntp_server_ip) < WIFI_DA16XXX_IPV4_MAX_LENGTH, + FSP_ERR_INVALID_ARGUMENT); /* Set the SNTP server IP address */ - err_scan = + strncpy(sntp_ip, (char *) p_instance_ctrl->p_wifi_da16xxx_cfg->sntp_server_ip, WIFI_DA16XXX_IPV4_MAX_LENGTH + 1); + token = strtok(sntp_ip, "."); - // NOLINTNEXTLINE(cert-err34-c) Disable warning about the use of sscanf - sscanf((const char *) p_instance_ctrl->p_wifi_da16xxx_cfg->sntp_server_ip, - "%u.%u.%u.%u,", - (unsigned int *) &ip_address_sntp_server[0], - (unsigned int *) &ip_address_sntp_server[1], - (unsigned int *) &ip_address_sntp_server[2], - (unsigned int *) &ip_address_sntp_server[3]); - if (4 == err_scan) + while ((token != NULL) && (err_scan < 4)) { - /* Configure the SNTP Server Address */ - err = RM_WIFI_DA16XXX_SntpServerIpAddressSet((uint8_t *) ip_address_sntp_server); + ip_address_sntp_server[err_scan++] = (uint8_t) strtol(token, NULL, 10); + token = strtok(NULL, "."); } + /* Check if the input IP address length did not contain 4 segments */ + FSP_ERROR_RETURN(4 == err_scan, FSP_ERR_INVALID_ARGUMENT); + + /* Configure the SNTP Server Address */ + err = RM_WIFI_DA16XXX_SntpServerIpAddressSet((uint8_t *) ip_address_sntp_server); + if (FSP_SUCCESS == err) { /* Enable/disable the SNTP clinet */ @@ -1958,6 +1982,76 @@ fsp_err_t RM_WIFI_DA16XXX_LocalTimeGet (uint8_t * p_local_time, uint32_t size_st return ret; } +/*******************************************************************************************************************//** + * Sends any AT command compatible with the DA16XXX module. Provide optional buffer to receive the response. + * + * @param[in] at_string Input AT command string from the user. + * @param[in] response_buffer Optional buffer for receiving the response. + * @param[in] length Size of optional buffer. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_ARGUMENT Input was not a valid AT command. + **********************************************************************************************************************/ +fsp_err_t RM_WIFI_DA16XXX_GenericAtSendRcv (char const * const at_string, char * const response_buffer, uint32_t length) +{ + uint32_t mutex_flag; + fsp_err_t ret; + wifi_da16xxx_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_da16xxx_instance; + at_transport_da16xxx_instance_t const * p_transport_instance = + p_instance_ctrl->p_wifi_da16xxx_cfg->p_transport_instance; + at_transport_da16xxx_data_t atcmd; + +#if (WIFI_DA16XXX_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(NULL != at_string, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Check if the user input string is a valid AT command e.g. ATE, AT+SDKVER */ + FSP_ERROR_RETURN((0 == strncmp(at_string, "?", 1)) || + (0 == strncmp(at_string, "help", 4)) || + (0 == strncmp(at_string, "AT", 2)), + FSP_ERR_INVALID_ARGUMENT); + + /* Take mutexes */ + mutex_flag = (WIFI_DA16XXX_MUTEX_TX | WIFI_DA16XXX_MUTEX_RX); + FSP_ERROR_RETURN(FSP_SUCCESS == p_transport_instance->p_api->takeMutex(p_transport_instance->p_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + snprintf((char *) p_instance_ctrl->cmd_tx_buff, sizeof(p_instance_ctrl->cmd_tx_buff), "%s\r", at_string); + + atcmd.p_at_cmd_string = (uint8_t *) p_instance_ctrl->cmd_tx_buff; + atcmd.at_cmd_string_length = 0; + atcmd.response_buffer_size = sizeof(p_instance_ctrl->cmd_rx_buff); + atcmd.timeout_ms = WIFI_DA16XXX_TIMEOUT_500MS; + atcmd.p_expect_code = WIFI_DA16XXX_RETURN_TEXT_OK; + atcmd.comm_ch_id = p_instance_ctrl->curr_socket; + + if (response_buffer != NULL) + { + memset(response_buffer, 0, length); + + atcmd.p_response_buffer = (uint8_t *) response_buffer; + } + else + { + memset((char *) p_instance_ctrl->cmd_rx_buff, 0, sizeof(p_instance_ctrl->cmd_rx_buff)); + + atcmd.p_response_buffer = p_instance_ctrl->cmd_rx_buff; + } + + ret = p_transport_instance->p_api->atCommandSend(p_transport_instance->p_ctrl, &atcmd); + + p_transport_instance->p_api->giveMutex(p_transport_instance->p_ctrl, mutex_flag); + + FSP_ERROR_RETURN(FSP_SUCCESS == ret, FSP_ERR_WIFI_INIT_FAILED); + + return ret; +} + /*******************************************************************************************************************//** * @} (end addtogroup WIFI_DA16XXX) **********************************************************************************************************************/ @@ -1996,6 +2090,78 @@ bool rm_wifi_da16xxx_callback (at_transport_da16xxx_callback_args_t * p_args) return ret; } +#if (WIFI_DA16XXX_CFG_CHECK_SDK_VERSION) + +/*******************************************************************************************************************//** + * Checks the minimum SDK version of the DA16XXX module is valid + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_INVALID_DATA Function did not return a valid SDK version. + **********************************************************************************************************************/ +static fsp_err_t rm_wifi_da16xxx_check_sdk_version (void) +{ + fsp_err_t ret = FSP_SUCCESS; + + wifi_da16xxx_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_da16xxx_instance; + at_transport_da16xxx_instance_t const * p_transport_instance = + p_instance_ctrl->p_wifi_da16xxx_cfg->p_transport_instance; + at_transport_da16xxx_data_t atcmd; + + /* Get SDK version */ + atcmd.p_at_cmd_string = (uint8_t *) "AT+SDKVER\r"; + atcmd.at_cmd_string_length = 0; + atcmd.p_response_buffer = p_instance_ctrl->cmd_rx_buff; + atcmd.response_buffer_size = sizeof(p_instance_ctrl->cmd_rx_buff); + atcmd.timeout_ms = WIFI_DA16XXX_TIMEOUT_500MS; + atcmd.p_expect_code = WIFI_DA16XXX_RETURN_TEXT_OK; + atcmd.comm_ch_id = p_instance_ctrl->curr_socket; + ret = p_transport_instance->p_api->atCommandSend(p_transport_instance->p_ctrl, &atcmd); + + FSP_ERROR_RETURN(FSP_SUCCESS == ret, FSP_ERR_WIFI_INIT_FAILED); + + char * ptr = (char *) p_instance_ctrl->cmd_rx_buff; + + /* Check that version data exists */ + FSP_ERROR_RETURN(0 == strncmp(ptr, "\r\n+SDKVER:", 10), FSP_ERR_INVALID_DATA); + + /* Advance pointer to the version number */ + ptr = ptr + strlen("\r\n+SDKVER:"); + + int version[4] = {0}; + + /* Extracting major, minor, revision, and engineering numbers from the current version string */ + ptr = strtok(ptr, "."); + + for (int i = 0; i < 3; i++) + { + FSP_ERROR_RETURN((ptr != NULL), FSP_ERR_INVALID_DATA); + + version[i] = strtol(ptr, NULL, 10); + + ptr = strtok(NULL, "."); + } + + /* Extracting major, minor, revision, and engineering numbers from the minimum version string */ + + /* Checking if each part of the version string is greater than or equal to the minimum version */ + FSP_ERROR_RETURN(((version[0] > WIFI_DA16XXX_MIN_SDK_VER_MAJOR) || + ((version[0] == WIFI_DA16XXX_MIN_SDK_VER_MAJOR) && + (version[1] > WIFI_DA16XXX_MIN_SDK_VER_MINOR)) || + ((version[0] == WIFI_DA16XXX_MIN_SDK_VER_MAJOR) && + (version[1] == WIFI_DA16XXX_MIN_SDK_VER_MINOR) && + (version[2] > WIFI_DA16XXX_MIN_SDK_VER_REVISION)) || + ((version[0] == WIFI_DA16XXX_MIN_SDK_VER_MAJOR) && + (version[1] == WIFI_DA16XXX_MIN_SDK_VER_MINOR) && + (version[2] == WIFI_DA16XXX_MIN_SDK_VER_REVISION) && + (version[3] >= WIFI_DA16XXX_MIN_SDK_VER_ENGI))), + FSP_ERR_INVALID_DATA); + + return ret; +} + +#endif + #if (BSP_CFG_RTOS == 2) /* FreeRTOS */ /*******************************************************************************************************************//** diff --git a/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c b/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c index b82d038ab..36384da02 100644 --- a/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c +++ b/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c @@ -22,24 +22,35 @@ #else // Azure RTOS #include "tx_api.h" #endif -#if (BSP_FEATURE_SCI_VERSION == 2U) - #include "r_sci_b_uart.h" +#if (0 == BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK) + #if (BSP_FEATURE_SCI_VERSION == 2U) + #include "r_sci_b_uart.h" typedef sci_b_uart_instance_ctrl_t rm_wifi_onchip_silex_uart_instance_ctrl_t; typedef sci_b_uart_extended_cfg_t rm_wifi_onchip_silex_uart_extended_cfg_t; typedef sci_b_baud_setting_t rm_wifi_onchip_silex_baud_setting_t; - #define RM_WIFI_ONCHIP_SILEX_SCI_UART_FLOW_CONTROL_RTS SCI_B_UART_FLOW_CONTROL_RTS - #define RM_WIFI_ONCHIP_SILEX_SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS SCI_B_UART_FLOW_CONTROL_HARDWARE_CTSRTS + #define RM_WIFI_ONCHIP_SILEX_SCI_UART_FLOW_CONTROL_RTS SCI_B_UART_FLOW_CONTROL_RTS + #define RM_WIFI_ONCHIP_SILEX_SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS SCI_B_UART_FLOW_CONTROL_HARDWARE_CTSRTS static fsp_err_t (* p_sci_uart_baud_calculate)(uint32_t, bool, uint32_t, struct st_sci_b_baud_setting_t * const) = &R_SCI_B_UART_BaudCalculate; -#else - #include "r_sci_uart.h" + #else + #include "r_sci_uart.h" typedef sci_uart_instance_ctrl_t rm_wifi_onchip_silex_uart_instance_ctrl_t; typedef sci_uart_extended_cfg_t rm_wifi_onchip_silex_uart_extended_cfg_t; typedef baud_setting_t rm_wifi_onchip_silex_baud_setting_t; - #define RM_WIFI_ONCHIP_SILEX_SCI_UART_FLOW_CONTROL_RTS SCI_UART_FLOW_CONTROL_RTS - #define RM_WIFI_ONCHIP_SILEX_SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS + #define RM_WIFI_ONCHIP_SILEX_SCI_UART_FLOW_CONTROL_RTS SCI_UART_FLOW_CONTROL_RTS + #define RM_WIFI_ONCHIP_SILEX_SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS static fsp_err_t (* p_sci_uart_baud_calculate)(uint32_t, bool, uint32_t, baud_setting_t * const) = &R_SCI_UART_BaudCalculate; + #endif +#else + #include "r_sau_uart.h" +typedef sau_uart_instance_ctrl_t rm_wifi_onchip_silex_uart_instance_ctrl_t; +typedef sau_uart_extended_cfg_t rm_wifi_onchip_silex_uart_extended_cfg_t; +typedef sau_uart_baudrate_setting_t rm_wifi_onchip_silex_baud_setting_t; +static fsp_err_t (* p_sau_uart_baud_calculate)(sau_uart_instance_ctrl_t * const, uint32_t, + sau_uart_baudrate_setting_t * const) = &R_SAU_UART_BaudCalculate; +static fsp_err_t (* p_sau_uart_baud_set)(uart_ctrl_t * const, const void * const) = &R_SAU_UART_BaudSet; + #endif /*! \cond PRIVATE */ @@ -194,11 +205,15 @@ typedef enum /* Unique number for WIFI Open status */ #define WIFI_OPEN (0x57495749ULL) // Is "WIFI" in ASCII -/* Unique number for SCI Open Status */ -#if (BSP_FEATURE_SCI_VERSION == 2U) - #define SCIU_OPEN (0x53434942U) // Is "SCIB" in ASCII +/* Unique number for SCI/SAU Open Status */ +#if (0 == BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK) + #if (BSP_FEATURE_SCI_VERSION == 2U) + #define SCIU_OPEN (0x53434942U) // Is "SCIB" in ASCII + #else + #define SCIU_OPEN (0x53434955U) // Is "SCIU" in ASCII + #endif #else - #define SCIU_OPEN (0x53434955U) // Is "SCIU" in ASCII + #define SAUU_OPEN (0x53415555U) // Is "SAUU" in ASCII #endif /*********************************************************************************************************************** @@ -294,20 +309,25 @@ static wifi_onchip_silex_instance_ctrl_t g_rm_wifi_onchip_silex_instance; static rm_wifi_onchip_silex_baud_setting_t g_baud_setting_115200 = { -#if (2U == BSP_FEATURE_SCI_VERSION) +#if (0 == BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK) + #if (2U == BSP_FEATURE_SCI_VERSION) .baudrate_bits_b.brme = 0, .baudrate_bits_b.abcse = 0, .baudrate_bits_b.abcs = 0, .baudrate_bits_b.bgdm = 0, .baudrate_bits_b.brr = 0, .baudrate_bits_b.mddr = 0, -#else + #else .semr_baudrate_bits_b.brme = 0, .semr_baudrate_bits_b.abcse = 0, .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 0, .brr = 0, .mddr = 0, + #endif +#else + .prs = 0, + .stclk = 0, #endif }; @@ -530,6 +550,7 @@ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg /* Create memory copy of uart configuration and update with new extended configuration structure. */ memcpy((void *) &uart0_cfg_115200, p_instance_ctrl->uart_instance_objects[0]->p_cfg, sizeof(uart_cfg_t)); p_uart = p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_SILEX_UART_INITIAL_PORT]; +#if (0 == BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK) (*p_sci_uart_baud_calculate)(WIFI_ONCHIP_SILEX_DEFAULT_BAUDRATE, WIFI_ONCHIP_SILEX_DEFAULT_MODULATION, WIFI_ONCHIP_SILEX_DEFAULT_ERROR, &g_baud_setting_115200); @@ -549,6 +570,22 @@ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg } FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_FAILED); +#else + + /* Open uart first, then set its baud to 112500 at run timing and no hardware flow control */ + err = p_uart->p_api->open(p_uart->p_ctrl, &uart0_cfg_115200); + + if (FSP_SUCCESS != err) + { + rm_wifi_onchip_silex_cleanup_open(p_instance_ctrl); + } + + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_FAILED); + + (*p_sau_uart_baud_calculate)(p_uart->p_ctrl, WIFI_ONCHIP_SILEX_DEFAULT_BAUDRATE, &g_baud_setting_115200); + + (*p_sau_uart_baud_set)(p_uart->p_ctrl, &g_baud_setting_115200); +#endif #if (BSP_CFG_RTOS == 2) // FreeRTOS vTaskDelay(pdMS_TO_TICKS(WIFI_ONCHIP_SILEX_TIMEOUT_100MS)); @@ -587,6 +624,7 @@ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg strncat((char *) p_temp_buff, g_wifi_onchip_silex_uart_cmd_baud, 10); strncat((char *) p_temp_buff, ",,,,", 5); +#if (0 == BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK) rm_wifi_onchip_silex_uart_extended_cfg_t * ext_cfg = (rm_wifi_onchip_silex_uart_extended_cfg_t *) p_instance_ctrl->uart_instance_objects[ WIFI_ONCHIP_SILEX_UART_INITIAL_PORT]->p_cfg->p_extend; @@ -601,6 +639,10 @@ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg strncat((char *) p_temp_buff, "n\r", 3); } +#else + strncat((char *) p_temp_buff, "n\r", 3); +#endif + /* Send reconfiguration AT command to wifi module */ err = rm_wifi_onchip_silex_send_basic(p_instance_ctrl, p_instance_ctrl->curr_cmd_port, @@ -1569,6 +1611,7 @@ fsp_err_t rm_wifi_onchip_silex_scan (WIFIScanResult_t * p_results, uint32_t maxN { break; } + #if (BSP_CFG_RTOS == 2) // FreeRTOS rm_wifi_onchip_silex_send_scan(p_instance_ctrl, p_instance_ctrl->curr_cmd_port, @@ -2843,15 +2886,26 @@ static void rm_wifi_onchip_silex_cleanup_open (wifi_onchip_silex_instance_ctrl_t #endif uart_instance_t * p_uart = p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_SILEX_UART_INITIAL_PORT]; +#if (0 == BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK) if (SCIU_OPEN == ((rm_wifi_onchip_silex_uart_instance_ctrl_t *) p_uart->p_ctrl)->open) +#else + if (SAUU_OPEN == ((rm_wifi_onchip_silex_uart_instance_ctrl_t *) p_uart->p_ctrl)->open) +#endif { p_uart->p_api->close(p_uart->p_ctrl); } - p_uart = p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_SILEX_UART_SECOND_PORT]; - if (SCIU_OPEN == ((rm_wifi_onchip_silex_uart_instance_ctrl_t *) p_uart->p_ctrl)->open) + if (2 == p_instance_ctrl->num_uarts) { - p_uart->p_api->close(p_uart->p_ctrl); + p_uart = p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_SILEX_UART_SECOND_PORT]; +#if (0 == BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK) + if (SCIU_OPEN == ((rm_wifi_onchip_silex_uart_instance_ctrl_t *) p_uart->p_ctrl)->open) +#else + if (SAUU_OPEN == ((rm_wifi_onchip_silex_uart_instance_ctrl_t *) p_uart->p_ctrl)->open) +#endif + { + p_uart->p_api->close(p_uart->p_ctrl); + } } } @@ -3506,7 +3560,7 @@ static fsp_err_t rm_wifi_onchip_silex_change_socket_index (wifi_onchip_silex_ins { if (socket_no != p_instance_ctrl->curr_socket_index) // Only attempt change if socket number is different than current. { -#if (BSP_CFG_RTOS == 1) +#if ((BSP_CFG_RTOS == 1) && (0 == BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK)) rm_wifi_onchip_silex_uart_instance_ctrl_t * p_data_port_uart_ctrl = (rm_wifi_onchip_silex_uart_instance_ctrl_t *) p_instance_ctrl->uart_instance_objects[p_instance_ctrl-> curr_data_port]-> @@ -3565,7 +3619,7 @@ static fsp_err_t rm_wifi_onchip_silex_change_socket_index (wifi_onchip_silex_ins continue; } -#if (BSP_CFG_RTOS == 1) +#if ((BSP_CFG_RTOS == 1) && (0 == BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK)) /* Clear flow control in order to resume data over data port. */ R_BSP_PinWrite(p_data_port_uart_ctrl->flow_pin, BSP_IO_LEVEL_LOW);